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VREFBUF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

VREFBUF_CSR (CSR)

VREFBUF_CCR (CCR)


VREFBUF_CSR (CSR)

VREFBUF control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CSR VREFBUF_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENVR HIZ VRS VRR

ENVR : Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Internal voltage reference mode disable (external voltage reference mode).

0x1 : B_0x1

Internal voltage reference mode (reference buffer enable or hold mode) enable.

End of enumeration elements list.

HIZ : High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

VREF+ pin is internally connected to the voltage reference buffer output.

0x1 : B_0x1

VREF+ pin is high impedance.

End of enumeration elements list.

VRS : Voltage reference scale This bit selects the value generated by the voltage reference buffer.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0x0 : B_0x0

Voltage reference set to VREF_OUT1 (around 2.048 V).

0x1 : B_0x1

Voltage reference set to VREF_OUT2 (around 2.5 V).

End of enumeration elements list.

VRR : Voltage reference buffer ready
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0x0 : B_0x0

the voltage reference buffer output is not ready.

0x1 : B_0x1

the voltage reference buffer output reached the requested level.

End of enumeration elements list.


VREFBUF_CCR (CCR)

VREFBUF calibration control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREFBUF_CCR VREFBUF_CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIM

TRIM : Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows the tuning of the internal reference buffer voltage.
bits : 0 - 5 (6 bit)
access : read-write



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