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DBGMCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IDCODE

APB2FZR

CR

APB1LFZR

APB1HFZR


IDCODE

DBGMCU_IDCODE
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IDCODE IDCODE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEV_ID REV_ID

DEV_ID : Device identifier
bits : 0 - 11 (12 bit)

REV_ID : Revision identifie
bits : 16 - 31 (16 bit)


APB2FZR

Debug MCU APB2 freeze register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2FZR APB2FZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM1_STOP DBG_TIM8_STOP DBG_TIM15_STOP DBG_TIM16_STOP DBG_TIM17_STOP

DBG_TIM1_STOP : TIM1 counter stopped when core is halted
bits : 11 - 11 (1 bit)

DBG_TIM8_STOP : TIM8 stop in debug
bits : 13 - 13 (1 bit)

DBG_TIM15_STOP : TIM15 counter stopped when core is halted
bits : 16 - 16 (1 bit)

DBG_TIM16_STOP : TIM16 counter stopped when core is halted
bits : 17 - 17 (1 bit)

DBG_TIM17_STOP : DBG_TIM17_STOP
bits : 18 - 18 (1 bit)


CR

Debug MCU configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_STOP DBG_STANDBY TRACE_IOEN TRACE_EN TRACE_MODE

DBG_STOP : Debug Stop mode
bits : 1 - 1 (1 bit)

DBG_STANDBY : Debug Standby mode
bits : 2 - 2 (1 bit)

TRACE_IOEN : Trace pin assignment control
bits : 4 - 4 (1 bit)

TRACE_EN : trace port and clock enable
bits : 5 - 5 (1 bit)

TRACE_MODE : Trace pin assignment control
bits : 6 - 7 (2 bit)


APB1LFZR

Debug MCU APB1 freeze register1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LFZR APB1LFZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_TIM2_STOP DBG_TIM3_STOP DBG_TIM4_STOP DBG_TIM5_STOP DBG_TIM6_STOP DBG_TIM7_STOP DBG_RTC_STOP DBG_WWDG_STOP DBG_IWDG_STOP DBG_I2C1_STOP DBG_I2C2_STOP DBG_I2C3_STOP DBG_LPTIM1_STOP

DBG_TIM2_STOP : TIM2 counter stopped when core is halted
bits : 0 - 0 (1 bit)

DBG_TIM3_STOP : TIM3 stop in debug
bits : 1 - 1 (1 bit)

DBG_TIM4_STOP : TIM4 stop in debug
bits : 2 - 2 (1 bit)

DBG_TIM5_STOP : TIM5 stop in debug
bits : 3 - 3 (1 bit)

DBG_TIM6_STOP : TIM6 counter stopped when core is halted
bits : 4 - 4 (1 bit)

DBG_TIM7_STOP : TIM7 counter stopped when core is halted
bits : 5 - 5 (1 bit)

DBG_RTC_STOP : RTC counter stopped when core is halted
bits : 10 - 10 (1 bit)

DBG_WWDG_STOP : Window watchdog counter stopped when core is halted
bits : 11 - 11 (1 bit)

DBG_IWDG_STOP : Independent watchdog counter stopped when core is halted
bits : 12 - 12 (1 bit)

DBG_I2C1_STOP : I2C1 SMBUS timeout counter stopped when core is halted
bits : 21 - 21 (1 bit)

DBG_I2C2_STOP : I2C2 SMBUS timeout counter stopped when core is halted
bits : 22 - 22 (1 bit)

DBG_I2C3_STOP : I2C3 SMBUS timeout counter stopped when core is halted
bits : 23 - 23 (1 bit)

DBG_LPTIM1_STOP : LPTIM1 counter stopped when core is halted
bits : 31 - 31 (1 bit)


APB1HFZR

Debug MCU APB1 freeze register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1HFZR APB1HFZR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_I2C4_STOP DBG_LPTIM2_STOP DBG_LPTIM3_STOP

DBG_I2C4_STOP : I2C4 stop in debug
bits : 1 - 1 (1 bit)

DBG_LPTIM2_STOP : LPTIM2 counter stopped when core is halted
bits : 5 - 5 (1 bit)

DBG_LPTIM3_STOP : LPTIM3 stop in debug
bits : 6 - 6 (1 bit)



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