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FDCAN

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC00 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FDCAN_CREL

FDCAN_TEST

FDCAN_CKDIV

FDCAN_RWD

FDCAN_CCCR

FDCAN_NBTP

FDCAN_TSCC

FDCAN_TSCV

FDCAN_TOCC

FDCAN_TOCV

FDCAN_ENDN

FDCAN_ECR

FDCAN_PSR

FDCAN_TDCR

FDCAN_IR

FDCAN_IE

FDCAN_ILS

FDCAN_ILE

FDCAN_RXGFC

FDCAN_XIDAM

FDCAN_HPMS

FDCAN_RXF0S

FDCAN_RXF0A

FDCAN_RXF1S

FDCAN_RXF1A

FDCAN_DBTP

FDCAN_TXBC

FDCAN_TXFQS

FDCAN_TXBRP

FDCAN_TXBAR

FDCAN_TXBCR

FDCAN_TXBTO

FDCAN_TXBCF

FDCAN_TXBTIE

FDCAN_TXBCIE

FDCAN_TXEFS

FDCAN_TXEFA


FDCAN_CREL

FDCAN Core Release Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_CREL FDCAN_CREL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY MON YEAR SUBSTEP STEP REL

DAY : Timestamp Day
bits : 0 - 7 (8 bit)

MON : Timestamp Month
bits : 8 - 15 (8 bit)

YEAR : Timestamp Year
bits : 16 - 19 (4 bit)

SUBSTEP : Sub-step of Core release
bits : 20 - 23 (4 bit)

STEP : Step of Core release
bits : 24 - 27 (4 bit)

REL : Core release
bits : 28 - 31 (4 bit)


FDCAN_TEST

FDCAN Test Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TEST FDCAN_TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBCK TX RX

LBCK : Loop Back mode
bits : 4 - 4 (1 bit)
access : read-write

TX : Loop Back mode
bits : 5 - 6 (2 bit)
access : read-write

RX : Control of Transmit Pin
bits : 7 - 7 (1 bit)
access : read-only


FDCAN_CKDIV

FDCAN TT Trigger Memory Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_CKDIV FDCAN_CKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIV

PDIV : PDIV
bits : 0 - 3 (4 bit)


FDCAN_RWD

FDCAN RAM Watchdog Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RWD FDCAN_RWD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDC WDV

WDC : Watchdog configuration
bits : 0 - 7 (8 bit)
access : read-write

WDV : Watchdog value
bits : 8 - 15 (8 bit)
access : read-only


FDCAN_CCCR

FDCAN CC Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_CCCR FDCAN_CCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT CCE ASM CSA CSR MON DAR TEST FDOE BSE PXHD EFBI TXP NISO

INIT : Initialization
bits : 0 - 0 (1 bit)

CCE : Configuration Change Enable
bits : 1 - 1 (1 bit)

ASM : ASM Restricted Operation Mode
bits : 2 - 2 (1 bit)

CSA : Clock Stop Acknowledge
bits : 3 - 3 (1 bit)

CSR : Clock Stop Request
bits : 4 - 4 (1 bit)

MON : Bus Monitoring Mode
bits : 5 - 5 (1 bit)

DAR : Disable Automatic Retransmission
bits : 6 - 6 (1 bit)

TEST : Test Mode Enable
bits : 7 - 7 (1 bit)

FDOE : FD Operation Enable
bits : 8 - 8 (1 bit)

BSE : FDCAN Bit Rate Switching
bits : 9 - 9 (1 bit)

PXHD : Protocol Exception Handling Disable
bits : 12 - 12 (1 bit)

EFBI : Edge Filtering during Bus Integration
bits : 13 - 13 (1 bit)

TXP : TXP
bits : 14 - 14 (1 bit)

NISO : Non ISO Operation
bits : 15 - 15 (1 bit)


FDCAN_NBTP

FDCAN Nominal Bit Timing and Prescaler Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_NBTP FDCAN_NBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSEG2 NTSEG1 NBRP NSJW

TSEG2 : Nominal Time segment after sample point
bits : 0 - 6 (7 bit)

NTSEG1 : Nominal Time segment before sample point
bits : 8 - 15 (8 bit)

NBRP : Bit Rate Prescaler
bits : 16 - 24 (9 bit)

NSJW : NSJW: Nominal (Re)Synchronization Jump Width
bits : 25 - 31 (7 bit)


FDCAN_TSCC

FDCAN Timestamp Counter Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TSCC FDCAN_TSCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSS TCP

TSS : Timestamp Select
bits : 0 - 1 (2 bit)

TCP : Timestamp Counter Prescaler
bits : 16 - 19 (4 bit)


FDCAN_TSCV

FDCAN Timestamp Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TSCV FDCAN_TSCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSC

TSC : Timestamp Counter
bits : 0 - 15 (16 bit)


FDCAN_TOCC

FDCAN Timeout Counter Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TOCC FDCAN_TOCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETOC TOS TOP

ETOC : Enable Timeout Counter
bits : 0 - 0 (1 bit)

TOS : Timeout Select
bits : 1 - 2 (2 bit)

TOP : Timeout Period
bits : 16 - 31 (16 bit)


FDCAN_TOCV

FDCAN Timeout Counter Value Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TOCV FDCAN_TOCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOC

TOC : Timeout Counter
bits : 0 - 15 (16 bit)


FDCAN_ENDN

FDCAN Core Release Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ENDN FDCAN_ENDN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETV

ETV : Endiannes Test Value
bits : 0 - 31 (32 bit)


FDCAN_ECR

FDCAN Error Counter Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ECR FDCAN_ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC REC RP CEL

TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read-only

REC : Receive Error Counter
bits : 8 - 14 (7 bit)
access : read-only

RP : Receive Error Passive
bits : 15 - 15 (1 bit)
access : read-write

CEL : AN Error Logging
bits : 16 - 23 (8 bit)
access : read-write


FDCAN_PSR

FDCAN Protocol Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_PSR FDCAN_PSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC ACT EP EW BO DLEC RESI RBRS REDL PXE TDCV

LEC : Last Error Code
bits : 0 - 2 (3 bit)
access : read-write

ACT : Activity
bits : 3 - 4 (2 bit)
access : read-only

EP : Error Passive
bits : 5 - 5 (1 bit)
access : read-only

EW : Warning Status
bits : 6 - 6 (1 bit)
access : read-only

BO : Bus_Off Status
bits : 7 - 7 (1 bit)
access : read-only

DLEC : Data Last Error Code
bits : 8 - 10 (3 bit)
access : read-write

RESI : ESI flag of last received FDCAN Message
bits : 11 - 11 (1 bit)
access : read-write

RBRS : BRS flag of last received FDCAN Message
bits : 12 - 12 (1 bit)
access : read-write

REDL : Received FDCAN Message
bits : 13 - 13 (1 bit)
access : read-write

PXE : Protocol Exception Event
bits : 14 - 14 (1 bit)
access : read-write

TDCV : Transmitter Delay Compensation Value
bits : 16 - 22 (7 bit)
access : read-only


FDCAN_TDCR

FDCAN Transmitter Delay Compensation Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TDCR FDCAN_TDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDCF TDCO

TDCF : Transmitter Delay Compensation Filter Window Length
bits : 0 - 6 (7 bit)

TDCO : Transmitter Delay Compensation Offset
bits : 8 - 14 (7 bit)


FDCAN_IR

FDCAN Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_IR FDCAN_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0N RF0F RF0L RF1N RF1F RF1L HPM TC TCF TFE TEFN TEFF TEFL TSW MRAF TOO ELO EP EW BO WDI PEA PED ARA

RF0N : RF0N
bits : 0 - 0 (1 bit)

RF0F : RF0F
bits : 1 - 1 (1 bit)

RF0L : RF0L
bits : 2 - 2 (1 bit)

RF1N : RF1N
bits : 3 - 3 (1 bit)

RF1F : RF1F
bits : 4 - 4 (1 bit)

RF1L : RF1L
bits : 5 - 5 (1 bit)

HPM : HPM
bits : 6 - 6 (1 bit)

TC : TC
bits : 7 - 7 (1 bit)

TCF : TCF
bits : 8 - 8 (1 bit)

TFE : TFE
bits : 9 - 9 (1 bit)

TEFN : TEFN
bits : 10 - 10 (1 bit)

TEFF : TEFF
bits : 11 - 11 (1 bit)

TEFL : TEFL
bits : 12 - 12 (1 bit)

TSW : TSW
bits : 13 - 13 (1 bit)

MRAF : MRAF
bits : 14 - 14 (1 bit)

TOO : TOO
bits : 15 - 15 (1 bit)

ELO : ELO
bits : 16 - 16 (1 bit)

EP : EP
bits : 17 - 17 (1 bit)

EW : EW
bits : 18 - 18 (1 bit)

BO : BO
bits : 19 - 19 (1 bit)

WDI : WDI
bits : 20 - 20 (1 bit)

PEA : PEA
bits : 21 - 21 (1 bit)

PED : PED
bits : 22 - 22 (1 bit)

ARA : ARA
bits : 23 - 23 (1 bit)


FDCAN_IE

FDCAN Interrupt Enable Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_IE FDCAN_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RF0NE RF0FE RF0LE RF1NE RF1FE RF1LE HPME TCE TCFE TEFE TEFNE TEFFE TEFLE MRAFE TOOE ELOE EPE EWE BOE WDIE PEAE PEDE ARAE

RF0NE : Rx FIFO 0 New Message Enable
bits : 0 - 0 (1 bit)

RF0FE : Rx FIFO 0 Full Enable
bits : 1 - 1 (1 bit)

RF0LE : Rx FIFO 0 Message Lost Enable
bits : 2 - 2 (1 bit)

RF1NE : Rx FIFO 1 New Message Enable
bits : 3 - 3 (1 bit)

RF1FE : Rx FIFO 1 Watermark Reached Enable
bits : 4 - 4 (1 bit)

RF1LE : Rx FIFO 1 Message Lost Enable
bits : 5 - 5 (1 bit)

HPME : High Priority Message Enable
bits : 6 - 6 (1 bit)

TCE : Transmission Completed Enable
bits : 7 - 7 (1 bit)

TCFE : Transmission Cancellation Finished Enable
bits : 8 - 8 (1 bit)

TEFE : Tx FIFO Empty Enable
bits : 9 - 9 (1 bit)

TEFNE : Tx Event FIFO New Entry Enable
bits : 10 - 10 (1 bit)

TEFFE : Tx Event FIFO Full Enable
bits : 11 - 11 (1 bit)

TEFLE : Tx Event FIFO Element Lost Enable
bits : 12 - 12 (1 bit)

MRAFE : Message RAM Access Failure Enable
bits : 13 - 13 (1 bit)

TOOE : Timeout Occurred Enable
bits : 14 - 14 (1 bit)

ELOE : Error Logging Overflow Enable
bits : 15 - 15 (1 bit)

EPE : Error Passive Enable
bits : 16 - 16 (1 bit)

EWE : Warning Status Enable
bits : 17 - 17 (1 bit)

BOE : Bus_Off Status Enable
bits : 18 - 18 (1 bit)

WDIE : Watchdog Interrupt Enable
bits : 19 - 19 (1 bit)

PEAE : Protocol Error in Arbitration Phase Enable
bits : 20 - 20 (1 bit)

PEDE : Protocol Error in Data Phase Enable
bits : 21 - 21 (1 bit)

ARAE : Access to Reserved Address Enable
bits : 22 - 22 (1 bit)


FDCAN_ILS

FDCAN Interrupt Line Select Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ILS FDCAN_ILS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFIFO0 RxFIFO1 SMSG TFERR MISC BERR PERR

RxFIFO0 : RxFIFO0
bits : 0 - 0 (1 bit)

RxFIFO1 : RxFIFO1
bits : 1 - 1 (1 bit)

SMSG : SMSG
bits : 2 - 2 (1 bit)

TFERR : TFERR
bits : 3 - 3 (1 bit)

MISC : MISC
bits : 4 - 4 (1 bit)

BERR : BERR
bits : 5 - 5 (1 bit)

PERR : PERR
bits : 6 - 6 (1 bit)


FDCAN_ILE

FDCAN Interrupt Line Enable Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_ILE FDCAN_ILE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EINT0 EINT1

EINT0 : Enable Interrupt Line 0
bits : 0 - 0 (1 bit)

EINT1 : Enable Interrupt Line 1
bits : 1 - 1 (1 bit)


FDCAN_RXGFC

FDCAN Global Filter Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXGFC FDCAN_RXGFC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RRFE RRFS ANFE ANFS F1OM F0OM LSS LSE

RRFE : Reject Remote Frames Extended
bits : 0 - 0 (1 bit)

RRFS : Reject Remote Frames Standard
bits : 1 - 1 (1 bit)

ANFE : Accept Non-matching Frames Extended
bits : 2 - 3 (2 bit)

ANFS : Accept Non-matching Frames Standard
bits : 4 - 5 (2 bit)

F1OM : F1OM
bits : 8 - 8 (1 bit)

F0OM : F0OM
bits : 9 - 9 (1 bit)

LSS : LSS
bits : 16 - 20 (5 bit)

LSE : LSE
bits : 24 - 27 (4 bit)


FDCAN_XIDAM

FDCAN Extended ID and Mask Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_XIDAM FDCAN_XIDAM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EIDM

EIDM : Extended ID Mask
bits : 0 - 28 (29 bit)


FDCAN_HPMS

FDCAN High Priority Message Status Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_HPMS FDCAN_HPMS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIDX MSI FIDX FLST

BIDX : Buffer Index
bits : 0 - 2 (3 bit)

MSI : Message Storage Indicator
bits : 6 - 7 (2 bit)

FIDX : Filter Index
bits : 8 - 12 (5 bit)

FLST : Filter List
bits : 15 - 15 (1 bit)


FDCAN_RXF0S

FDCAN Rx FIFO 0 Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF0S FDCAN_RXF0S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0FL F0GI F0PI F0F RF0L

F0FL : Rx FIFO 0 Fill Level
bits : 0 - 3 (4 bit)

F0GI : Rx FIFO 0 Get Index
bits : 8 - 9 (2 bit)

F0PI : Rx FIFO 0 Put Index
bits : 16 - 17 (2 bit)

F0F : Rx FIFO 0 Full
bits : 24 - 24 (1 bit)

RF0L : Rx FIFO 0 Message Lost
bits : 25 - 25 (1 bit)


FDCAN_RXF0A

CAN Rx FIFO 0 Acknowledge Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF0A FDCAN_RXF0A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0AI

F0AI : Rx FIFO 0 Acknowledge Index
bits : 0 - 2 (3 bit)


FDCAN_RXF1S

FDCAN Rx FIFO 1 Status Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF1S FDCAN_RXF1S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1FL F1GI F1PI F1F RF1L

F1FL : Rx FIFO 1 Fill Level
bits : 0 - 3 (4 bit)
access : read-write

F1GI : Rx FIFO 1 Get Index
bits : 8 - 9 (2 bit)
access : read-only

F1PI : Rx FIFO 1 Put Index
bits : 16 - 17 (2 bit)
access : read-only

F1F : Rx FIFO 1 Full
bits : 24 - 24 (1 bit)
access : read-only

RF1L : Rx FIFO 1 Message Lost
bits : 25 - 25 (1 bit)
access : read-only


FDCAN_RXF1A

FDCAN Rx FIFO 1 Acknowledge Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_RXF1A FDCAN_RXF1A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F1AI

F1AI : Rx FIFO 1 Acknowledge Index
bits : 0 - 2 (3 bit)


FDCAN_DBTP

FDCAN Data Bit Timing and Prescaler Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_DBTP FDCAN_DBTP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSJW DTSEG2 DTSEG1 DBRP TDC

DSJW : Synchronization Jump Width
bits : 0 - 3 (4 bit)

DTSEG2 : Data time segment after sample point
bits : 4 - 7 (4 bit)

DTSEG1 : Data time segment after sample point
bits : 8 - 12 (5 bit)

DBRP : Data BIt Rate Prescaler
bits : 16 - 20 (5 bit)

TDC : Transceiver Delay Compensation
bits : 23 - 23 (1 bit)


FDCAN_TXBC

FDCAN Tx buffer configuration register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBC FDCAN_TXBC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFQM

TFQM : Tx FIFO/Queue Mode
bits : 24 - 24 (1 bit)


FDCAN_TXFQS

FDCAN Tx FIFO/Queue Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXFQS FDCAN_TXFQS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFFL TFGI TFQPI TFQF

TFFL : Tx FIFO Free Level
bits : 0 - 2 (3 bit)

TFGI : TFGI
bits : 8 - 9 (2 bit)

TFQPI : Tx FIFO/Queue Put Index
bits : 16 - 17 (2 bit)

TFQF : Tx FIFO/Queue Full
bits : 21 - 21 (1 bit)


FDCAN_TXBRP

FDCAN Tx Buffer Request Pending Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBRP FDCAN_TXBRP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRP

TRP : Transmission Request Pending
bits : 0 - 2 (3 bit)


FDCAN_TXBAR

FDCAN Tx Buffer Add Request Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBAR FDCAN_TXBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR

AR : Add Request
bits : 0 - 2 (3 bit)


FDCAN_TXBCR

FDCAN Tx Buffer Cancellation Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBCR FDCAN_TXBCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR

CR : Cancellation Request
bits : 0 - 2 (3 bit)


FDCAN_TXBTO

FDCAN Tx Buffer Transmission Occurred Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBTO FDCAN_TXBTO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO

TO : Transmission Occurred.
bits : 0 - 2 (3 bit)


FDCAN_TXBCF

FDCAN Tx Buffer Cancellation Finished Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBCF FDCAN_TXBCF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : Cancellation Finished
bits : 0 - 2 (3 bit)


FDCAN_TXBTIE

FDCAN Tx Buffer Transmission Interrupt Enable Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBTIE FDCAN_TXBTIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIE

TIE : Transmission Interrupt Enable
bits : 0 - 2 (3 bit)


FDCAN_TXBCIE

FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXBCIE FDCAN_TXBCIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF

CF : Cancellation Finished Interrupt Enable
bits : 0 - 2 (3 bit)


FDCAN_TXEFS

FDCAN Tx Event FIFO Status Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXEFS FDCAN_TXEFS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFFL EFGI EFPI EFF TEFL

EFFL : Event FIFO Fill Level
bits : 0 - 2 (3 bit)

EFGI : Event FIFO Get Index.
bits : 8 - 9 (2 bit)

EFPI : Event FIFO Put Index
bits : 16 - 17 (2 bit)

EFF : Event FIFO Full.
bits : 24 - 24 (1 bit)

TEFL : Tx Event FIFO Element Lost.
bits : 25 - 25 (1 bit)


FDCAN_TXEFA

FDCAN Tx Event FIFO Acknowledge Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDCAN_TXEFA FDCAN_TXEFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EFAI

EFAI : Event FIFO Acknowledge Index
bits : 0 - 1 (2 bit)



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