\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Octal-SPI Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENBSPI : QSPI Enable
bits : 0 - 0 (1 bit)
access : read-write
SELCLKPOL : Clock Polarity, CPOL
bits : 1 - 1 (1 bit)
access : read-write
SELCLKPHASE : Clock Phase, CPHA
bits : 2 - 2 (1 bit)
access : read-write
PHYMODEENABLE : PHY Mode Enable
bits : 3 - 3 (1 bit)
access : read-write
ENBDEVHOLD : Enable Device Hold
bits : 4 - 4 (1 bit)
access : read-write
ENBDEVRST : Enable Device Reset
bits : 5 - 5 (1 bit)
access : read-write
DEVRSTCONFIG : Device Reset Configuration
bits : 6 - 6 (1 bit)
access : read-write
ENBDIRACCCTLR : Enable Direct Access Controller
bits : 7 - 7 (1 bit)
access : read-write
ENBLEGACYIPMODE : Legacy IP Mode Enable
bits : 8 - 8 (1 bit)
access : read-write
PERIPHSELDEC : Peripheral Select Decode
bits : 9 - 9 (1 bit)
access : read-write
PERIPHCSLINES : Peripheral Chip Select Lines
bits : 10 - 11 (2 bit)
access : read-write
WRPROTFLASH : Write Protect Flash Pin
bits : 14 - 14 (1 bit)
access : read-write
ENBAHBADDRREMAP : Enable Address Remapping
bits : 16 - 16 (1 bit)
access : read-write
ENTERXIPMODE : Enter XIP Mode on Next READ
bits : 17 - 17 (1 bit)
access : read-write
ENTERXIPMODEIMM : Enter XIP Mode Immediately
bits : 18 - 18 (1 bit)
access : read-write
MSTRBAUDDIV : Master Mode Baud Rate Divisor
bits : 19 - 22 (4 bit)
access : read-write
ENABLEAHBDECODER : Enable Address Decoder
bits : 23 - 23 (1 bit)
access : read-write
ENABLEDTRPROTOCOL : Enable DTR Protocol
bits : 24 - 24 (1 bit)
access : read-write
PIPELINEPHY : Pipeline PHY Mode Enable
bits : 25 - 25 (1 bit)
access : read-write
CRCENABLE : CRC Enable Bit
bits : 29 - 29 (1 bit)
access : read-write
DUALBYTEOPCODEEN : Dual-byte Opcode Mode Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
IDLE : Serial Interface and Low Level SPI Pipeline is IDLE
bits : 31 - 31 (1 bit)
access : read-only
Read Data Capture Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYPASS : Bypass the Adapted Loopback Clock Circuit
bits : 0 - 0 (1 bit)
access : read-write
DELAY : Read Delay
bits : 1 - 4 (4 bit)
access : read-write
DQSENABLE : DQS Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
DDRREADDELAY : DDR Read Delay
bits : 16 - 19 (4 bit)
access : read-write
I/O Routing Pin Enable Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCLKPEN : SCLK Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
CS0PEN : CS0 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
CS1PEN : CS1 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write
DQ0PEN : DQ0 Pin Enable
bits : 5 - 5 (1 bit)
access : read-write
DQ1PEN : DQ1 Pin Enable
bits : 6 - 6 (1 bit)
access : read-write
DQ2PEN : DQ2 Pin Enable
bits : 7 - 7 (1 bit)
access : read-write
DQ3PEN : DQ3 Pin Enable
bits : 8 - 8 (1 bit)
access : read-write
DQ4PEN : DQ4 Pin Enable
bits : 9 - 9 (1 bit)
access : read-write
DQ5PEN : DQ5 Pin Enable
bits : 10 - 10 (1 bit)
access : read-write
DQ6PEN : DQ6 Pin Enable
bits : 11 - 11 (1 bit)
access : read-write
DQ7PEN : DQ7 Pin Enable
bits : 12 - 12 (1 bit)
access : read-write
DQSPEN : DQS Pin Enable
bits : 13 - 13 (1 bit)
access : read-write
SCLKINPEN : SCLKIN Pin Enable
bits : 14 - 14 (1 bit)
access : read-write
RST0PEN : RST0 Pin Enable
bits : 16 - 16 (1 bit)
access : read-write
RST1PEN : RST1 Pin Enable
bits : 17 - 17 (1 bit)
access : read-write
I/O Route Location Register 0
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSPILOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
QSPIRSTLOC : I/O Location
bits : 6 - 11 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
End of enumeration elements list.
Device Size Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMADDRBYTES : Number of Address Bytes
bits : 0 - 3 (4 bit)
access : read-write
BYTESPERDEVICEPAGE : Number of Bytes Per Device Page
bits : 4 - 15 (12 bit)
access : read-write
BYTESPERSUBSECTOR : Number of Bytes Per Block
bits : 16 - 20 (5 bit)
access : read-write
MEMSIZEONCS0 : Size of Flash Device Connected to CS[0] Pin
bits : 21 - 22 (2 bit)
access : read-write
MEMSIZEONCS1 : Size of Flash Device Connected to CS[1] Pin
bits : 23 - 24 (2 bit)
access : read-write
SRAM Partition Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Indirect Read Partition Size
bits : 0 - 7 (8 bit)
access : read-write
Indirect Address Trigger Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Indirect Address Trigger Register
bits : 0 - 31 (32 bit)
access : read-write
Remap Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Remap Address Value
bits : 0 - 31 (32 bit)
access : read-write
Mode Bit Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Mode Bits
bits : 0 - 7 (8 bit)
access : read-write
CHUNKSIZE : Chunk Size
bits : 8 - 10 (3 bit)
access : read-write
CRCOUTENABLE : CRC# Output Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
RXCRCDATAUP : RX CRC Data (upper)
bits : 16 - 23 (8 bit)
access : read-only
RXCRCDATALOW : RX CRC Data (lower)
bits : 24 - 31 (8 bit)
access : read-only
SRAM Fill Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRAMFILLINDACREAD : SRAM Fill Level (Indirect Read Partition)
bits : 0 - 15 (16 bit)
access : read-only
SRAMFILLINDACWRITE : SRAM Fill Level (Indirect Write Partition)
bits : 16 - 31 (16 bit)
access : read-only
TX Threshold Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL : Threshold Level
bits : 0 - 4 (5 bit)
access : read-write
RX Threshold Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL : Threshold Level
bits : 0 - 4 (5 bit)
access : read-write
Write Completion Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPCODE : Opcode
bits : 0 - 7 (8 bit)
access : read-write
POLLINGBITINDEX : Polling Bit Index
bits : 8 - 10 (3 bit)
access : read-write
POLLINGPOLARITY : Polling Polarity
bits : 13 - 13 (1 bit)
access : read-write
DISABLEPOLLING : Disable Polling
bits : 14 - 14 (1 bit)
access : read-write
ENABLEPOLLINGEXP : Enable Polling Expiration
bits : 15 - 15 (1 bit)
access : read-write
POLLCOUNT : Poll Count
bits : 16 - 23 (8 bit)
access : read-write
POLLREPDELAY : Poll Repetition Delay
bits : 24 - 31 (8 bit)
access : read-write
Polling Expiration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOOFPOLLSBEFEXP : Number of Polls Cycles Before Expiration
bits : 0 - 31 (32 bit)
access : read-write
Device Read Instruction Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDOPCODENONXIP : Read Opcode in Non-XIP Mode
bits : 0 - 7 (8 bit)
access : read-write
INSTRTYPE : Instruction Type
bits : 8 - 9 (2 bit)
access : read-write
DDREN : DDR Enable
bits : 10 - 10 (1 bit)
access : read-write
ADDRXFERTYPESTDMODE : Address Transfer Type for Standard SPI Modes
bits : 12 - 13 (2 bit)
access : read-write
DATAXFERTYPEEXTMODE : Data Transfer Type for Standard SPI Modes
bits : 16 - 17 (2 bit)
access : read-write
MODEBITENABLE : Mode Bit Enable
bits : 20 - 20 (1 bit)
access : read-write
DUMMYRDCLKCYCLES : Dummy Read Clock Cycles
bits : 24 - 28 (5 bit)
access : read-write
Interrupt Status Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODEMFAIL : Mode M Failure
bits : 0 - 0 (1 bit)
access : read-write
UNDERFLOWDET : Underflow Detected
bits : 1 - 1 (1 bit)
access : read-write
INDIRECTOPDONE : Indirect Operation Complete
bits : 2 - 2 (1 bit)
access : read-write
INDIRECTREADREJECT : Indirect Operation Was Requested but Could Not Be Accepted
bits : 3 - 3 (1 bit)
access : read-write
PROTWRATTEMPT : Write to Protected Area Was Attempted and Rejected
bits : 4 - 4 (1 bit)
access : read-write
ILLEGALACCESSDET : Illegal Memory Access Has Been Detected
bits : 5 - 5 (1 bit)
access : read-write
INDIRECTXFERLEVELBREACH : Indirect Transfer Watermark Level Breached
bits : 6 - 6 (1 bit)
access : read-write
RECVOVERFLOW : Receive Overflow
bits : 7 - 7 (1 bit)
access : read-write
TXFIFONOTFULL : Small TX FIFO Not Full
bits : 8 - 8 (1 bit)
access : read-write
TXFIFOFULL : Small TX FIFO Full
bits : 9 - 9 (1 bit)
access : read-write
RXFIFONOTEMPTY : Small RX FIFO Not Empty
bits : 10 - 10 (1 bit)
access : read-write
RXFIFOFULL : Small RX FIFO Full
bits : 11 - 11 (1 bit)
access : read-write
INDRDSRAMFULL : Indirect Read Partition Overflow
bits : 12 - 12 (1 bit)
access : read-write
POLLEXPINT : The Maximum Number of Programmed Polls Cycles is Expired
bits : 13 - 13 (1 bit)
access : read-write
STIGREQINT : The Controller is Ready for Getting Another STIG Request
bits : 14 - 14 (1 bit)
access : read-write
RXCRCDATAERR : RX CRC Data Error
bits : 16 - 16 (1 bit)
access : read-write
RXCRCDATAVAL : RX CRC Data Valid
bits : 17 - 17 (1 bit)
access : read-write
TXCRCCHUNKBRK : TX CRC Chunk Was Broken
bits : 18 - 18 (1 bit)
access : read-write
Interrupt Mask
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODEMFAILMASK : Mode M Failure Mask
bits : 0 - 0 (1 bit)
access : read-write
UNDERFLOWDETMASK : Underflow Detected Mask
bits : 1 - 1 (1 bit)
access : read-write
INDIRECTOPDONEMASK : Indirect Complete Mask
bits : 2 - 2 (1 bit)
access : read-write
INDIRECTREADREJECTMASK : Indirect Read Reject Mask
bits : 3 - 3 (1 bit)
access : read-write
PROTWRATTEMPTMASK : Protected Area Write Attempt Mask
bits : 4 - 4 (1 bit)
access : read-write
ILLEGALACCESSDETMASK : Illegal Access Detected Mask
bits : 5 - 5 (1 bit)
access : read-write
INDIRECTXFERLEVELBREACHMASK : Transfer Watermark Breach Mask
bits : 6 - 6 (1 bit)
access : read-write
RECVOVERFLOWMASK : Receive Overflow Mask
bits : 7 - 7 (1 bit)
access : read-write
TXFIFONOTFULLMASK : Small TX FIFO Not Full Mask
bits : 8 - 8 (1 bit)
access : read-write
TXFIFOFULLMASK : Small TX FIFO Full Mask
bits : 9 - 9 (1 bit)
access : read-write
RXFIFONOTEMPTYMASK : Small RX FIFO Not Empty Mask
bits : 10 - 10 (1 bit)
access : read-write
RXFIFOFULLMASK : Small RX FIFO Full Mask
bits : 11 - 11 (1 bit)
access : read-write
INDRDSRAMFULLMASK : Indirect Read Partition Overflow Mask
bits : 12 - 12 (1 bit)
access : read-write
POLLEXPINTMASK : Polling Expiration Detected Mask
bits : 13 - 13 (1 bit)
access : read-write
STIGREQMASK : STIG Request Completion Mask
bits : 14 - 14 (1 bit)
access : read-write
RXCRCDATAERRMASK : RX CRC Data Error Mask
bits : 16 - 16 (1 bit)
access : read-write
RXCRCDATAVALMASK : RX CRC Data Valid Mask
bits : 17 - 17 (1 bit)
access : read-write
TXCRCCHUNKBRKMASK : TX CRC Chunk Was Broken Mask
bits : 18 - 18 (1 bit)
access : read-write
Lower Write Protection Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBSECTOR : Lower Block Number
bits : 0 - 31 (32 bit)
access : read-write
Upper Write Protection Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBSECTOR : Upper Block Number
bits : 0 - 31 (32 bit)
access : read-write
Write Protection Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INV : Write Protection Inversion Bit
bits : 0 - 0 (1 bit)
access : read-write
ENB : Write Protection Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Indirect Read Transfer Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start Indirect Read
bits : 0 - 0 (1 bit)
access : write-only
CANCEL : Cancel Indirect Read
bits : 1 - 1 (1 bit)
access : write-only
RDSTATUS : Indirect Read Status
bits : 2 - 2 (1 bit)
access : read-only
SRAMFULL : SRAM Full
bits : 3 - 3 (1 bit)
access : read-write
RDQUEUED : Two Indirect Read Operations Have Been Queued
bits : 4 - 4 (1 bit)
access : read-only
INDOPSDONESTATUS : Indirect Completion Status
bits : 5 - 5 (1 bit)
access : read-write
NUMINDOPSDONE : Number Indirect Operations Done
bits : 6 - 7 (2 bit)
access : read-only
Indirect Read Transfer Watermark Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL : Watermark Value
bits : 0 - 31 (32 bit)
access : read-write
Indirect Read Transfer Start Address Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Indirect Read Transfer Start Address
bits : 0 - 31 (32 bit)
access : read-write
Indirect Read Transfer Number Bytes Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Indirect Read Transfer Number Bytes
bits : 0 - 31 (32 bit)
access : read-write
Indirect Write Transfer Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start Indirect Write
bits : 0 - 0 (1 bit)
access : write-only
CANCEL : Cancel Indirect Write
bits : 1 - 1 (1 bit)
access : write-only
WRSTATUS : Indirect Write Status
bits : 2 - 2 (1 bit)
access : read-only
WRQUEUED : Two Indirect Write Operations Have Been Queued
bits : 4 - 4 (1 bit)
access : read-only
INDOPSDONESTATUS : Indirect Completion Status
bits : 5 - 5 (1 bit)
access : read-write
NUMINDOPSDONE : Indirect Operations Done
bits : 6 - 7 (2 bit)
access : read-only
Indirect Write Transfer Watermark Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL : Watermark Value
bits : 0 - 31 (32 bit)
access : read-write
Indirect Write Transfer Start Address Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Start of Indirect Access
bits : 0 - 31 (32 bit)
access : read-write
Indirect Write Transfer Number Bytes Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Indirect Number of Bytes
bits : 0 - 31 (32 bit)
access : read-write
Device Write Instruction Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WROPCODE : Write Opcode
bits : 0 - 7 (8 bit)
access : read-write
WELDIS : WEL Disable
bits : 8 - 8 (1 bit)
access : read-write
ADDRXFERTYPESTDMODE : Address Transfer Type for Standard SPI Modes
bits : 12 - 13 (2 bit)
access : read-write
DATAXFERTYPEEXTMODE : Data Transfer Type for Standard SPI Modes
bits : 16 - 17 (2 bit)
access : read-write
DUMMYWRCLKCYCLES : Dummy Write Clock Cycles
bits : 24 - 28 (5 bit)
access : read-write
Indirect Trigger Address Range Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INDRANGEWIDTH : Indirect Trigger Address Width
bits : 0 - 3 (4 bit)
access : read-write
Flash Command Control Memory Register (STIG)
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGGERMEMBANKREQ : Trigger the Memory Bank Data Request
bits : 0 - 0 (1 bit)
access : write-only
MEMBANKREQINPROGRESS : Memory Bank Data Request in Progress
bits : 1 - 1 (1 bit)
access : read-only
MEMBANKREADDATA : Last Requested Data From the STIG Memory Bank
bits : 8 - 15 (8 bit)
access : read-only
NBOFSTIGREADBYTES : Number of Read Bytes for the Extended STIG
bits : 16 - 18 (3 bit)
access : read-write
MEMBANKADDR : Memory Bank Address
bits : 20 - 28 (9 bit)
access : read-write
Flash Command Control Register (STIG)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMDEXEC : Execute the Command
bits : 0 - 0 (1 bit)
access : write-only
CMDEXECSTATUS : Command Execution in Progress
bits : 1 - 1 (1 bit)
access : read-only
STIGMEMBANKEN : STIG Memory Bank Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
NUMDUMMYCYCLES : Number of Dummy Cycles
bits : 7 - 11 (5 bit)
access : read-write
NUMWRDATABYTES : Number of Write Data Bytes
bits : 12 - 14 (3 bit)
access : read-write
ENBWRITEDATA : Write Data Enable
bits : 15 - 15 (1 bit)
access : read-write
NUMADDRBYTES : Number of Address Bytes
bits : 16 - 17 (2 bit)
access : read-write
ENBMODEBIT : Mode Bit Enable
bits : 18 - 18 (1 bit)
access : read-write
ENBCOMDADDR : Command Address Enable
bits : 19 - 19 (1 bit)
access : read-write
NUMRDDATABYTES : Number of Read Data Bytes
bits : 20 - 22 (3 bit)
access : read-write
ENBREADDATA : Read Data Enable
bits : 23 - 23 (1 bit)
access : read-write
CMDOPCODE : Command Opcode
bits : 24 - 31 (8 bit)
access : read-write
Flash Command Address Register (STIG)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Command Address
bits : 0 - 31 (32 bit)
access : read-write
Flash Command Read Data Register (Lower) (STIG)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Read Data Lower
bits : 0 - 31 (32 bit)
access : read-only
Flash Command Read Data Register (Upper) (STIG)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Read Data Upper
bits : 0 - 31 (32 bit)
access : read-only
Flash Command Write Data Register (Lower) (STIG)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Command Write Data Lower Byte
bits : 0 - 31 (32 bit)
access : read-write
Flash Command Write Data Register (Upper) (STIG)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Command Write Data Upper Byte
bits : 0 - 31 (32 bit)
access : read-write
Polling Flash Status Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVICESTATUS : Device Status
bits : 0 - 7 (8 bit)
access : read-only
DEVICESTATUSVALID : Device Status Valid
bits : 8 - 8 (1 bit)
access : read-only
DEVICESTATUSNBDUMMY : Auto-polling Dummy Cycles
bits : 16 - 19 (4 bit)
access : read-write
PHY Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYCONFIGRXDLLDELAY : RX DLL Delay
bits : 0 - 6 (7 bit)
access : read-write
PHYCONFIGTXDLLDELAY : TX DLL Delay
bits : 16 - 22 (7 bit)
access : read-write
PHYCONFIGRESYNC : PHY Config Resync
bits : 31 - 31 (1 bit)
access : write-only
Device Delay Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DINIT : Clock Delay for CS
bits : 0 - 7 (8 bit)
access : read-write
DAFTER : Clock Delay for Last Transaction Bit
bits : 8 - 15 (8 bit)
access : read-write
DBTWN : Clock Delay Between Two Chip Selects
bits : 16 - 23 (8 bit)
access : read-write
DNSS : Clock Delay for Chip Select Deassert
bits : 24 - 31 (8 bit)
access : read-write
Opcode Extension Register (Lower)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTSTIGOPCODE : STIG Opcode Extension
bits : 0 - 7 (8 bit)
access : read-write
EXTPOLLOPCODE : Polling Opcode Extension
bits : 8 - 15 (8 bit)
access : read-write
EXTWRITEOPCODE : Write Opcode Extension
bits : 16 - 23 (8 bit)
access : read-write
EXTREADOPCODE : Read Opcode Extension
bits : 24 - 31 (8 bit)
access : read-write
Opcode Extension Register (Upper)
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTWELOPCODE : WEL Opcode Extension
bits : 16 - 23 (8 bit)
access : read-write
WELOPCODE : WEL Opcode
bits : 24 - 31 (8 bit)
access : read-write
Module ID Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CONF : Configuration ID Number
bits : 0 - 1 (2 bit)
access : read-only
MODULEID : Module/Revision ID Number
bits : 8 - 23 (16 bit)
access : read-only
FIXPATCH : Fix/patch Number
bits : 24 - 31 (8 bit)
access : read-only
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