\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
ADC Common status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRDY_MST : ADDRDY_MST
bits : 0 - 0 (1 bit)
EOSMP_MST : EOSMP_MST
bits : 1 - 1 (1 bit)
EOC_MST : EOC_MST
bits : 2 - 2 (1 bit)
EOS_MST : EOS_MST
bits : 3 - 3 (1 bit)
OVR_MST : OVR_MST
bits : 4 - 4 (1 bit)
JEOC_MST : JEOC_MST
bits : 5 - 5 (1 bit)
JEOS_MST : JEOS_MST
bits : 6 - 6 (1 bit)
AWD1_MST : AWD1_MST
bits : 7 - 7 (1 bit)
AWD2_MST : AWD2_MST
bits : 8 - 8 (1 bit)
AWD3_MST : AWD3_MST
bits : 9 - 9 (1 bit)
JQOVF_MST : JQOVF_MST
bits : 10 - 10 (1 bit)
ADRDY_SLV : ADRDY_SLV
bits : 16 - 16 (1 bit)
EOSMP_SLV : EOSMP_SLV
bits : 17 - 17 (1 bit)
EOC_SLV : EOC_SLV
bits : 18 - 18 (1 bit)
EOS_SLV : EOS_SLV
bits : 19 - 19 (1 bit)
OVR_SLV : OVR_SLV
bits : 20 - 20 (1 bit)
JEOC_SLV : JEOC_SLV
bits : 21 - 21 (1 bit)
JEOS_SLV : JEOS_SLV
bits : 22 - 22 (1 bit)
AWD1_SLV : AWD1_SLV
bits : 23 - 23 (1 bit)
AWD2_SLV : AWD2_SLV
bits : 24 - 24 (1 bit)
AWD3_SLV : AWD3_SLV
bits : 25 - 25 (1 bit)
JQOVF_SLV : JQOVF_SLV
bits : 26 - 26 (1 bit)
ADC common control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUAL : DUAL
bits : 0 - 4 (5 bit)
DELAY : DELAY
bits : 8 - 10 (3 bit)
DMACFG : DMACFG
bits : 13 - 13 (1 bit)
MDMA : MDMA
bits : 14 - 15 (2 bit)
CKMODE : ADC clock mode
bits : 16 - 17 (2 bit)
PRESC : ADC prescaler
bits : 18 - 21 (4 bit)
VREFEN : VREFINT enable
bits : 22 - 22 (1 bit)
CH17SEL : CH17SEL
bits : 23 - 23 (1 bit)
CH18SEL : CH18SEL
bits : 24 - 24 (1 bit)
Common regular data register for dual mode
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RDATA_MST : RDATA_MST
bits : 0 - 15 (16 bit)
RDATA_SLV : RDATA_SLV
bits : 16 - 31 (16 bit)
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