\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
endpoint 0 register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
endpoint 4 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
endpoint 5 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
endpoint 6 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
endpoint 7 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
endpoint 1 register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRES : Force USB Reset
bits : 0 - 0 (1 bit)
PDWN : Power down
bits : 1 - 1 (1 bit)
LPMODE : Low-power mode
bits : 2 - 2 (1 bit)
FSUSP : Force suspend
bits : 3 - 3 (1 bit)
RESUME : Resume request
bits : 4 - 4 (1 bit)
ESOFM : Expected start of frame interrupt mask
bits : 8 - 8 (1 bit)
SOFM : Start of frame interrupt mask
bits : 9 - 9 (1 bit)
RESETM : USB reset interrupt mask
bits : 10 - 10 (1 bit)
SUSPM : Suspend mode interrupt mask
bits : 11 - 11 (1 bit)
WKUPM : Wakeup interrupt mask
bits : 12 - 12 (1 bit)
ERRM : Error interrupt mask
bits : 13 - 13 (1 bit)
PMAOVRM : Packet memory area over / underrun interrupt mask
bits : 14 - 14 (1 bit)
CTRM : Correct transfer interrupt mask
bits : 15 - 15 (1 bit)
interrupt status register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_ID : Endpoint Identifier
bits : 0 - 3 (4 bit)
access : read-only
DIR : Direction of transaction
bits : 4 - 4 (1 bit)
access : read-only
ESOF : Expected start frame
bits : 8 - 8 (1 bit)
access : read-write
SOF : start of frame
bits : 9 - 9 (1 bit)
access : read-write
RESET : reset request
bits : 10 - 10 (1 bit)
access : read-write
SUSP : Suspend mode request
bits : 11 - 11 (1 bit)
access : read-write
WKUP : Wakeup
bits : 12 - 12 (1 bit)
access : read-write
ERR : Error
bits : 13 - 13 (1 bit)
access : read-write
PMAOVR : Packet memory area over / underrun
bits : 14 - 14 (1 bit)
access : read-write
CTR : Correct transfer
bits : 15 - 15 (1 bit)
access : read-only
frame number register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FN : Frame number
bits : 0 - 10 (11 bit)
LSOF : Lost SOF
bits : 11 - 12 (2 bit)
LCK : Locked
bits : 13 - 13 (1 bit)
RXDM : Receive data - line status
bits : 14 - 14 (1 bit)
RXDP : Receive data + line status
bits : 15 - 15 (1 bit)
device address
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADD : Device address
bits : 0 - 0 (1 bit)
ADD1 : Device address
bits : 1 - 1 (1 bit)
ADD2 : Device address
bits : 2 - 2 (1 bit)
ADD3 : Device address
bits : 3 - 3 (1 bit)
ADD4 : Device address
bits : 4 - 4 (1 bit)
ADD5 : Device address
bits : 5 - 5 (1 bit)
ADD6 : Device address
bits : 6 - 6 (1 bit)
EF : Enable function
bits : 7 - 7 (1 bit)
Buffer table address
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BTABLE : Buffer table
bits : 3 - 15 (13 bit)
endpoint 2 register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
endpoint 3 register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Endpoint address
bits : 0 - 3 (4 bit)
access : read-write
STAT_TX : Status bits, for transmission transfers
bits : 4 - 5 (2 bit)
access : read-write
DTOG_TX : Data Toggle, for transmission transfers
bits : 6 - 6 (1 bit)
access : read-write
CTR_TX : Correct Transfer for transmission
bits : 7 - 7 (1 bit)
access : read-write
EP_KIND : Endpoint kind
bits : 8 - 8 (1 bit)
access : read-write
EP_TYPE : Endpoint type
bits : 9 - 10 (2 bit)
access : read-write
SETUP : Setup transaction completed
bits : 11 - 11 (1 bit)
access : read-only
STAT_RX : Status bits, for reception transfers
bits : 12 - 13 (2 bit)
access : read-write
DTOG_RX : Data Toggle, for reception transfers
bits : 14 - 14 (1 bit)
access : read-write
CTR_RX : Correct transfer for reception
bits : 15 - 15 (1 bit)
access : read-write
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