\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
CMU Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUTSEL0 : Clock Output Select 0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
Disabled
0x00000001 : ULFRCO
ULFRCO (directly from oscillator)
0x00000002 : LFRCO
LFRCO (directly from oscillator)
0x00000003 : LFXO
LFXO (directly from oscillator)
0x00000006 : HFXO
HFXO (directly from oscillator)
0x00000007 : HFEXPCLK
HFEXPCLK
0x00000009 : ULFRCOQ
ULFRCO (qualified)
0x0000000A : LFRCOQ
LFRCO (qualified)
0x0000000B : LFXOQ
LFXO (qualified)
0x0000000C : HFRCOQ
HFRCO (qualified)
0x0000000D : AUXHFRCOQ
AUXHFRCO (qualified)
0x0000000E : HFXOQ
HFXO (qualified)
0x0000000F : HFSRCCLK
HFSRCCLK
End of enumeration elements list.
CLKOUTSEL1 : Clock Output Select 1
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
Disabled
0x00000001 : ULFRCO
ULFRCO (directly from oscillator)
0x00000002 : LFRCO
LFRCO (directly from oscillator)
0x00000003 : LFXO
LFXO (directly from oscillator)
0x00000006 : HFXO
HFXO (directly from oscillator)
0x00000007 : HFEXPCLK
HFEXPCLK
0x00000009 : ULFRCOQ
ULFRCO (qualified)
0x0000000A : LFRCOQ
LFRCO (qualified)
0x0000000B : LFXOQ
LFXO (qualified)
0x0000000C : HFRCOQ
HFRCO (qualified)
0x0000000D : AUXHFRCOQ
AUXHFRCO (qualified)
0x0000000E : HFXOQ
HFXO (qualified)
0x0000000F : HFSRCCLK
HFSRCCLK
End of enumeration elements list.
CLKOUTSEL2 : Clock Output Select 2
bits : 10 - 13 (4 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
Disabled
0x00000001 : ULFRCO
ULFRCO (directly from oscillator)
0x00000002 : LFRCO
LFRCO (directly from oscillator)
0x00000003 : LFXO
LFXO (directly from oscillator)
0x00000005 : HFXODIV2Q
HFXO divided by two (qualified)
0x00000006 : HFXO
HFXO (directly from oscillator)
0x00000007 : HFEXPCLK
HFEXPCLK
0x00000009 : ULFRCOQ
ULFRCO (qualified)
0x0000000A : LFRCOQ
LFRCO (qualified)
0x0000000B : LFXOQ
LFXO (qualified)
0x0000000C : HFRCOQ
HFRCO (qualified)
0x0000000D : AUXHFRCOQ
AUXHFRCO (qualified)
0x0000000E : HFXOQ
HFXO (qualified)
0x0000000F : HFSRCCLK
HFSRCCLK
End of enumeration elements list.
WSHFLE : Wait State for High-Frequency LE Interface
bits : 16 - 16 (1 bit)
access : read-write
HFPERCLKEN : HFPERCLK Enable
bits : 20 - 20 (1 bit)
access : read-write
HFRCO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : HFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
FINETUNING : HFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write
FREQRANGE : HFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write
CMPBIAS : HFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write
LDOHP : HFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write
CLKDIV : Locally Divide HFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
Divide by 1.
0x00000001 : DIV2
Divide by 2.
0x00000002 : DIV4
Divide by 4.
End of enumeration elements list.
FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write
VREFTC : HFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write
High Frequency Clock Prescaler Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFCLK Prescaler
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
HFCLKLEPRESC : HFCLKLE Prescaler
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV2
HFCLKLE is HFBUSCLKLE divided by 2.
0x00000001 : DIV4
HFCLKLE is HFBUSCLKLE divided by 4.
0x00000002 : DIV8
HFCLKLE is HFBUSCLKLE divided by 8.
End of enumeration elements list.
High Frequency Bus Clock Prescaler Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFBUSCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Core Clock Prescaler Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFCORECLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Peripheral Clock Prescaler Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Export Clock Prescaler Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFEXPCLK Prescaler
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Peripheral Clock Prescaler B Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
High Frequency Peripheral Clock Prescaler C Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : HFPERCLK Prescaler
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
Low Frequency a Prescaler Register 0 (Async Reg)
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LESENSE : Low Energy Sensor Interface Prescaler
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFACLKLESENSE = LFACLK
0x00000001 : DIV2
LFACLKLESENSE = LFACLK/2
0x00000002 : DIV4
LFACLKLESENSE = LFACLK/4
0x00000003 : DIV8
LFACLKLESENSE = LFACLK/8
End of enumeration elements list.
LETIMER0 : Low Energy Timer 0 Prescaler
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFACLKLETIMER0 = LFACLK
0x00000001 : DIV2
LFACLKLETIMER0 = LFACLK/2
0x00000002 : DIV4
LFACLKLETIMER0 = LFACLK/4
0x00000003 : DIV8
LFACLKLETIMER0 = LFACLK/8
0x00000004 : DIV16
LFACLKLETIMER0 = LFACLK/16
0x00000005 : DIV32
LFACLKLETIMER0 = LFACLK/32
0x00000006 : DIV64
LFACLKLETIMER0 = LFACLK/64
0x00000007 : DIV128
LFACLKLETIMER0 = LFACLK/128
0x00000008 : DIV256
LFACLKLETIMER0 = LFACLK/256
0x00000009 : DIV512
LFACLKLETIMER0 = LFACLK/512
0x0000000A : DIV1024
LFACLKLETIMER0 = LFACLK/1024
0x0000000B : DIV2048
LFACLKLETIMER0 = LFACLK/2048
0x0000000C : DIV4096
LFACLKLETIMER0 = LFACLK/4096
0x0000000D : DIV8192
LFACLKLETIMER0 = LFACLK/8192
0x0000000E : DIV16384
LFACLKLETIMER0 = LFACLK/16384
0x0000000F : DIV32768
LFACLKLETIMER0 = LFACLK/32768
End of enumeration elements list.
Low Frequency B Prescaler Register 0 (Async Reg)
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTICK : Prescaler
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0x00000000 : DIV1
LFBCLKSYSTICK = LFBCLK
End of enumeration elements list.
LEUART0 : Low Energy UART 0 Prescaler
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFBCLKLEUART0 = LFBCLK
0x00000001 : DIV2
LFBCLKLEUART0 = LFBCLK/2
0x00000002 : DIV4
LFBCLKLEUART0 = LFBCLK/4
0x00000003 : DIV8
LFBCLKLEUART0 = LFBCLK/8
End of enumeration elements list.
CSEN : Capacitive touch sense module Prescaler
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV16
LFBCLKCSEN = LFBCLK/16
0x00000001 : DIV32
LFBCLKCSEN = LFBCLK/32
0x00000002 : DIV64
LFBCLKCSEN = LFBCLK/64
0x00000003 : DIV128
LFBCLKCSEN = LFBCLK/128
End of enumeration elements list.
Low Frequency E Prescaler Register 0 (Async Reg)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCC : Real-Time Counter and Calendar Prescaler
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
LFECLKRTCC = LFECLK
0x00000001 : DIV2
LFECLKRTCC = LFECLK/2
0x00000002 : DIV4
LFECLKRTCC = LFECLK/4
End of enumeration elements list.
Synchronization Busy Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LFACLKEN0 : Low Frequency a Clock Enable 0 Busy
bits : 0 - 0 (1 bit)
access : read-only
LFAPRESC0 : Low Frequency a Prescaler 0 Busy
bits : 2 - 2 (1 bit)
access : read-only
LFBCLKEN0 : Low Frequency B Clock Enable 0 Busy
bits : 4 - 4 (1 bit)
access : read-only
LFBPRESC0 : Low Frequency B Prescaler 0 Busy
bits : 6 - 6 (1 bit)
access : read-only
LFECLKEN0 : Low Frequency E Clock Enable 0 Busy
bits : 16 - 16 (1 bit)
access : read-only
LFEPRESC0 : Low Frequency E Prescaler 0 Busy
bits : 18 - 18 (1 bit)
access : read-only
HFRCOBSY : HFRCO Busy
bits : 24 - 24 (1 bit)
access : read-only
AUXHFRCOBSY : AUXHFRCO Busy
bits : 25 - 25 (1 bit)
access : read-only
LFRCOBSY : LFRCO Busy
bits : 26 - 26 (1 bit)
access : read-only
LFRCOVREFBSY : LFRCO VREF Busy
bits : 27 - 27 (1 bit)
access : read-only
HFXOBSY : HFXO Busy
bits : 28 - 28 (1 bit)
access : read-only
LFXOBSY : LFXO Busy
bits : 29 - 29 (1 bit)
access : read-only
Freeze Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write
PCNT Control Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCNT0CLKEN : PCNT0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
PCNT0CLKSEL : PCNT0 Clock Select
bits : 1 - 1 (1 bit)
access : read-write
ADC Control Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC0CLKDIV : ADC0 Clock Prescaler
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : NODIVISION
None
End of enumeration elements list.
ADC0CLKSEL : ADC0 Clock Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
ADC0 is not clocked
0x00000001 : AUXHFRCO
AUXHFRCO is clocking ADC0
0x00000002 : HFXO
HFXO is clocking ADC0
0x00000003 : HFSRCCLK
HFSRCCLK is clocking ADC0
End of enumeration elements list.
ADC0CLKINV : Invert Clock Selected By ADC0CLKSEL
bits : 8 - 8 (1 bit)
access : read-write
I/O Routing Pin Enable Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUT0PEN : CLKOUT0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
CLKOUT1PEN : CLKOUT1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
CLKOUT2PEN : CLKOUT2 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write
CLKIN0PEN : CLKIN0 Pin Enable
bits : 28 - 28 (1 bit)
access : read-write
I/O Routing Location Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKOUT0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
CLKOUT1LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
CLKOUT2LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
End of enumeration elements list.
I/O Routing Location Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKIN0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
0x00000003 : LOC3
Location 3
0x00000004 : LOC4
Location 4
0x00000005 : LOC5
Location 5
0x00000006 : LOC6
Location 6
0x00000007 : LOC7
Location 7
End of enumeration elements list.
AUXHFRCO Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : AUXHFRCO Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
FINETUNING : AUXHFRCO Fine Tuning Value
bits : 8 - 13 (6 bit)
access : read-write
FREQRANGE : AUXHFRCO Frequency Range
bits : 16 - 20 (5 bit)
access : read-write
CMPBIAS : AUXHFRCO Comparator Bias Current
bits : 21 - 23 (3 bit)
access : read-write
LDOHP : AUXHFRCO LDO High Power Mode
bits : 24 - 24 (1 bit)
access : read-write
CLKDIV : Locally Divide AUXHFRCO Clock Output
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0x00000000 : DIV1
Divide by 1.
0x00000001 : DIV2
Divide by 2.
0x00000002 : DIV4
Divide by 4.
End of enumeration elements list.
FINETUNINGEN : Enable Reference for Fine Tuning
bits : 27 - 27 (1 bit)
access : read-write
VREFTC : AUXHFRCO Temperature Coefficient Trim on Comparator Reference
bits : 28 - 31 (4 bit)
access : read-write
Configuration Lock Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0x00000000 : UNLOCKED
None
0x00000001 : LOCKED
None
End of enumeration elements list.
HFRCO Spread Spectrum Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSAMP : Spread Spectrum Amplitude
bits : 0 - 2 (3 bit)
access : read-write
SSINV : Spread Spectrum Update Interval
bits : 8 - 12 (5 bit)
access : read-write
LFRCO Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : LFRCO Tuning Value
bits : 0 - 8 (9 bit)
access : read-write
ENVREF : Enable Duty Cycling of Vref
bits : 16 - 16 (1 bit)
access : read-write
ENCHOP : Enable Comparator Chopping
bits : 17 - 17 (1 bit)
access : read-write
ENDEM : Enable Dynamic Element Matching
bits : 18 - 18 (1 bit)
access : read-write
VREFUPDATE : Control Vref Update Rate
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x00000000 : 32CYCLES
32 clocks.
0x00000001 : 64CYCLES
64 clocks.
0x00000002 : 128CYCLES
128 clocks.
0x00000003 : 256CYCLES
256 clocks.
End of enumeration elements list.
TIMEOUT : LFRCO Timeout
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 16CYCLES
Timeout period of 16 cycles
0x00000002 : 32CYCLES
Timeout period of 32 cycles
End of enumeration elements list.
GMCCURTUNE : Tuning of Gmc Current
bits : 28 - 31 (4 bit)
access : read-write
HFXO Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : HFXO Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : XTAL
4 MHz - 48 MHz crystal oscillator
0x00000001 : ACBUFEXTCLK
An AC coupled buffer is coupled in series with HFXTAL_N pin, suitable for external sinus wave.
0x00000002 : DCBUFEXTCLK
A DC coupled buffer is coupled in series with HFXTAL_N pin, suitable for external sinus wave.
0x00000003 : DIGEXTCLK
Digital external clock can be supplied on HFXTAL_N pin.
End of enumeration elements list.
PEAKDETMODE : HFXO Automatic Peak Detection Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x00000000 : ONCECMD
Automatic control of HFXO peak detection sequence. Only performs peak detection on initial HFXO startup. CMU_CMD HFXOPEAKDETSTART allowed to be used after HFXORDY=1.
0x00000001 : AUTOCMD
Automatic control of HFXO peak detection sequence. CMU_CMD HFXOPEAKDETSTART allowed to be used after HFXORDY=1.
0x00000002 : CMD
CMU_CMD HFXOPEAKDETSTART can be used to trigger the peak detection sequence after HFXORDY=1.
0x00000003 : MANUAL
CMU_HFXOSTEADYSTATECTRL IBTRIMXOCORE and PEAKDETEN are under full software control and are allowed to be changed once HFXO is ready.
End of enumeration elements list.
LFTIMEOUT : HFXO Low Frequency Timeout
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x00000000 : 0CYCLES
Timeout period of 0 cycles (disabled)
0x00000001 : 2CYCLES
Timeout period of 2 cycles
0x00000002 : 4CYCLES
Timeout period of 4 cycles
0x00000003 : 16CYCLES
Timeout period of 16 cycles
0x00000004 : 32CYCLES
Timeout period of 32 cycles
0x00000005 : 64CYCLES
Timeout period of 64 cycles
0x00000006 : 1KCYCLES
Timeout period of 1024 cycles
0x00000007 : 4KCYCLES
Timeout period of 4096 cycles
End of enumeration elements list.
AUTOSTARTEM0EM1 : Automatically Start of HFXO Upon EM0/EM1 Entry From EM2/EM3
bits : 28 - 28 (1 bit)
access : read-write
AUTOSTARTSELEM0EM1 : Automatically Start and Select of HFXO Upon EM0/EM1 Entry From EM2/EM3
bits : 29 - 29 (1 bit)
access : read-write
HFXO Control 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEAKDETTHR : Sets the Amplitude Detection Level (mV)
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x00000000 : THR0
50mV amplitude detection level
0x00000001 : THR1
75mV amplitude detection level
0x00000002 : THR2
115mV amplitude detection level
0x00000003 : THR3
160mV amplitude detection level
0x00000004 : THR4
220mV amplitude detection level
0x00000005 : THR5
260mV amplitude detection level
0x00000006 : THR6
320mV amplitude detection level
0x00000007 : THR7
Same as THR6
End of enumeration elements list.
HFXO Startup Control
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBTRIMXOCORE : Sets the Startup Oscillator Core Bias Current
bits : 0 - 10 (11 bit)
access : read-write
CTUNE : Sets Oscillator Tuning Capacitance
bits : 11 - 19 (9 bit)
access : read-write
HFXO Steady State Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IBTRIMXOCORE : Sets the Steady State Oscillator Core Bias Current.
bits : 0 - 10 (11 bit)
access : read-write
CTUNE : Sets Oscillator Tuning Capacitance
bits : 11 - 19 (9 bit)
access : read-write
PEAKDETEN : Enables Oscillator Peak Detectors
bits : 26 - 26 (1 bit)
access : read-write
PEAKMONEN : Automatically Perform Peak Monitoring Algorithm on Every Rising Edge of ULFRCO
bits : 27 - 27 (1 bit)
access : read-write
HFXO Timeout Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTUPTIMEOUT : Wait Duration in HFXO Startup Enable Wait State
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 64CYCLES
Timeout period of 64 cycles
0x00000005 : 128CYCLES
Timeout period of 128 cycles
0x00000006 : 256CYCLES
Timeout period of 256 cycles
0x00000007 : 1KCYCLES
Timeout period of 1024 cycles
0x00000008 : 2KCYCLES
Timeout period of 2048 cycles
0x00000009 : 4KCYCLES
Timeout period of 4096 cycles
0x0000000A : 8KCYCLES
Timeout period of 8192 cycles
0x0000000B : 16KCYCLES
Timeout period of 16384 cycles
0x0000000C : 32KCYCLES
Timeout period of 32768 cycles
0x0000000D : 64KCYCLES
Timeout period of 65536 cycles
0x0000000E : 128KCYCLES
Timeout period of 131072 cycles
End of enumeration elements list.
STEADYTIMEOUT : Wait Duration in HFXO Startup Steady Wait State
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 64CYCLES
Timeout period of 64 cycles
0x00000005 : 128CYCLES
Timeout period of 128 cycles
0x00000006 : 256CYCLES
Timeout period of 256 cycles
0x00000007 : 1KCYCLES
Timeout period of 1024 cycles
0x00000008 : 2KCYCLES
Timeout period of 2048 cycles
0x00000009 : 4KCYCLES
Timeout period of 4096 cycles
0x0000000A : 8KCYCLES
Timeout period of 8192 cycles
0x0000000B : 16KCYCLES
Timeout period of 16384 cycles
0x0000000C : 32KCYCLES
Timeout period of 32768 cycles
0x0000000D : 64KCYCLES
Timeout period of 65536 cycles
0x0000000E : 128KCYCLES
Timeout period of 131072 cycles
End of enumeration elements list.
PEAKDETTIMEOUT : Wait Duration in HFXO Peak Detection Wait State
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 4CYCLES
Timeout period of 4 cycles
0x00000002 : 16CYCLES
Timeout period of 16 cycles
0x00000003 : 32CYCLES
Timeout period of 32 cycles
0x00000004 : 64CYCLES
Timeout period of 64 cycles
0x00000005 : 128CYCLES
Timeout period of 128 cycles
0x00000006 : 256CYCLES
Timeout period of 256 cycles
0x00000007 : 1KCYCLES
Timeout period of 1024 cycles
0x00000008 : 2KCYCLES
Timeout period of 2048 cycles
0x00000009 : 4KCYCLES
Timeout period of 4096 cycles
0x0000000A : 8KCYCLES
Timeout period of 8192 cycles
0x0000000B : 16KCYCLES
Timeout period of 16384 cycles
0x0000000C : 32KCYCLES
Timeout period of 32768 cycles
0x0000000D : 64KCYCLES
Timeout period of 65536 cycles
0x0000000E : 128KCYCLES
Timeout period of 131072 cycles
End of enumeration elements list.
LFXO Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TUNING : LFXO Internal Capacitor Array Tuning Value
bits : 0 - 6 (7 bit)
access : read-write
MODE : LFXO Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x00000000 : XTAL
32768 Hz crystal oscillator
0x00000001 : BUFEXTCLK
An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32768 Hz).
0x00000002 : DIGEXTCLK
Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.
End of enumeration elements list.
GAIN : LFXO Startup Gain
bits : 11 - 12 (2 bit)
access : read-write
HIGHAMPL : LFXO High XTAL Oscillation Amplitude Enable
bits : 14 - 14 (1 bit)
access : read-write
AGC : LFXO AGC Enable
bits : 15 - 15 (1 bit)
access : read-write
CUR : LFXO Current Trim
bits : 16 - 17 (2 bit)
access : read-write
BUFCUR : LFXO Buffer Bias Current
bits : 20 - 20 (1 bit)
access : read-write
TIMEOUT : LFXO Timeout
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x00000000 : 2CYCLES
Timeout period of 2 cycles
0x00000001 : 256CYCLES
Timeout period of 256 cycles
0x00000002 : 1KCYCLES
Timeout period of 1024 cycles
0x00000003 : 2KCYCLES
Timeout period of 2048 cycles
0x00000004 : 4KCYCLES
Timeout period of 4096 cycles
0x00000005 : 8KCYCLES
Timeout period of 8192 cycles
0x00000006 : 16KCYCLES
Timeout period of 16384 cycles
0x00000007 : 32KCYCLES
Timeout period of 32768 cycles
End of enumeration elements list.
DPLL Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Operating Mode Control
bits : 0 - 0 (1 bit)
access : read-write
EDGESEL : Reference Edge Select
bits : 1 - 1 (1 bit)
access : read-write
AUTORECOVER : Automatic Recovery Ctrl
bits : 2 - 2 (1 bit)
access : read-write
REFSEL : Reference Clock Selection Control
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
0x00000000 : HFXO
HFXO selected
0x00000001 : LFXO
LFXO selected
0x00000003 : CLKIN0
CLKIN0 selected
End of enumeration elements list.
DITHEN : Dither Enable Control
bits : 6 - 6 (1 bit)
access : read-write
DPLL Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M : Factor M
bits : 0 - 11 (12 bit)
access : read-write
N : Factor N
bits : 16 - 27 (12 bit)
access : read-write
Calibration Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPSEL : Calibration Up-counter Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFXO
Select HFXO as up-counter
0x00000001 : LFXO
Select LFXO as up-counter
0x00000002 : HFRCO
Select HFRCO as up-counter
0x00000003 : LFRCO
Select LFRCO as up-counter
0x00000004 : AUXHFRCO
Select AUXHFRCO as up-counter
0x00000005 : PRS
Select PRS input selected by PRSUPSEL as up-counter
End of enumeration elements list.
DOWNSEL : Calibration Down-counter Select
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x00000000 : HFCLK
Select HFCLK for down-counter
0x00000001 : HFXO
Select HFXO for down-counter
0x00000002 : LFXO
Select LFXO for down-counter
0x00000003 : HFRCO
Select HFRCO for down-counter
0x00000004 : LFRCO
Select LFRCO for down-counter
0x00000005 : AUXHFRCO
Select AUXHFRCO for down-counter
0x00000006 : PRS
Select PRS input selected by PRSDOWNSEL as down-counter
End of enumeration elements list.
CONT : Continuous Calibration
bits : 8 - 8 (1 bit)
access : read-write
PRSUPSEL : PRS Select for PRS Input When Selected in UPSEL
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected as input
0x00000001 : PRSCH1
PRS Channel 1 selected as input
0x00000002 : PRSCH2
PRS Channel 2 selected as input
0x00000003 : PRSCH3
PRS Channel 3 selected as input
0x00000004 : PRSCH4
PRS Channel 4 selected as input
0x00000005 : PRSCH5
PRS Channel 5 selected as input
0x00000006 : PRSCH6
PRS Channel 6 selected as input
0x00000007 : PRSCH7
PRS Channel 7 selected as input
End of enumeration elements list.
PRSDOWNSEL : PRS Select for PRS Input When Selected in DOWNSEL
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x00000000 : PRSCH0
PRS Channel 0 selected as input
0x00000001 : PRSCH1
PRS Channel 1 selected as input
0x00000002 : PRSCH2
PRS Channel 2 selected as input
0x00000003 : PRSCH3
PRS Channel 3 selected as input
0x00000004 : PRSCH4
PRS Channel 4 selected as input
0x00000005 : PRSCH5
PRS Channel 5 selected as input
0x00000006 : PRSCH6
PRS Channel 6 selected as input
0x00000007 : PRSCH7
PRS Channel 7 selected as input
End of enumeration elements list.
Calibration Counter Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALCNT : Calibration Counter
bits : 0 - 19 (20 bit)
access : read-write
Oscillator Enable/Disable Command Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCOEN : HFRCO Enable
bits : 0 - 0 (1 bit)
access : write-only
HFRCODIS : HFRCO Disable
bits : 1 - 1 (1 bit)
access : write-only
HFXOEN : HFXO Enable
bits : 2 - 2 (1 bit)
access : write-only
HFXODIS : HFXO Disable
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCOEN : AUXHFRCO Enable
bits : 4 - 4 (1 bit)
access : write-only
AUXHFRCODIS : AUXHFRCO Disable
bits : 5 - 5 (1 bit)
access : write-only
LFRCOEN : LFRCO Enable
bits : 6 - 6 (1 bit)
access : write-only
LFRCODIS : LFRCO Disable
bits : 7 - 7 (1 bit)
access : write-only
LFXOEN : LFXO Enable
bits : 8 - 8 (1 bit)
access : write-only
LFXODIS : LFXO Disable
bits : 9 - 9 (1 bit)
access : write-only
DPLLEN : DPLL Enable
bits : 12 - 12 (1 bit)
access : write-only
DPLLDIS : DPLL Disable
bits : 13 - 13 (1 bit)
access : write-only
Command Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CALSTART : Calibration Start
bits : 0 - 0 (1 bit)
access : write-only
CALSTOP : Calibration Stop
bits : 1 - 1 (1 bit)
access : write-only
HFXOPEAKDETSTART : HFXO Peak Detection Start
bits : 4 - 4 (1 bit)
access : write-only
Debug Trace Clock Select
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG : Debug Trace Clock
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : AUXHFRCO
AUXHFRCO is the debug trace clock
0x00000001 : HFCLK
HFCLK is the debug trace clock
0x00000002 : HFRCODIV2
HFRCO divided by 2 is the debug trace clock
End of enumeration elements list.
High Frequency Clock Select Command Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HF : HFCLK Select
bits : 0 - 2 (3 bit)
access : write-only
Enumeration:
0x00000001 : HFRCO
Select HFRCO as HFCLK
0x00000002 : HFXO
Select HFXO as HFCLK
0x00000003 : LFRCO
Select LFRCO as HFCLK
0x00000004 : LFXO
Select LFXO as HFCLK
0x00000005 : HFRCODIV2
Select HFRCO divided by 2 as HFCLK
0x00000007 : CLKIN0
Select CLKIN0 as HFCLK
End of enumeration elements list.
Low Frequency A Clock Select Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFA : Clock Select for LFA
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFACLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFACLK
0x00000002 : LFXO
LFXO selected as LFACLK
0x00000004 : ULFRCO
ULFRCO selected as LFACLK
End of enumeration elements list.
Low Frequency B Clock Select Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFB : Clock Select for LFB
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFBCLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFBCLK
0x00000002 : LFXO
LFXO selected as LFBCLK
0x00000003 : HFCLKLE
HFCLK divided by two/four is selected as LFBCLK
0x00000004 : ULFRCO
ULFRCO selected as LFBCLK
End of enumeration elements list.
Low Frequency E Clock Select Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LFE : Clock Select for LFE
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLED
LFECLK is disabled
0x00000001 : LFRCO
LFRCO selected as LFECLK
0x00000002 : LFXO
LFXO selected as LFECLK
0x00000004 : ULFRCO
ULFRCO selected as LFECLK
End of enumeration elements list.
Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HFRCOENS : HFRCO Enable Status
bits : 0 - 0 (1 bit)
access : read-only
HFRCORDY : HFRCO Ready
bits : 1 - 1 (1 bit)
access : read-only
HFXOENS : HFXO Enable Status
bits : 2 - 2 (1 bit)
access : read-only
HFXORDY : HFXO Ready
bits : 3 - 3 (1 bit)
access : read-only
AUXHFRCOENS : AUXHFRCO Enable Status
bits : 4 - 4 (1 bit)
access : read-only
AUXHFRCORDY : AUXHFRCO Ready
bits : 5 - 5 (1 bit)
access : read-only
LFRCOENS : LFRCO Enable Status
bits : 6 - 6 (1 bit)
access : read-only
LFRCORDY : LFRCO Ready
bits : 7 - 7 (1 bit)
access : read-only
LFXOENS : LFXO Enable Status
bits : 8 - 8 (1 bit)
access : read-only
LFXORDY : LFXO Ready
bits : 9 - 9 (1 bit)
access : read-only
DPLLENS : DPLL Enable Status
bits : 12 - 12 (1 bit)
access : read-only
DPLLRDY : DPLL Ready
bits : 13 - 13 (1 bit)
access : read-only
CALRDY : Calibration Ready
bits : 16 - 16 (1 bit)
access : read-only
HFXOPEAKDETRDY : HFXO Peak Detection Ready
bits : 22 - 22 (1 bit)
access : read-only
HFXOAMPLOW : HFXO Amplitude Tuning Value Too Low
bits : 25 - 25 (1 bit)
access : read-only
LFXOPHASE : LFXO Clock Phase
bits : 27 - 27 (1 bit)
access : read-only
LFRCOPHASE : LFRCO Clock Phase
bits : 28 - 28 (1 bit)
access : read-only
ULFRCOPHASE : ULFRCO Clock Phase
bits : 29 - 29 (1 bit)
access : read-only
HFCLK Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SELECTED : HFCLK Selected
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x00000001 : HFRCO
HFRCO is selected as HFCLK clock source
0x00000002 : HFXO
HFXO is selected as HFCLK clock source
0x00000003 : LFRCO
LFRCO is selected as HFCLK clock source
0x00000004 : LFXO
LFXO is selected as HFCLK clock source
0x00000005 : HFRCODIV2
HFRCO divided by 2 is selected as HFCLK clock source
0x00000007 : CLKIN0
CLKIN0 is selected as HFCLK clock source
End of enumeration elements list.
HFXO Trim Status
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IBTRIMXOCORE : Value of IBTRIMXOCORE Found By Automatic HFXO Peak Detection Algorithm
bits : 0 - 10 (11 bit)
access : read-only
IBTRIMXOCOREMON : Value of IBTRIMXOCORE Found By Automatic HFXO Peak Detection Algorithm or Peak Monitoring Algorithm (completion of Either Algorithm Will Cause an Update of IBTRIMXOCOREMON)
bits : 16 - 26 (11 bit)
access : read-only
VALID : Peak Detection Algorithm Found a Value for IBTRIMXOCORE
bits : 30 - 30 (1 bit)
access : read-only
MONVALID : Peak Detection Algorithm or Peak Monitoring Algorithm Found a Value for IBTRIMXOCOREMON
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Flag Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCO Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
HFXORDY : HFXO Ready Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
LFRCORDY : LFRCO Ready Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
LFXORDY : LFXO Ready Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
CALRDY : Calibration Ready Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
CALOF : Calibration Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only
HFXODISERR : HFXO Disable Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only
HFXOAUTOSW : HFXO Automatic Switch Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only
HFXOPEAKDETRDY : HFXO Automatic Peak Detection Ready Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only
HFRCODIS : HFRCO Disable Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-only
LFTIMEOUTERR : Low Frequency Timeout Error Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-only
DPLLRDY : DPLL Lock Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-only
DPLLLOCKFAILLOW : DPLL Lock Failure Low Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only
DPLLLOCKFAILHIGH : DPLL Lock Failure Low Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-only
LFXOEDGE : LFXO Clock Edge Detected Interrupt Flag
bits : 27 - 27 (1 bit)
access : read-only
LFRCOEDGE : LFRCO Clock Edge Detected Interrupt Flag
bits : 28 - 28 (1 bit)
access : read-only
ULFRCOEDGE : ULFRCO Clock Edge Detected Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-only
CMUERR : CMU Error Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : Set HFRCORDY Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
HFXORDY : Set HFXORDY Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
LFRCORDY : Set LFRCORDY Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
LFXORDY : Set LFXORDY Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCORDY : Set AUXHFRCORDY Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
CALRDY : Set CALRDY Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
CALOF : Set CALOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only
HFXODISERR : Set HFXODISERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only
HFXOAUTOSW : Set HFXOAUTOSW Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only
HFXOPEAKDETRDY : Set HFXOPEAKDETRDY Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only
HFRCODIS : Set HFRCODIS Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only
LFTIMEOUTERR : Set LFTIMEOUTERR Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only
DPLLRDY : Set DPLLRDY Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only
DPLLLOCKFAILLOW : Set DPLLLOCKFAILLOW Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only
DPLLLOCKFAILHIGH : Set DPLLLOCKFAILHIGH Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only
LFXOEDGE : Set LFXOEDGE Interrupt Flag
bits : 27 - 27 (1 bit)
access : write-only
LFRCOEDGE : Set LFRCOEDGE Interrupt Flag
bits : 28 - 28 (1 bit)
access : write-only
ULFRCOEDGE : Set ULFRCOEDGE Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only
CMUERR : Set CMUERR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : Clear HFRCORDY Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
HFXORDY : Clear HFXORDY Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
LFRCORDY : Clear LFRCORDY Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only
LFXORDY : Clear LFXORDY Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only
AUXHFRCORDY : Clear AUXHFRCORDY Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only
CALRDY : Clear CALRDY Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only
CALOF : Clear CALOF Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only
HFXODISERR : Clear HFXODISERR Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only
HFXOAUTOSW : Clear HFXOAUTOSW Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only
HFXOPEAKDETRDY : Clear HFXOPEAKDETRDY Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only
HFRCODIS : Clear HFRCODIS Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only
LFTIMEOUTERR : Clear LFTIMEOUTERR Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only
DPLLRDY : Clear DPLLRDY Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only
DPLLLOCKFAILLOW : Clear DPLLLOCKFAILLOW Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only
DPLLLOCKFAILHIGH : Clear DPLLLOCKFAILHIGH Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only
LFXOEDGE : Clear LFXOEDGE Interrupt Flag
bits : 27 - 27 (1 bit)
access : write-only
LFRCOEDGE : Clear LFRCOEDGE Interrupt Flag
bits : 28 - 28 (1 bit)
access : write-only
ULFRCOEDGE : Clear ULFRCOEDGE Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only
CMUERR : Clear CMUERR Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HFRCORDY : HFRCORDY Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
HFXORDY : HFXORDY Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
LFRCORDY : LFRCORDY Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
LFXORDY : LFXORDY Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
AUXHFRCORDY : AUXHFRCORDY Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
CALRDY : CALRDY Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
CALOF : CALOF Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
HFXODISERR : HFXODISERR Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
HFXOAUTOSW : HFXOAUTOSW Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
HFXOPEAKDETRDY : HFXOPEAKDETRDY Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
HFRCODIS : HFRCODIS Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
LFTIMEOUTERR : LFTIMEOUTERR Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
DPLLRDY : DPLLRDY Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
DPLLLOCKFAILLOW : DPLLLOCKFAILLOW Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
DPLLLOCKFAILHIGH : DPLLLOCKFAILHIGH Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
LFXOEDGE : LFXOEDGE Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
LFRCOEDGE : LFRCOEDGE Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
ULFRCOEDGE : ULFRCOEDGE Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write
CMUERR : CMUERR Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write
High Frequency Bus Clock Enable Register 0
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LE : Low Energy Peripheral Interface Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
CRYPTO0 : Advanced Encryption Standard Accelerator Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
GPIO : General purpose Input/Output Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
PRS : Peripheral Reflex System Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
LDMA : Linked Direct Memory Access Controller Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
GPCRC : General Purpose CRC Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
High Frequency Peripheral Clock Enable Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USART0 : Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
USART1 : Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
USART2 : Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
USART3 : Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
TIMER0 : Timer 0 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
TIMER1 : Timer 1 Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
I2C0 : I2C 0 Clock Enable
bits : 6 - 6 (1 bit)
access : read-write
I2C1 : I2C 1 Clock Enable
bits : 7 - 7 (1 bit)
access : read-write
ACMP0 : Analog Comparator 0 Clock Enable
bits : 8 - 8 (1 bit)
access : read-write
ACMP1 : Analog Comparator 1 Clock Enable
bits : 9 - 9 (1 bit)
access : read-write
CRYOTIMER : CRYOTIMER Clock Enable
bits : 10 - 10 (1 bit)
access : read-write
ADC0 : Analog to Digital Converter 0 Clock Enable
bits : 11 - 11 (1 bit)
access : read-write
TRNG0 : True Random Number Generator 0 Clock Enable
bits : 12 - 12 (1 bit)
access : read-write
High Frequency Peripheral Clock Enable Register 1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART0 : Universal Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
WTIMER0 : Wide Timer 0 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
WTIMER1 : Wide Timer 1 Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
CAN0 : CAN 0 Clock Enable
bits : 3 - 3 (1 bit)
access : read-write
VDAC0 : Digital to Analog Converter 0 Clock Enable
bits : 4 - 4 (1 bit)
access : read-write
CSEN : Capacitive touch sense module Clock Enable
bits : 5 - 5 (1 bit)
access : read-write
Low Frequency a Clock Enable Register 0 (Async Reg)
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LESENSE : Low Energy Sensor Interface Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
LETIMER0 : Low Energy Timer 0 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
Low Frequency B Clock Enable Register 0 (Async Reg)
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTICK : Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
LEUART0 : Low Energy UART 0 Clock Enable
bits : 1 - 1 (1 bit)
access : read-write
CSEN : Capacitive touch sense module Clock Enable
bits : 2 - 2 (1 bit)
access : read-write
Low Frequency E Clock Enable Register 0 (Async Reg)
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCC : Real-Time Counter and Calendar Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.