\n

RMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

LOCK

RSTCAUSE

CMD

RST


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOGRMODE LOCKUPRMODE SYSRMODE PINRMODE RESETSTATE

WDOGRMODE : WDOG Reset Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Reset request is blocked. This disable bit is redundant with enable/disable bit in WDOG

0x00000001 : LIMITED

The CRYOTIMER, DEBUGGER, RTCC, are not reset.

0x00000002 : EXTENDED

The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.

0x00000004 : FULL

The entire device is reset except some EMU and RMU registers.

End of enumeration elements list.

LOCKUPRMODE : Core LOCKUP Reset Mode
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Reset request is blocked.

0x00000001 : LIMITED

The CRYOTIMER, DEBUGGER, RTCC, are not reset.

0x00000002 : EXTENDED

The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.

0x00000004 : FULL

The entire device is reset except some EMU and RMU registers.

End of enumeration elements list.

SYSRMODE : Core Sysreset Reset Mode
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Reset request is blocked.

0x00000001 : LIMITED

The CRYOTIMER, DEBUGGER, RTCC, are not reset.

0x00000002 : EXTENDED

The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.

0x00000004 : FULL

The entire device is reset except some EMU and RMU registers.

End of enumeration elements list.

PINRMODE : PIN Reset Mode
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Reset request is blocked.

0x00000001 : LIMITED

The CRYOTIMER, DEBUGGER, RTCC, are not reset.

0x00000002 : EXTENDED

The CRYOTIMER, DEBUGGER are not reset. RTCC is reset.

0x00000004 : FULL

The entire device is reset except some EMU and RMU registers.

End of enumeration elements list.

RESETSTATE : System Software Reset State
bits : 24 - 25 (2 bit)
access : read-write


LOCK

Configuration Lock Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


RSTCAUSE

Reset Cause Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSTCAUSE RSTCAUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORST AVDDBOD DVDDBOD DECBOD EXTRST LOCKUPRST SYSREQRST WDOGRST BUMODERST EM4RST

PORST : Power on Reset
bits : 0 - 0 (1 bit)
access : read-only

AVDDBOD : Brown Out Detector AVDD Reset
bits : 2 - 2 (1 bit)
access : read-only

DVDDBOD : Brown Out Detector DVDD Reset
bits : 3 - 3 (1 bit)
access : read-only

DECBOD : Brown Out Detector Decouple Domain Reset
bits : 4 - 4 (1 bit)
access : read-only

EXTRST : External Pin Reset
bits : 8 - 8 (1 bit)
access : read-only

LOCKUPRST : LOCKUP Reset
bits : 9 - 9 (1 bit)
access : read-only

SYSREQRST : System Request Reset
bits : 10 - 10 (1 bit)
access : read-only

WDOGRST : Watchdog Reset
bits : 11 - 11 (1 bit)
access : read-only

BUMODERST : Backup Mode Reset
bits : 12 - 12 (1 bit)
access : read-only

EM4RST : EM4 Reset
bits : 16 - 16 (1 bit)
access : read-only


CMD

Command Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCCLR

RCCLR : Reset Cause Clear
bits : 0 - 0 (1 bit)
access : write-only


RST

Reset Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RST RST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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