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CAN0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

INTID

TEST

BRPE

TRANSREQ

MESSAGEDATA

MESSAGESTATE

CONFIG

IF0IF

IF0IFS

IF0IFC

IF0IEN

STATUS

IF1IF

IF1IFS

IF1IFC

IF1IEN

ROUTE

MIR0_CMDMASK

MIR0_MASK

MIR0_ARB

MIR0_CTRL

MIR0_DATAL

MIR0_DATAH

MIR0_CMDREQ

ERRCNT

MIR1_CMDMASK

MIR1_MASK

MIR1_ARB

MIR1_CTRL

MIR1_DATAL

MIR1_DATAH

MIR1_CMDREQ

BITTIMING


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT IE SIE EIE DAR CCE TEST

INIT : Initialize
bits : 0 - 0 (1 bit)
access : read-write

IE : Module Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

SIE : Status Change Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

EIE : Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

DAR : Disable Automatic Retransmission
bits : 5 - 5 (1 bit)
access : read-write

CCE : Configuration Change Enable
bits : 6 - 6 (1 bit)
access : read-write

TEST : Test Mode Enable Write
bits : 7 - 7 (1 bit)
access : read-write


INTID

Interrupt Identification Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTID INTID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID INTSTAT

INTID : Interrupt Identifier
bits : 0 - 5 (6 bit)
access : read-only

INTSTAT : Status Interupt
bits : 15 - 15 (1 bit)
access : read-only


TEST

Test Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASIC SILENT LBACK TX RX

BASIC : Basic Mode
bits : 2 - 2 (1 bit)
access : read-write

SILENT : Silent Mode
bits : 3 - 3 (1 bit)
access : read-write

LBACK : Loopback Mode
bits : 4 - 4 (1 bit)
access : read-write

TX : Control of CAN_TX Pin
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x00000000 : CORE

Reset value, CAN_TX is controlled by the CAN Core.

0x00000001 : SAMPT

Sample Point can be monitored at CAN_TX pin.

0x00000002 : LOW

CAN_TX pin drives a dominant bit (0) value.

0x00000003 : HIGH

CAN_TX pin drives a recessive bit (1) value.

End of enumeration elements list.

RX : Monitors the Actual Value of CAN_RX Pin
bits : 7 - 7 (1 bit)
access : read-only


BRPE

BRP Extension Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRPE BRPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRPE

BRPE : Baud Rate Prescaler Extension
bits : 0 - 3 (4 bit)
access : read-write


TRANSREQ

Transmission Request Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TRANSREQ TRANSREQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRQSTOUT

TXRQSTOUT : Transmission Request Bits (Of All Message Objects)
bits : 0 - 31 (32 bit)
access : read-only

Enumeration:

0x00000000 : FALSE

This Message Object is not waiting for transmission.

0x00000001 : TRUE

The transmission of this Message Object is requested and is not yet done.

End of enumeration elements list.


MESSAGEDATA

New Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MESSAGEDATA MESSAGEDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALID

VALID : DATAVALID Bits (of All Message Objects)
bits : 0 - 31 (32 bit)
access : read-only


MESSAGESTATE

Message Valid Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MESSAGESTATE MESSAGESTATE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALID

VALID : Message Valid Bits (of All Message Objects)
bits : 0 - 31 (32 bit)
access : read-only


CONFIG

Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONFIG CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGHALT

DBGHALT : Debug Halt
bits : 15 - 15 (1 bit)
access : read-write


IF0IF

Message Object Interrupt Flag Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF0IF IF0IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGE

MESSAGE : Message Object Interrupt Flag
bits : 0 - 31 (32 bit)
access : read-only


IF0IFS

Message Object Interrupt Flag Set Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IF0IFS IF0IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGE

MESSAGE : Set MESSAGE Interrupt Flag
bits : 0 - 31 (32 bit)
access : write-only


IF0IFC

Message Object Interrupt Flag Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IF0IFC IF0IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGE

MESSAGE : Clear MESSAGE Interrupt Flag
bits : 0 - 31 (32 bit)
access : write-only


IF0IEN

Message Object Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF0IEN IF0IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MESSAGE

MESSAGE : MESSAGE Interrupt Enable
bits : 0 - 31 (32 bit)
access : read-write


STATUS

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEC TXOK RXOK EPASS EWARN BOFF

LEC : Last Error Code
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No error occurred during last CAN bus event.

0x00000001 : STUFF

More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.

0x00000002 : FORM

A fixed format part of a received frame has the wrong format.

0x00000003 : ACK

The message this CAN Core transmitted was not acknowledged by another node.

0x00000004 : BIT1

During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.

0x00000005 : BIT0

During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored Bus value was recessive. During Bus Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).

0x00000006 : CRC

The CRC check sum was incorrect in the message received the CRC received for an incoming message does not match with the calculated CRC for the received data.

0x00000007 : UNUSED

When the LEC shows the value '7', no CAN bus event was detected since the CPU wrote this value to the LEC.

End of enumeration elements list.

TXOK : Transmitted a Message Successfully
bits : 3 - 3 (1 bit)
access : read-write

RXOK : Received a Message Successfully
bits : 4 - 4 (1 bit)
access : read-write

EPASS : Error Passive
bits : 5 - 5 (1 bit)
access : read-only

EWARN : Warning Status
bits : 6 - 6 (1 bit)
access : read-only

BOFF : Bus Off Status
bits : 7 - 7 (1 bit)
access : read-only


IF1IF

Status Interrupt Flag Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF1IF IF1IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS

STATUS : Status Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only


IF1IFS

Message Object Interrupt Flag Set Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IF1IFS IF1IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS

STATUS : Set STATUS Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only


IF1IFC

Message Object Interrupt Flag Clear Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IF1IFC IF1IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS

STATUS : Clear STATUS Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only


IF1IEN

Status Interrupt Enable Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF1IEN IF1IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS

STATUS : STATUS Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPEN RXLOC TXLOC

TXPEN : TX Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

RXLOC : RX Pin Location
bits : 2 - 7 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

0x00000007 : LOC7

Location 7

End of enumeration elements list.

TXLOC : TX Pin Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

0x00000007 : LOC7

Location 7

End of enumeration elements list.


MIR0_CMDMASK

Interface Command Mask Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_CMDMASK MIR0_CMDMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAB DATAA TXRQSTNEWDAT CLRINTPND CONTROL ARBACC MASKACC WRRD

DATAB : CC Channel Mode
bits : 0 - 0 (1 bit)
access : read-write

DATAA : Access Data Bytes 0-3
bits : 1 - 1 (1 bit)
access : read-write

TXRQSTNEWDAT : Transmission Request Bit/ New Data Bit
bits : 2 - 2 (1 bit)
access : read-write

CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 3 (1 bit)
access : read-write

CONTROL : Access Control Bits
bits : 4 - 4 (1 bit)
access : read-write

ARBACC : Access Arbitration Bits
bits : 5 - 5 (1 bit)
access : read-write

MASKACC : Access Mask Bits
bits : 6 - 6 (1 bit)
access : read-write

WRRD : Write/Read RAM
bits : 7 - 7 (1 bit)
access : read-write


MIR0_MASK

Interface Mask Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_MASK MIR0_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK MDIR MXTD

MASK : Identifier Mask
bits : 0 - 28 (29 bit)
access : read-write

MDIR : Mask Message Direction
bits : 30 - 30 (1 bit)
access : read-write

MXTD : Mask Extended Identifier
bits : 31 - 31 (1 bit)
access : read-write


MIR0_ARB

Interface Arbitration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_ARB MIR0_ARB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID DIR XTD MSGVAL

ID : Message Identifier
bits : 0 - 28 (29 bit)
access : read-write

DIR : Message Direction
bits : 29 - 29 (1 bit)
access : read-write

XTD : Extended Identifier
bits : 30 - 30 (1 bit)
access : read-write

MSGVAL : Message Valid
bits : 31 - 31 (1 bit)
access : read-write


MIR0_CTRL

Interface Message Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_CTRL MIR0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MESSAGEOF DATAVALID

DLC : Data Length Code
bits : 0 - 3 (4 bit)
access : read-write

EOB : End of Buffer
bits : 7 - 7 (1 bit)
access : read-write

TXRQST : Transmit Request
bits : 8 - 8 (1 bit)
access : read-write

RMTEN : Remote Enable
bits : 9 - 9 (1 bit)
access : read-write

RXIE : Receive Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

TXIE : Transmit Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

UMASK : Use Acceptance Mask
bits : 12 - 12 (1 bit)
access : read-write

INTPND : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-write

MESSAGEOF : Message Lost (only Valid for Message Objects With Direction = Receive)
bits : 14 - 14 (1 bit)
access : read-write

DATAVALID : New Data
bits : 15 - 15 (1 bit)
access : read-write


MIR0_DATAL

Interface Data a Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_DATAL MIR0_DATAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : First Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write

DATA1 : Second Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write

DATA2 : Third Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write

DATA3 : Fourth Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write


MIR0_DATAH

Interface Data B Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_DATAH MIR0_DATAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : Fifth Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write

DATA5 : Sixth Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write

DATA6 : Seventh Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write

DATA7 : Eight Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write


MIR0_CMDREQ

Interface Command Request Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR0_CMDREQ MIR0_CMDREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSGNUM BUSY

MSGNUM : Message Number
bits : 0 - 5 (6 bit)
access : read-write

BUSY : Busy Flag
bits : 15 - 15 (1 bit)
access : read-only


ERRCNT

Error Count Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ERRCNT ERRCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEC REC RECERRP

TEC : Transmit Error Counter
bits : 0 - 7 (8 bit)
access : read-only

REC : Receive Error Counter
bits : 8 - 14 (7 bit)
access : read-only

RECERRP : Receive Error Passive
bits : 15 - 15 (1 bit)
access : read-only


MIR1_CMDMASK

Interface Command Mask Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_CMDMASK MIR1_CMDMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAB DATAA TXRQSTNEWDAT CLRINTPND CONTROL ARBACC MASKACC WRRD

DATAB : CC Channel Mode
bits : 0 - 0 (1 bit)
access : read-write

DATAA : Access Data Bytes 0-3
bits : 1 - 1 (1 bit)
access : read-write

TXRQSTNEWDAT : Transmission Request Bit/ New Data Bit
bits : 2 - 2 (1 bit)
access : read-write

CLRINTPND : Clear Interrupt Pending Bit
bits : 3 - 3 (1 bit)
access : read-write

CONTROL : Access Control Bits
bits : 4 - 4 (1 bit)
access : read-write

ARBACC : Access Arbitration Bits
bits : 5 - 5 (1 bit)
access : read-write

MASKACC : Access Mask Bits
bits : 6 - 6 (1 bit)
access : read-write

WRRD : Write/Read RAM
bits : 7 - 7 (1 bit)
access : read-write


MIR1_MASK

Interface Mask Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_MASK MIR1_MASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK MDIR MXTD

MASK : Identifier Mask
bits : 0 - 28 (29 bit)
access : read-write

MDIR : Mask Message Direction
bits : 30 - 30 (1 bit)
access : read-write

MXTD : Mask Extended Identifier
bits : 31 - 31 (1 bit)
access : read-write


MIR1_ARB

Interface Arbitration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_ARB MIR1_ARB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID DIR XTD MSGVAL

ID : Message Identifier
bits : 0 - 28 (29 bit)
access : read-write

DIR : Message Direction
bits : 29 - 29 (1 bit)
access : read-write

XTD : Extended Identifier
bits : 30 - 30 (1 bit)
access : read-write

MSGVAL : Message Valid
bits : 31 - 31 (1 bit)
access : read-write


MIR1_CTRL

Interface Message Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_CTRL MIR1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLC EOB TXRQST RMTEN RXIE TXIE UMASK INTPND MESSAGEOF DATAVALID

DLC : Data Length Code
bits : 0 - 3 (4 bit)
access : read-write

EOB : End of Buffer
bits : 7 - 7 (1 bit)
access : read-write

TXRQST : Transmit Request
bits : 8 - 8 (1 bit)
access : read-write

RMTEN : Remote Enable
bits : 9 - 9 (1 bit)
access : read-write

RXIE : Receive Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

TXIE : Transmit Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

UMASK : Use Acceptance Mask
bits : 12 - 12 (1 bit)
access : read-write

INTPND : Interrupt Pending
bits : 13 - 13 (1 bit)
access : read-write

MESSAGEOF : Message Lost (only Valid for Message Objects With Direction = Receive)
bits : 14 - 14 (1 bit)
access : read-write

DATAVALID : New Data
bits : 15 - 15 (1 bit)
access : read-write


MIR1_DATAL

Interface Data a Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_DATAL MIR1_DATAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0 DATA1 DATA2 DATA3

DATA0 : First Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write

DATA1 : Second Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write

DATA2 : Third Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write

DATA3 : Fourth Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write


MIR1_DATAH

Interface Data B Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_DATAH MIR1_DATAH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4 DATA5 DATA6 DATA7

DATA4 : Fifth Byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write

DATA5 : Sixth Byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write

DATA6 : Seventh Byte of CAN Data Frame
bits : 16 - 23 (8 bit)
access : read-write

DATA7 : Eight Byte of CAN Data Frame
bits : 24 - 31 (8 bit)
access : read-write


MIR1_CMDREQ

Interface Command Request Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIR1_CMDREQ MIR1_CMDREQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSGNUM BUSY

MSGNUM : Message Number
bits : 0 - 5 (6 bit)
access : read-write

BUSY : Busy Flag
bits : 15 - 15 (1 bit)
access : read-only


BITTIMING

Bit Timing Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BITTIMING BITTIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRP SJW TSEG1 TSEG2

BRP : Baud Rate Prescaler
bits : 0 - 5 (6 bit)
access : read-write

SJW : Synchronization Jump Width
bits : 6 - 7 (2 bit)
access : read-write

TSEG1 : Time Segment Before the Sample Point
bits : 8 - 11 (4 bit)
access : read-write

TSEG2 : Time Segment After the Sample Point
bits : 12 - 14 (3 bit)
access : read-write



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