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PRS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SWPULSE

ROUTELOC0

TRACECTRL

ROUTELOC1

CTRL

DMAREQ0

DMAREQ1

SWLEVEL

PEEK

CH0_CTRL

CH1_CTRL

CH2_CTRL

CH3_CTRL

CH4_CTRL

CH5_CTRL

CH6_CTRL

CH7_CTRL

ROUTEPEN


SWPULSE

Software Pulse Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPULSE SWPULSE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PULSE CH1PULSE CH2PULSE CH3PULSE CH4PULSE CH5PULSE CH6PULSE CH7PULSE

CH0PULSE : Channel 0 Pulse Generation
bits : 0 - 0 (1 bit)
access : write-only

CH1PULSE : Channel 1 Pulse Generation
bits : 1 - 1 (1 bit)
access : write-only

CH2PULSE : Channel 2 Pulse Generation
bits : 2 - 2 (1 bit)
access : write-only

CH3PULSE : Channel 3 Pulse Generation
bits : 3 - 3 (1 bit)
access : write-only

CH4PULSE : Channel 4 Pulse Generation
bits : 4 - 4 (1 bit)
access : write-only

CH5PULSE : Channel 5 Pulse Generation
bits : 5 - 5 (1 bit)
access : write-only

CH6PULSE : Channel 6 Pulse Generation
bits : 6 - 6 (1 bit)
access : write-only

CH7PULSE : Channel 7 Pulse Generation
bits : 7 - 7 (1 bit)
access : write-only


ROUTELOC0

I/O Routing Location Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC0 ROUTELOC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0LOC CH1LOC CH2LOC CH3LOC

CH0LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.

CH1LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.

CH2LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.

CH3LOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.


TRACECTRL

MTB Trace Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRACECTRL TRACECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSTARTEN TSTART TSTOPEN TSTOP

TSTARTEN : PRS TSTART Enable
bits : 0 - 0 (1 bit)
access : read-write

TSTART : MTB TSTART PRS Select
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 is controlling TSTART.

0x00000001 : PRSCH1

PRS ch 1 is controlling TSTART.

0x00000002 : PRSCH2

PRS ch 2 is controlling TSTART.

0x00000003 : PRSCH3

PRS ch 3 is controlling TSTART.

0x00000004 : PRSCH4

PRS ch 4 is controlling TSTART.

0x00000005 : PRSCH5

PRS ch 5 is controlling TSTART.

0x00000006 : PRSCH6

PRS ch 6 is controlling TSTART.

0x00000007 : PRSCH7

PRS ch 7 is controlling TSTART.

End of enumeration elements list.

TSTOPEN : PRS TSTOP Enable
bits : 8 - 8 (1 bit)
access : read-write

TSTOP : MTB TSTOP PRS Select
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 is controlling TSTOP.

0x00000001 : PRSCH1

PRS ch 1 is controlling TSTOP.

0x00000002 : PRSCH2

PRS ch 2 is controlling TSTOP.

0x00000003 : PRSCH3

PRS ch 3 is controlling TSTOP.

0x00000004 : PRSCH4

PRS ch 4 is controlling TSTOP.

0x00000005 : PRSCH5

PRS ch 5 is controlling TSTOP.

0x00000006 : PRSCH6

PRS ch 6 is controlling TSTOP.

0x00000007 : PRSCH7

PRS ch 7 is controlling TSTOP.

End of enumeration elements list.


ROUTELOC1

I/O Routing Location Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC1 ROUTELOC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH4LOC CH5LOC CH6LOC CH7LOC

CH4LOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.

CH5LOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.

CH6LOC : I/O Location
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.

CH7LOC : I/O Location
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.


CTRL

Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEVONPRS SEVONPRSSEL

SEVONPRS : Set Event on PRS
bits : 0 - 0 (1 bit)
access : read-write

SEVONPRSSEL : SEVONPRS PRS Channel Select
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

End of enumeration elements list.


DMAREQ0

DMA Request 0 Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAREQ0 DMAREQ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DMA Request 0 PRS Channel Select
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

End of enumeration elements list.


DMAREQ1

DMA Request 1 Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAREQ1 DMAREQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : DMA Request 1 PRS Channel Select
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

0x00000006 : PRSCH6

PRS Channel 6 selected

0x00000007 : PRSCH7

PRS Channel 7 selected

End of enumeration elements list.


SWLEVEL

Software Level Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWLEVEL SWLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0LEVEL CH1LEVEL CH2LEVEL CH3LEVEL CH4LEVEL CH5LEVEL CH6LEVEL CH7LEVEL

CH0LEVEL : Channel 0 Software Level
bits : 0 - 0 (1 bit)
access : read-write

CH1LEVEL : Channel 1 Software Level
bits : 1 - 1 (1 bit)
access : read-write

CH2LEVEL : Channel 2 Software Level
bits : 2 - 2 (1 bit)
access : read-write

CH3LEVEL : Channel 3 Software Level
bits : 3 - 3 (1 bit)
access : read-write

CH4LEVEL : Channel 4 Software Level
bits : 4 - 4 (1 bit)
access : read-write

CH5LEVEL : Channel 5 Software Level
bits : 5 - 5 (1 bit)
access : read-write

CH6LEVEL : Channel 6 Software Level
bits : 6 - 6 (1 bit)
access : read-write

CH7LEVEL : Channel 7 Software Level
bits : 7 - 7 (1 bit)
access : read-write


PEEK

PRS Channel Values
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PEEK PEEK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL CH1VAL CH2VAL CH3VAL CH4VAL CH5VAL CH6VAL CH7VAL

CH0VAL : Channel 0 Current Value
bits : 0 - 0 (1 bit)
access : read-only

CH1VAL : Channel 1 Current Value
bits : 1 - 1 (1 bit)
access : read-only

CH2VAL : Channel 2 Current Value
bits : 2 - 2 (1 bit)
access : read-only

CH3VAL : Channel 3 Current Value
bits : 3 - 3 (1 bit)
access : read-only

CH4VAL : Channel 4 Current Value
bits : 4 - 4 (1 bit)
access : read-only

CH5VAL : Channel 5 Current Value
bits : 5 - 5 (1 bit)
access : read-only

CH6VAL : Channel 6 Current Value
bits : 6 - 6 (1 bit)
access : read-only

CH7VAL : Channel 7 Current Value
bits : 7 - 7 (1 bit)
access : read-only


CH0_CTRL

Channel Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CTRL CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH1_CTRL

Channel Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CTRL CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH2_CTRL

Channel Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CTRL CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH3_CTRL

Channel Control Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CTRL CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH4_CTRL

Channel Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CTRL CH4_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH5_CTRL

Channel Control Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CTRL CH5_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH6_CTRL

Channel Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CTRL CH6_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


CH7_CTRL

Channel Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CTRL CH7_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL STRETCH INV ORPREV ANDNEXT ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : PRSL

Peripheral Reflex System

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000004 : ADC0

Analog to Digital Converter 0

0x00000005 : RTCC

Real-Time Counter and Calendar

0x00000006 : GPIOL

General purpose Input/Output

0x00000007 : GPIOH

General purpose Input/Output

0x00000008 : LETIMER0

Low Energy Timer 0

0x00000009 : PCNT0

Pulse Counter 0

0x0000000A : CRYOTIMER

CRYOTIMER

0x0000000B : CMU

Clock Management Unit

0x00000011 : VDAC0

Digital to Analog Converter 0

0x00000012 : LESENSEL

Low Energy Sensor Interface

0x00000013 : LESENSEH

Low Energy Sensor Interface

0x00000014 : LESENSED

Low Energy Sensor Interface

0x00000015 : LESENSE

Low Energy Sensor Interface

0x00000020 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000021 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000022 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x00000023 : USART3

Universal Synchronous/Asynchronous Receiver/Transmitter 3

0x00000024 : UART0

Universal Asynchronous Receiver/Transmitter 0

0x00000025 : TIMER0

Timer 0

0x00000026 : TIMER1

Timer 1

0x00000027 : WTIMER0

Wide Timer 0

0x00000028 : WTIMER1

Wide Timer 1

0x00000029 : CM0P

None

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

STRETCH : Stretch Channel Output
bits : 25 - 25 (1 bit)
access : read-write

INV : Invert Channel
bits : 26 - 26 (1 bit)
access : read-write

ORPREV : Or Previous
bits : 27 - 27 (1 bit)
access : read-write

ANDNEXT : And Next
bits : 28 - 28 (1 bit)
access : read-write

ASYNC : Asynchronous Reflex
bits : 30 - 30 (1 bit)
access : read-write


ROUTEPEN

I/O Routing Pin Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTEPEN ROUTEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PEN CH1PEN CH2PEN CH3PEN CH4PEN CH5PEN CH6PEN CH7PEN

CH0PEN : CH0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

CH1PEN : CH1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CH2PEN : CH2 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CH3PEN : CH3 Pin Enable
bits : 3 - 3 (1 bit)
access : read-write

CH4PEN : CH4 Pin Enable
bits : 4 - 4 (1 bit)
access : read-write

CH5PEN : CH5 Pin Enable
bits : 5 - 5 (1 bit)
access : read-write

CH6PEN : CH6 Pin Enable
bits : 6 - 6 (1 bit)
access : read-write

CH7PEN : CH7 Pin Enable
bits : 7 - 7 (1 bit)
access : read-write



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