\n

LCD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STATUS

AREGA

AREGB

IF

IFS

IFC

IEN

BIASCTRL

DISPCTRL

SEGD0L

SEGD1L

SEGD2L

SEGD3L

SEGD0H

SEGD1H

SEGD2H

SEGD3H

SEGD4L

SEGD5L

SEGD6L

SEGD7L

SEGD4H

SEGD5H

SEGD6H

SEGD7H

SEGEN

BACTRL

FREEZE

SYNCBUSY

FRAMERATE

SEGEN2


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN UDCTRL DSC

EN : LCD Enable
bits : 0 - 0 (1 bit)
access : read-write

UDCTRL : Update Data Control
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0x00000000 : REGULAR

The data transfer is controlled by SW. Transfer is performed as soon as possible

0x00000001 : FCEVENT

The data transfer is done at the next event triggered by the Frame Counter

0x00000002 : FRAMESTART

The data transfer is done continuously at every LCD frame start

End of enumeration elements list.

DSC : Direct Segment Control
bits : 23 - 23 (1 bit)
access : read-write


STATUS

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASTATE BLINK

ASTATE : Current Animation State
bits : 0 - 3 (4 bit)
access : read-only

BLINK : Blink State
bits : 8 - 8 (1 bit)
access : read-only


AREGA

Animation Register a
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREGA AREGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREGA

AREGA : Animation Register a Data
bits : 0 - 7 (8 bit)
access : read-write


AREGB

Animation Register B
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AREGB AREGB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREGB

AREGB : Animation Register B Data
bits : 0 - 7 (8 bit)
access : read-write


IF

Interrupt Flag Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC

FC : Frame Counter Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write


BIASCTRL

Analog BIAS Control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIASCTRL BIASCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEED BUFDRV BUFBIAS

SPEED : SPEED Adjustment
bits : 0 - 2 (3 bit)
access : read-write

BUFDRV : Buffer Drive Strength
bits : 4 - 7 (4 bit)
access : read-write

BUFBIAS : Buffer Bias Setting
bits : 10 - 12 (3 bit)
access : read-write


DISPCTRL

Display Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISPCTRL DISPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MUX WAVE CONTRAST CHGRDST BIAS MODE

MUX : Mux Configuration
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : STATIC

Static

0x00000001 : DUPLEX

Duplex

0x00000002 : TRIPLEX

Triplex

0x00000003 : QUADRUPLEX

Quadruplex

0x00000005 : SEXTAPLEX

Sextaplex

0x00000007 : OCTAPLEX

Octaplex

End of enumeration elements list.

WAVE : Waveform Selection
bits : 4 - 4 (1 bit)
access : read-write

CONTRAST : Contrast Control
bits : 8 - 13 (6 bit)
access : read-write

CHGRDST : Charge Redistribution Cycles
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Disable charge redistribution.

0x00000001 : ONE

Use 1 prescaled low frequency clock cycle for charge redistribution.

0x00000002 : TWO

Use 2 prescaled low frequency clock cycles for charge redistribution.

0x00000003 : THREE

Use 3 prescaled low frequency clock cycles for charge redistribution.

0x00000004 : FOUR

Use 4 prescaled low frequency clock cycles for charge redistribution.

End of enumeration elements list.

BIAS : Bias Configuration
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : STATIC

Static

0x00000001 : ONEHALF

1/2 Bias

0x00000002 : ONETHIRD

1/3 Bias

0x00000003 : ONEFOURTH

1/4 Bias

End of enumeration elements list.

MODE : Mode Setting
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x00000000 : NOEXTCAP

No External Cap. Uses an internal current source to generate VLCD. Use CONTRAST[4:0] to control VLCD.

0x00000001 : STEPDOWN

Use step down control with VLCD less than VDD. Use CONTRAST[5:0] to control VLCD level, and use SPEED to adjust VLCD drive strength.

0x00000002 : CPINTOSC

Charge pump used with internal oscillator. Use CONTRAST[5:0] to control VLCD level, and use SPEED to adjust oscillator frequency.

End of enumeration elements list.


SEGD0L

Segment Data Low Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD0L SEGD0L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD0L

SEGD0L : COM0 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD1L

Segment Data Low Register 1
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD1L SEGD1L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD1L

SEGD1L : COM1 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD2L

Segment Data Low Register 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD2L SEGD2L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD2L

SEGD2L : COM2 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD3L

Segment Data Low Register 3
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD3L SEGD3L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD3L

SEGD3L : COM3 Segment Data Low
bits : 0 - 31 (32 bit)
access : read-write


SEGD0H

Segment Data High Register 0
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD0H SEGD0H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD0H

SEGD0H : COM0 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD1H

Segment Data High Register 1
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD1H SEGD1H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD1H

SEGD1H : COM1 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD2H

Segment Data High Register 2
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD2H SEGD2H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD2H

SEGD2H : COM2 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD3H

Segment Data High Register 3
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD3H SEGD3H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD3H

SEGD3H : COM3 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD4L

Segment Data Low Register 4
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD4L SEGD4L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD4L

SEGD4L : COM4 Segment Data
bits : 0 - 31 (32 bit)
access : read-write


SEGD5L

Segment Data Low Register 5
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD5L SEGD5L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD5L

SEGD5L : COM5 Segment Data
bits : 0 - 31 (32 bit)
access : read-write


SEGD6L

Segment Data Low Register 6
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD6L SEGD6L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD6L

SEGD6L : COM6 Segment Data
bits : 0 - 31 (32 bit)
access : read-write


SEGD7L

Segment Data Low Register 7
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD7L SEGD7L read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD7L

SEGD7L : COM7 Segment Data
bits : 0 - 31 (32 bit)
access : read-write


SEGD4H

Segment Data High Register 4
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD4H SEGD4H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD4H

SEGD4H : COM0 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD5H

Segment Data High Register 5
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD5H SEGD5H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD5H

SEGD5H : COM1 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD6H

Segment Data High Register 6
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD6H SEGD6H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD6H

SEGD6H : COM2 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGD7H

Segment Data High Register 7
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGD7H SEGD7H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGD7H

SEGD7H : COM3 Segment Data High
bits : 0 - 7 (8 bit)
access : read-write


SEGEN

Segment Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGEN SEGEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGEN

SEGEN : Segment Enable
bits : 0 - 31 (32 bit)
access : read-write


BACTRL

Blink and Animation Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BACTRL BACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLINKEN BLANK AEN AREGASC AREGBSC ALOGSEL FCEN FCPRESC FCTOP ALOC

BLINKEN : Blink Enable
bits : 0 - 0 (1 bit)
access : read-write

BLANK : Blank Display
bits : 1 - 1 (1 bit)
access : read-write

AEN : Animation Enable
bits : 2 - 2 (1 bit)
access : read-write

AREGASC : Animate Register a Shift Control
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0x00000000 : NOSHIFT

No Shift operation on Animation Register A

0x00000001 : SHIFTLEFT

Animation Register A is shifted left

0x00000002 : SHIFTRIGHT

Animation Register A is shifted right

End of enumeration elements list.

AREGBSC : Animate Register B Shift Control
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0x00000000 : NOSHIFT

No Shift operation on Animation Register B

0x00000001 : SHIFTLEFT

Animation Register B is shifted left

0x00000002 : SHIFTRIGHT

Animation Register B is shifted right

End of enumeration elements list.

ALOGSEL : Animate Logic Function Select
bits : 7 - 7 (1 bit)
access : read-write

FCEN : Frame Counter Enable
bits : 8 - 8 (1 bit)
access : read-write

FCPRESC : Frame Counter Prescaler
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

CLKFC = CLKFRAME / 1

0x00000001 : DIV2

CLKFC = CLKFRAME / 2

0x00000002 : DIV4

CLKFC = CLKFRAME / 4

0x00000003 : DIV8

CLKFC = CLKFRAME / 8

End of enumeration elements list.

FCTOP : Frame Counter Top Value
bits : 18 - 23 (6 bit)
access : read-write

ALOC : Animation Location
bits : 28 - 28 (1 bit)
access : read-write


FREEZE

Freeze Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FREEZE FREEZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE LCDGATE

REGFREEZE : Register Update Freeze
bits : 0 - 0 (1 bit)
access : read-write

LCDGATE : LCD Gate
bits : 1 - 1 (1 bit)
access : read-write


SYNCBUSY

Synchronization Busy Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL BACTRL AREGA AREGB SEGD0L SEGD1L SEGD2L SEGD3L SEGD0H SEGD1H SEGD2H SEGD3H SEGD4L SEGD5L SEGD6L SEGD7L SEGD4H SEGD5H SEGD6H SEGD7H

CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only

BACTRL : BACTRL Register Busy
bits : 1 - 1 (1 bit)
access : read-only

AREGA : AREGA Register Busy
bits : 2 - 2 (1 bit)
access : read-only

AREGB : AREGB Register Busy
bits : 3 - 3 (1 bit)
access : read-only

SEGD0L : SEGD0L Register Busy
bits : 4 - 4 (1 bit)
access : read-only

SEGD1L : SEGD1L Register Busy
bits : 5 - 5 (1 bit)
access : read-only

SEGD2L : SEGD2L Register Busy
bits : 6 - 6 (1 bit)
access : read-only

SEGD3L : SEGD3L Register Busy
bits : 7 - 7 (1 bit)
access : read-only

SEGD0H : SEGD0H Register Busy
bits : 8 - 8 (1 bit)
access : read-only

SEGD1H : SEGD1H Register Busy
bits : 9 - 9 (1 bit)
access : read-only

SEGD2H : SEGD2H Register Busy
bits : 10 - 10 (1 bit)
access : read-only

SEGD3H : SEGD3H Register Busy
bits : 11 - 11 (1 bit)
access : read-only

SEGD4L : SEGD4L Register Busy
bits : 12 - 12 (1 bit)
access : read-only

SEGD5L : SEGD5L Register Busy
bits : 13 - 13 (1 bit)
access : read-only

SEGD6L : SEGD6L Register Busy
bits : 14 - 14 (1 bit)
access : read-only

SEGD7L : SEGD7L Register Busy
bits : 15 - 15 (1 bit)
access : read-only

SEGD4H : SEGD4H Register Busy
bits : 16 - 16 (1 bit)
access : read-only

SEGD5H : SEGD5H Register Busy
bits : 17 - 17 (1 bit)
access : read-only

SEGD6H : SEGD6H Register Busy
bits : 18 - 18 (1 bit)
access : read-only

SEGD7H : SEGD7H Register Busy
bits : 19 - 19 (1 bit)
access : read-only


FRAMERATE

Frame Rate
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAMERATE FRAMERATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRDIV

FRDIV : Frame Rate Divider
bits : 0 - 8 (9 bit)
access : read-write


SEGEN2

Segment Enable (32 to 39)
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEGEN2 SEGEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGEN2

SEGEN2 : Segment Enable (second Group)
bits : 0 - 3 (4 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.