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VDAC0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CMD

OPA3_APORTREQ

OPA3_APORTCONFLICT

OPA3_CTRL

OPA3_TIMER

OPA3_MUX

OPA3_OUT

OPA3_CAL

IF

IFS

IFC

IEN

CH0DATA

CH1DATA

COMBDATA

CAL

STATUS

CH0CTRL

OPA0_APORTREQ

OPA0_APORTCONFLICT

OPA0_CTRL

OPA0_TIMER

OPA0_MUX

OPA0_OUT

OPA0_CAL

CH1CTRL

OPA1_APORTREQ

OPA1_APORTCONFLICT

OPA1_CTRL

OPA1_TIMER

OPA1_MUX

OPA1_OUT

OPA1_CAL

OPA2_APORTREQ

OPA2_APORTCONFLICT

OPA2_CTRL

OPA2_TIMER

OPA2_MUX

OPA2_OUT

OPA2_CAL


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIFF SINEMODE OUTENPRS CH0PRESCRST REFSEL PRESC REFRESHPERIOD WARMUPMODE DACCLKMODE

DIFF : Differential Mode
bits : 0 - 0 (1 bit)
access : read-write

SINEMODE : Sine Mode
bits : 4 - 4 (1 bit)
access : read-write

OUTENPRS : PRS Controlled Output Enable
bits : 5 - 5 (1 bit)
access : read-write

CH0PRESCRST : Channel 0 Start Reset Prescaler
bits : 6 - 6 (1 bit)
access : read-write

REFSEL : Reference Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x00000000 : 1V25LN

Internal low noise 1.25 V bandgap reference

0x00000001 : 2V5LN

Internal low noise 2.5 V bandgap reference

0x00000002 : 1V25

Internal 1.25 V bandgap reference

0x00000003 : 2V5

Internal 2.5 V bandgap reference

0x00000004 : VDD

AVDD reference

0x00000006 : EXT

External pin reference

End of enumeration elements list.

PRESC : Prescaler Setting for DAC Clock
bits : 16 - 22 (7 bit)
access : read-write

Enumeration:

0x00000000 : NODIVISION

None

End of enumeration elements list.

REFRESHPERIOD : Refresh Period
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : 8CYCLES

All channels with enabled refresh are refreshed every 8 DAC_CLK cycles

0x00000001 : 16CYCLES

All channels with enabled refresh are refreshed every 16 DAC_CLK cycles

0x00000002 : 32CYCLES

All channels with enabled refresh are refreshed every 32 DAC_CLK cycles

0x00000003 : 64CYCLES

All channels with enabled refresh are refreshed every 64 DAC_CLK cycles

End of enumeration elements list.

WARMUPMODE : Warm-up Mode
bits : 28 - 28 (1 bit)
access : read-write

DACCLKMODE : Clock Mode
bits : 31 - 31 (1 bit)
access : read-write


CMD

Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0EN CH0DIS CH1EN CH1DIS OPA0EN OPA0DIS OPA1EN OPA1DIS OPA2EN OPA2DIS OPA3EN OPA3DIS

CH0EN : DAC Channel 0 Enable
bits : 0 - 0 (1 bit)
access : write-only

CH0DIS : DAC Channel 0 Disable
bits : 1 - 1 (1 bit)
access : write-only

CH1EN : DAC Channel 1 Enable
bits : 2 - 2 (1 bit)
access : write-only

CH1DIS : DAC Channel 1 Disable
bits : 3 - 3 (1 bit)
access : write-only

OPA0EN : OPA0 Enable
bits : 16 - 16 (1 bit)
access : write-only

OPA0DIS : OPA0 Disable
bits : 17 - 17 (1 bit)
access : write-only

OPA1EN : OPA1 Enable
bits : 18 - 18 (1 bit)
access : write-only

OPA1DIS : OPA1 Disable
bits : 19 - 19 (1 bit)
access : write-only

OPA2EN : OPA2 Enable
bits : 20 - 20 (1 bit)
access : write-only

OPA2DIS : OPA2 Disable
bits : 21 - 21 (1 bit)
access : write-only

OPA3EN : OPA3 Enable
bits : 22 - 22 (1 bit)
access : write-only

OPA3DIS : OPA3 Disable
bits : 23 - 23 (1 bit)
access : write-only


OPA3_APORTREQ

Operational Amplifier APORT Request Status Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA3_APORTREQ OPA3_APORTREQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XREQ APORT1YREQ APORT2XREQ APORT2YREQ APORT3XREQ APORT3YREQ APORT4XREQ APORT4YREQ

APORT1XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 2 - 2 (1 bit)
access : read-only

APORT1YREQ : 1 If the Bus Connected to APORT1X is Requested
bits : 3 - 3 (1 bit)
access : read-only

APORT2XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 4 - 4 (1 bit)
access : read-only

APORT2YREQ : 1 If the Bus Connected to APORT2Y is Requested
bits : 5 - 5 (1 bit)
access : read-only

APORT3XREQ : 1 If the Bus Connected to APORT3X is Requested
bits : 6 - 6 (1 bit)
access : read-only

APORT3YREQ : 1 If the Bus Connected to APORT3Y is Requested
bits : 7 - 7 (1 bit)
access : read-only

APORT4XREQ : 1 If the Bus Connected to APORT4X is Requested
bits : 8 - 8 (1 bit)
access : read-only

APORT4YREQ : 1 If the Bus Connected to APORT4Y is Requested
bits : 9 - 9 (1 bit)
access : read-only


OPA3_APORTCONFLICT

Operational Amplifier APORT Conflict Status Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA3_APORTCONFLICT OPA3_APORTCONFLICT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XCONFLICT APORT1YCONFLICT APORT2XCONFLICT APORT2YCONFLICT APORT3XCONFLICT APORT3YCONFLICT APORT4XCONFLICT APORT4YCONFLICT

APORT1XCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 2 - 2 (1 bit)
access : read-only

APORT1YCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 3 - 3 (1 bit)
access : read-only

APORT2XCONFLICT : 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral
bits : 4 - 4 (1 bit)
access : read-only

APORT2YCONFLICT : 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral
bits : 5 - 5 (1 bit)
access : read-only

APORT3XCONFLICT : 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral
bits : 6 - 6 (1 bit)
access : read-only

APORT3YCONFLICT : 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral
bits : 7 - 7 (1 bit)
access : read-only

APORT4XCONFLICT : 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral
bits : 8 - 8 (1 bit)
access : read-only

APORT4YCONFLICT : 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral
bits : 9 - 9 (1 bit)
access : read-only


OPA3_CTRL

Operational Amplifier Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA3_CTRL OPA3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRIVESTRENGTH INCBW HCMDIS OUTSCALE PRSEN PRSMODE PRSSEL PRSOUTMODE APORTXMASTERDIS APORTYMASTERDIS

DRIVESTRENGTH : OPAx Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : 0

Lower accuracy with Low drive strength.

0x00000001 : 1

Low accuracy with Low drive strength.

0x00000002 : 2

High accuracy with High drive strength.

0x00000003 : 3

Higher accuracy with High drive strength.

End of enumeration elements list.

INCBW : OPAx Unity Gain Bandwidth Scale
bits : 2 - 2 (1 bit)
access : read-write

HCMDIS : High Common Mode Disable
bits : 3 - 3 (1 bit)
access : read-write

OUTSCALE : Scale OPAx Output Driving Strength
bits : 4 - 4 (1 bit)
access : read-write

PRSEN : OPAx PRS Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write

PRSMODE : OPAx PRS Trigger Mode
bits : 9 - 9 (1 bit)
access : read-write

PRSSEL : OPAx PRS Trigger Select
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 triggers OPA.

0x00000001 : PRSCH1

PRS ch 1 triggers OPA.

0x00000002 : PRSCH2

PRS ch 2 triggers OPA.

0x00000003 : PRSCH3

PRS ch 3 triggers OPA.

0x00000004 : PRSCH4

PRS ch 4 triggers OPA.

0x00000005 : PRSCH5

PRS ch 5 triggers OPA.

0x00000006 : PRSCH6

PRS ch 6 triggers OPA.

0x00000007 : PRSCH7

PRS ch 7 triggers OPA.

End of enumeration elements list.

PRSOUTMODE : OPAx PRS Output Select
bits : 16 - 16 (1 bit)
access : read-write

APORTXMASTERDIS : APORT Bus Master Disable
bits : 20 - 20 (1 bit)
access : read-write

APORTYMASTERDIS : APORT Bus Master Disable
bits : 21 - 21 (1 bit)
access : read-write


OPA3_TIMER

Operational Amplifier Timer Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA3_TIMER OPA3_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTUPDLY WARMUPTIME SETTLETIME

STARTUPDLY : OPAx Startup Delay Count Value
bits : 0 - 5 (6 bit)
access : read-write

WARMUPTIME : OPAx Warmup Time Count Value
bits : 8 - 14 (7 bit)
access : read-write

SETTLETIME : OPAx Output Settling Timeout Value
bits : 16 - 25 (10 bit)
access : read-write


OPA3_MUX

Operational Amplifier Mux Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA3_MUX OPA3_MUX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSSEL NEGSEL RESINMUX GAIN3X RESSEL

POSSEL : OPAx Non-inverting Input Mux
bits : 0 - 7 (8 bit)
access : read-write

NEGSEL : OPAx Inverting Input Mux
bits : 8 - 15 (8 bit)
access : read-write

RESINMUX : OPAx Resistor Ladder Input Mux
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Set for Unity Gain

0x00000001 : OPANEXT

Set for NEXTOUT(x-1) input

0x00000002 : NEGPAD

NEG pad connected

0x00000003 : POSPAD

POS pad connected

0x00000004 : COMPAD

Neg pad of OPA0 connected. Direct input to support common reference.

0x00000005 : CENTER

OPA0 and OPA1 Resmux connected to form fully differential instrumentation amplifier.

0x00000006 : VSS

VSS connected

End of enumeration elements list.

GAIN3X : OPAx Dedicated 3x Gain Resistor Ladder
bits : 20 - 20 (1 bit)
access : read-write

RESSEL : OPAx Resistor Ladder Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : RES0

Gain of 1/3

0x00000001 : RES1

Gain of 1

0x00000002 : RES2

Gain of 1 2/3

0x00000003 : RES3

Gain of 2 1/5

0x00000004 : RES4

Gain of 3

0x00000005 : RES5

Gain of 4 1/3

0x00000006 : RES6

Gain of 7

0x00000007 : RES7

Gain of 15

End of enumeration elements list.


OPA3_OUT

Operational Amplifier Output Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA3_OUT OPA3_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAINOUTEN ALTOUTEN APORTOUTEN SHORT ALTOUTPADEN APORTOUTSEL

MAINOUTEN : OPAx Main Output Enable
bits : 0 - 0 (1 bit)
access : read-write

ALTOUTEN : OPAx Alternative Output Enable
bits : 1 - 1 (1 bit)
access : read-write

APORTOUTEN : OPAx Aport Output Enable
bits : 2 - 2 (1 bit)
access : read-write

SHORT : OPAx Main and Alternative Output Short
bits : 3 - 3 (1 bit)
access : read-write

ALTOUTPADEN : OPAx Output Enable Value
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0x00000001 : OUT0

Alternate Output 0

0x00000002 : OUT1

Alternate Output 1

0x00000004 : OUT2

Alternate Output 2

0x00000008 : OUT3

Alternate Output 3

0x00000010 : OUT4

Alternate Output 4

End of enumeration elements list.

APORTOUTSEL : OPAx APORT Output
bits : 16 - 23 (8 bit)
access : read-write


OPA3_CAL

Operational Amplifier Calibration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA3_CAL OPA3_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM1 CM2 CM3 GM GM3 OFFSETP OFFSETN

CM1 : Compensation Cap Cm1 Trim Value
bits : 0 - 3 (4 bit)
access : read-write

CM2 : Compensation Cap Cm2 Trim Value
bits : 5 - 8 (4 bit)
access : read-write

CM3 : Compensation Cap Cm3 Trim Value
bits : 10 - 11 (2 bit)
access : read-write

GM : Gm Trim Value
bits : 13 - 15 (3 bit)
access : read-write

GM3 : Gm3 Trim Value
bits : 17 - 18 (2 bit)
access : read-write

OFFSETP : OPAx Non-Inverting Input Offset Configuration Value
bits : 20 - 24 (5 bit)
access : read-write

OFFSETN : OPAx Inverting Input Offset Configuration Value
bits : 26 - 30 (5 bit)
access : read-write


IF

Interrupt Flag Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CD CH1CD CH0OF CH1OF CH0UF CH1UF CH0BL CH1BL EM23ERR OPA0APORTCONFLICT OPA1APORTCONFLICT OPA2APORTCONFLICT OPA3APORTCONFLICT OPA0PRSTIMEDERR OPA1PRSTIMEDERR OPA2PRSTIMEDERR OPA3PRSTIMEDERR OPA0OUTVALID OPA1OUTVALID OPA2OUTVALID OPA3OUTVALID

CH0CD : Channel 0 Conversion Done Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

CH1CD : Channel 1 Conversion Done Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

CH0OF : Channel 0 Data Overflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

CH1OF : Channel 1 Data Overflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

CH0UF : Channel 0 Data Underflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

CH1UF : Channel 1 Data Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only

CH0BL : Channel 0 Buffer Level Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only

CH1BL : Channel 1 Buffer Level Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

EM23ERR : EM2/3 Entry Error Flag
bits : 15 - 15 (1 bit)
access : read-only

OPA0APORTCONFLICT : OPA0 Bus Conflict Output Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only

OPA1APORTCONFLICT : OPA1 Bus Conflict Output Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-only

OPA2APORTCONFLICT : OPA2 Bus Conflict Output Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-only

OPA3APORTCONFLICT : OPA3 Bus Conflict Output Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-only

OPA0PRSTIMEDERR : OPA0 PRS Trigger Mode Error Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-only

OPA1PRSTIMEDERR : OPA1 PRS Trigger Mode Error Interrupt Flag
bits : 21 - 21 (1 bit)
access : read-only

OPA2PRSTIMEDERR : OPA2 PRS Trigger Mode Error Interrupt Flag
bits : 22 - 22 (1 bit)
access : read-only

OPA3PRSTIMEDERR : OPA3 PRS Trigger Mode Error Interrupt Flag
bits : 23 - 23 (1 bit)
access : read-only

OPA0OUTVALID : OPA0 Output Valid Interrupt Flag
bits : 28 - 28 (1 bit)
access : read-only

OPA1OUTVALID : OPA1 Output Valid Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-only

OPA2OUTVALID : OPA3 Output Valid Interrupt Flag
bits : 30 - 30 (1 bit)
access : read-only

OPA3OUTVALID : OPA3 Output Valid Interrupt Flag
bits : 31 - 31 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CD CH1CD CH0OF CH1OF CH0UF CH1UF EM23ERR OPA0APORTCONFLICT OPA1APORTCONFLICT OPA2APORTCONFLICT OPA3APORTCONFLICT OPA0PRSTIMEDERR OPA1PRSTIMEDERR OPA2PRSTIMEDERR OPA3PRSTIMEDERR OPA0OUTVALID OPA1OUTVALID OPA2OUTVALID OPA3OUTVALID

CH0CD : Set CH0CD Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

CH1CD : Set CH1CD Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

CH0OF : Set CH0OF Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

CH1OF : Set CH1OF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

CH0UF : Set CH0UF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

CH1UF : Set CH1UF Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

EM23ERR : Set EM23ERR Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

OPA0APORTCONFLICT : Set OPA0APORTCONFLICT Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

OPA1APORTCONFLICT : Set OPA1APORTCONFLICT Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

OPA2APORTCONFLICT : Set OPA2APORTCONFLICT Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only

OPA3APORTCONFLICT : Set OPA3APORTCONFLICT Interrupt Flag
bits : 19 - 19 (1 bit)
access : write-only

OPA0PRSTIMEDERR : Set OPA0PRSTIMEDERR Interrupt Flag
bits : 20 - 20 (1 bit)
access : write-only

OPA1PRSTIMEDERR : Set OPA1PRSTIMEDERR Interrupt Flag
bits : 21 - 21 (1 bit)
access : write-only

OPA2PRSTIMEDERR : Set OPA2PRSTIMEDERR Interrupt Flag
bits : 22 - 22 (1 bit)
access : write-only

OPA3PRSTIMEDERR : Set OPA3PRSTIMEDERR Interrupt Flag
bits : 23 - 23 (1 bit)
access : write-only

OPA0OUTVALID : Set OPA0OUTVALID Interrupt Flag
bits : 28 - 28 (1 bit)
access : write-only

OPA1OUTVALID : Set OPA1OUTVALID Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only

OPA2OUTVALID : Set OPA2OUTVALID Interrupt Flag
bits : 30 - 30 (1 bit)
access : write-only

OPA3OUTVALID : Set OPA3OUTVALID Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CD CH1CD CH0OF CH1OF CH0UF CH1UF EM23ERR OPA0APORTCONFLICT OPA1APORTCONFLICT OPA2APORTCONFLICT OPA3APORTCONFLICT OPA0PRSTIMEDERR OPA1PRSTIMEDERR OPA2PRSTIMEDERR OPA3PRSTIMEDERR OPA0OUTVALID OPA1OUTVALID OPA2OUTVALID OPA3OUTVALID

CH0CD : Clear CH0CD Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

CH1CD : Clear CH1CD Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

CH0OF : Clear CH0OF Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

CH1OF : Clear CH1OF Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

CH0UF : Clear CH0UF Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

CH1UF : Clear CH1UF Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

EM23ERR : Clear EM23ERR Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

OPA0APORTCONFLICT : Clear OPA0APORTCONFLICT Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

OPA1APORTCONFLICT : Clear OPA1APORTCONFLICT Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

OPA2APORTCONFLICT : Clear OPA2APORTCONFLICT Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only

OPA3APORTCONFLICT : Clear OPA3APORTCONFLICT Interrupt Flag
bits : 19 - 19 (1 bit)
access : write-only

OPA0PRSTIMEDERR : Clear OPA0PRSTIMEDERR Interrupt Flag
bits : 20 - 20 (1 bit)
access : write-only

OPA1PRSTIMEDERR : Clear OPA1PRSTIMEDERR Interrupt Flag
bits : 21 - 21 (1 bit)
access : write-only

OPA2PRSTIMEDERR : Clear OPA2PRSTIMEDERR Interrupt Flag
bits : 22 - 22 (1 bit)
access : write-only

OPA3PRSTIMEDERR : Clear OPA3PRSTIMEDERR Interrupt Flag
bits : 23 - 23 (1 bit)
access : write-only

OPA0OUTVALID : Clear OPA0OUTVALID Interrupt Flag
bits : 28 - 28 (1 bit)
access : write-only

OPA1OUTVALID : Clear OPA1OUTVALID Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only

OPA2OUTVALID : Clear OPA2OUTVALID Interrupt Flag
bits : 30 - 30 (1 bit)
access : write-only

OPA3OUTVALID : Clear OPA3OUTVALID Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0CD CH1CD CH0OF CH1OF CH0UF CH1UF CH0BL CH1BL EM23ERR OPA0APORTCONFLICT OPA1APORTCONFLICT OPA2APORTCONFLICT OPA3APORTCONFLICT OPA0PRSTIMEDERR OPA1PRSTIMEDERR OPA2PRSTIMEDERR OPA3PRSTIMEDERR OPA0OUTVALID OPA1OUTVALID OPA2OUTVALID OPA3OUTVALID

CH0CD : CH0CD Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

CH1CD : CH1CD Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

CH0OF : CH0OF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

CH1OF : CH1OF Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

CH0UF : CH0UF Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

CH1UF : CH1UF Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

CH0BL : CH0BL Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

CH1BL : CH1BL Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

EM23ERR : EM23ERR Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write

OPA0APORTCONFLICT : OPA0APORTCONFLICT Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

OPA1APORTCONFLICT : OPA1APORTCONFLICT Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

OPA2APORTCONFLICT : OPA2APORTCONFLICT Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

OPA3APORTCONFLICT : OPA3APORTCONFLICT Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

OPA0PRSTIMEDERR : OPA0PRSTIMEDERR Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write

OPA1PRSTIMEDERR : OPA1PRSTIMEDERR Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write

OPA2PRSTIMEDERR : OPA2PRSTIMEDERR Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write

OPA3PRSTIMEDERR : OPA3PRSTIMEDERR Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write

OPA0OUTVALID : OPA0OUTVALID Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write

OPA1OUTVALID : OPA1OUTVALID Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write

OPA2OUTVALID : OPA2OUTVALID Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write

OPA3OUTVALID : OPA3OUTVALID Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write


CH0DATA

Channel 0 Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DATA CH0DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Channel 0 Data
bits : 0 - 11 (12 bit)
access : read-write


CH1DATA

Channel 1 Data Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1DATA CH1DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Channel 1 Data
bits : 0 - 11 (12 bit)
access : read-write


COMBDATA

Combined Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMBDATA COMBDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0DATA CH1DATA

CH0DATA : Channel 0 Data
bits : 0 - 11 (12 bit)
access : read-write

CH1DATA : Channel 1 Data
bits : 16 - 27 (12 bit)
access : read-write


CAL

Calibration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAL CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSETTRIM GAINERRTRIM GAINERRTRIMCH1

OFFSETTRIM : Input Buffer Offset Calibration Value
bits : 0 - 2 (3 bit)
access : read-write

GAINERRTRIM : Gain Error Trim Value
bits : 8 - 13 (6 bit)
access : read-write

GAINERRTRIMCH1 : Gain Error Trim Value for CH1
bits : 16 - 19 (4 bit)
access : read-write


STATUS

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0ENS CH1ENS CH0BL CH1BL CH0WARM CH1WARM OPA0APORTCONFLICT OPA1APORTCONFLICT OPA2APORTCONFLICT OPA3APORTCONFLICT OPA0ENS OPA1ENS OPA2ENS OPA3ENS OPA0WARM OPA1WARM OPA2WARM OPA3WARM OPA0OUTVALID OPA1OUTVALID OPA2OUTVALID OPA3OUTVALID

CH0ENS : Channel 0 Enabled Status
bits : 0 - 0 (1 bit)
access : read-only

CH1ENS : Channel 1 Enabled Status
bits : 1 - 1 (1 bit)
access : read-only

CH0BL : Channel 0 Buffer Level
bits : 2 - 2 (1 bit)
access : read-only

CH1BL : Channel 1 Buffer Level
bits : 3 - 3 (1 bit)
access : read-only

CH0WARM : Channel 0 Warm
bits : 4 - 4 (1 bit)
access : read-only

CH1WARM : Channel 1 Warm
bits : 5 - 5 (1 bit)
access : read-only

OPA0APORTCONFLICT : OPA0 Bus Conflict Output
bits : 16 - 16 (1 bit)
access : read-only

OPA1APORTCONFLICT : OPA1 Bus Conflict Output
bits : 17 - 17 (1 bit)
access : read-only

OPA2APORTCONFLICT : OPA2 Bus Conflict Output
bits : 18 - 18 (1 bit)
access : read-only

OPA3APORTCONFLICT : OPA3 Bus Conflict Output
bits : 19 - 19 (1 bit)
access : read-only

OPA0ENS : OPA0 Enabled Status
bits : 20 - 20 (1 bit)
access : read-only

OPA1ENS : OPA1 Enabled Status
bits : 21 - 21 (1 bit)
access : read-only

OPA2ENS : OPA2 Enabled Status
bits : 22 - 22 (1 bit)
access : read-only

OPA3ENS : OPA3 Enabled Status
bits : 23 - 23 (1 bit)
access : read-only

OPA0WARM : OPA0 Warm Status
bits : 24 - 24 (1 bit)
access : read-only

OPA1WARM : OPA1 Warm Status
bits : 25 - 25 (1 bit)
access : read-only

OPA2WARM : OPA2 Warm Status
bits : 26 - 26 (1 bit)
access : read-only

OPA3WARM : OPA3 Warm Status
bits : 27 - 27 (1 bit)
access : read-only

OPA0OUTVALID : OPA0 Output Valid Status
bits : 28 - 28 (1 bit)
access : read-only

OPA1OUTVALID : OPA1 Output Valid Status
bits : 29 - 29 (1 bit)
access : read-only

OPA2OUTVALID : OPA2 Output Valid Status
bits : 30 - 30 (1 bit)
access : read-only

OPA3OUTVALID : OPA3 Output Valid Status
bits : 31 - 31 (1 bit)
access : read-only


CH0CTRL

Channel 0 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0CTRL CH0CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONVMODE TRIGMODE PRSASYNC PRSSEL

CONVMODE : Conversion Mode
bits : 0 - 0 (1 bit)
access : read-write

TRIGMODE : Channel 0 Trigger Mode
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x00000000 : SW

Channel 0 is triggered by CH0DATA or COMBDATA write

0x00000001 : PRS

Channel 0 is triggered by PRS input

0x00000002 : REFRESH

Channel 0 is triggered by Refresh timer

0x00000003 : SWPRS

Channel 0 is triggered by CH0DATA/COMBDATA write or PRS input

0x00000004 : SWREFRESH

Channel 0 is triggered by CH0DATA/COMBDATA write or Refresh timer

0x00000005 : LESENSE

Channel 0 is triggered by LESENSE

End of enumeration elements list.

PRSASYNC : Channel 0 PRS Asynchronous Enable
bits : 8 - 8 (1 bit)
access : read-write

PRSSEL : Channel 0 PRS Trigger Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 triggers a conversion.

0x00000001 : PRSCH1

PRS ch 1 triggers a conversion.

0x00000002 : PRSCH2

PRS ch 2 triggers a conversion.

0x00000003 : PRSCH3

PRS ch 3 triggers a conversion.

0x00000004 : PRSCH4

PRS ch 4 triggers a conversion.

0x00000005 : PRSCH5

PRS ch 5 triggers a conversion.

0x00000006 : PRSCH6

PRS ch 6 triggers a conversion.

0x00000007 : PRSCH7

PRS ch 7 triggers a conversion.

End of enumeration elements list.


OPA0_APORTREQ

Operational Amplifier APORT Request Status Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA0_APORTREQ OPA0_APORTREQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XREQ APORT1YREQ APORT2XREQ APORT2YREQ APORT3XREQ APORT3YREQ APORT4XREQ APORT4YREQ

APORT1XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 2 - 2 (1 bit)
access : read-only

APORT1YREQ : 1 If the Bus Connected to APORT1X is Requested
bits : 3 - 3 (1 bit)
access : read-only

APORT2XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 4 - 4 (1 bit)
access : read-only

APORT2YREQ : 1 If the Bus Connected to APORT2Y is Requested
bits : 5 - 5 (1 bit)
access : read-only

APORT3XREQ : 1 If the Bus Connected to APORT3X is Requested
bits : 6 - 6 (1 bit)
access : read-only

APORT3YREQ : 1 If the Bus Connected to APORT3Y is Requested
bits : 7 - 7 (1 bit)
access : read-only

APORT4XREQ : 1 If the Bus Connected to APORT4X is Requested
bits : 8 - 8 (1 bit)
access : read-only

APORT4YREQ : 1 If the Bus Connected to APORT4Y is Requested
bits : 9 - 9 (1 bit)
access : read-only


OPA0_APORTCONFLICT

Operational Amplifier APORT Conflict Status Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA0_APORTCONFLICT OPA0_APORTCONFLICT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XCONFLICT APORT1YCONFLICT APORT2XCONFLICT APORT2YCONFLICT APORT3XCONFLICT APORT3YCONFLICT APORT4XCONFLICT APORT4YCONFLICT

APORT1XCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 2 - 2 (1 bit)
access : read-only

APORT1YCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 3 - 3 (1 bit)
access : read-only

APORT2XCONFLICT : 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral
bits : 4 - 4 (1 bit)
access : read-only

APORT2YCONFLICT : 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral
bits : 5 - 5 (1 bit)
access : read-only

APORT3XCONFLICT : 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral
bits : 6 - 6 (1 bit)
access : read-only

APORT3YCONFLICT : 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral
bits : 7 - 7 (1 bit)
access : read-only

APORT4XCONFLICT : 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral
bits : 8 - 8 (1 bit)
access : read-only

APORT4YCONFLICT : 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral
bits : 9 - 9 (1 bit)
access : read-only


OPA0_CTRL

Operational Amplifier Control Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA0_CTRL OPA0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRIVESTRENGTH INCBW HCMDIS OUTSCALE PRSEN PRSMODE PRSSEL PRSOUTMODE APORTXMASTERDIS APORTYMASTERDIS

DRIVESTRENGTH : OPAx Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : 0

Lower accuracy with Low drive strength.

0x00000001 : 1

Low accuracy with Low drive strength.

0x00000002 : 2

High accuracy with High drive strength.

0x00000003 : 3

Higher accuracy with High drive strength.

End of enumeration elements list.

INCBW : OPAx Unity Gain Bandwidth Scale
bits : 2 - 2 (1 bit)
access : read-write

HCMDIS : High Common Mode Disable
bits : 3 - 3 (1 bit)
access : read-write

OUTSCALE : Scale OPAx Output Driving Strength
bits : 4 - 4 (1 bit)
access : read-write

PRSEN : OPAx PRS Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write

PRSMODE : OPAx PRS Trigger Mode
bits : 9 - 9 (1 bit)
access : read-write

PRSSEL : OPAx PRS Trigger Select
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 triggers OPA.

0x00000001 : PRSCH1

PRS ch 1 triggers OPA.

0x00000002 : PRSCH2

PRS ch 2 triggers OPA.

0x00000003 : PRSCH3

PRS ch 3 triggers OPA.

0x00000004 : PRSCH4

PRS ch 4 triggers OPA.

0x00000005 : PRSCH5

PRS ch 5 triggers OPA.

0x00000006 : PRSCH6

PRS ch 6 triggers OPA.

0x00000007 : PRSCH7

PRS ch 7 triggers OPA.

End of enumeration elements list.

PRSOUTMODE : OPAx PRS Output Select
bits : 16 - 16 (1 bit)
access : read-write

APORTXMASTERDIS : APORT Bus Master Disable
bits : 20 - 20 (1 bit)
access : read-write

APORTYMASTERDIS : APORT Bus Master Disable
bits : 21 - 21 (1 bit)
access : read-write


OPA0_TIMER

Operational Amplifier Timer Control Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA0_TIMER OPA0_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTUPDLY WARMUPTIME SETTLETIME

STARTUPDLY : OPAx Startup Delay Count Value
bits : 0 - 5 (6 bit)
access : read-write

WARMUPTIME : OPAx Warmup Time Count Value
bits : 8 - 14 (7 bit)
access : read-write

SETTLETIME : OPAx Output Settling Timeout Value
bits : 16 - 25 (10 bit)
access : read-write


OPA0_MUX

Operational Amplifier Mux Configuration Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA0_MUX OPA0_MUX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSSEL NEGSEL RESINMUX GAIN3X RESSEL

POSSEL : OPAx Non-inverting Input Mux
bits : 0 - 7 (8 bit)
access : read-write

NEGSEL : OPAx Inverting Input Mux
bits : 8 - 15 (8 bit)
access : read-write

RESINMUX : OPAx Resistor Ladder Input Mux
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Set for Unity Gain

0x00000001 : OPANEXT

Set for NEXTOUT(x-1) input

0x00000002 : NEGPAD

NEG pad connected

0x00000003 : POSPAD

POS pad connected

0x00000004 : COMPAD

Neg pad of OPA0 connected. Direct input to support common reference.

0x00000005 : CENTER

OPA0 and OPA1 Resmux connected to form fully differential instrumentation amplifier.

0x00000006 : VSS

VSS connected

End of enumeration elements list.

GAIN3X : OPAx Dedicated 3x Gain Resistor Ladder
bits : 20 - 20 (1 bit)
access : read-write

RESSEL : OPAx Resistor Ladder Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : RES0

Gain of 1/3

0x00000001 : RES1

Gain of 1

0x00000002 : RES2

Gain of 1 2/3

0x00000003 : RES3

Gain of 2 1/5

0x00000004 : RES4

Gain of 3

0x00000005 : RES5

Gain of 4 1/3

0x00000006 : RES6

Gain of 7

0x00000007 : RES7

Gain of 15

End of enumeration elements list.


OPA0_OUT

Operational Amplifier Output Configuration Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA0_OUT OPA0_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAINOUTEN ALTOUTEN APORTOUTEN SHORT ALTOUTPADEN APORTOUTSEL

MAINOUTEN : OPAx Main Output Enable
bits : 0 - 0 (1 bit)
access : read-write

ALTOUTEN : OPAx Alternative Output Enable
bits : 1 - 1 (1 bit)
access : read-write

APORTOUTEN : OPAx Aport Output Enable
bits : 2 - 2 (1 bit)
access : read-write

SHORT : OPAx Main and Alternative Output Short
bits : 3 - 3 (1 bit)
access : read-write

ALTOUTPADEN : OPAx Output Enable Value
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0x00000001 : OUT0

Alternate Output 0

0x00000002 : OUT1

Alternate Output 1

0x00000004 : OUT2

Alternate Output 2

0x00000008 : OUT3

Alternate Output 3

0x00000010 : OUT4

Alternate Output 4

End of enumeration elements list.

APORTOUTSEL : OPAx APORT Output
bits : 16 - 23 (8 bit)
access : read-write


OPA0_CAL

Operational Amplifier Calibration Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA0_CAL OPA0_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM1 CM2 CM3 GM GM3 OFFSETP OFFSETN

CM1 : Compensation Cap Cm1 Trim Value
bits : 0 - 3 (4 bit)
access : read-write

CM2 : Compensation Cap Cm2 Trim Value
bits : 5 - 8 (4 bit)
access : read-write

CM3 : Compensation Cap Cm3 Trim Value
bits : 10 - 11 (2 bit)
access : read-write

GM : Gm Trim Value
bits : 13 - 15 (3 bit)
access : read-write

GM3 : Gm3 Trim Value
bits : 17 - 18 (2 bit)
access : read-write

OFFSETP : OPAx Non-Inverting Input Offset Configuration Value
bits : 20 - 24 (5 bit)
access : read-write

OFFSETN : OPAx Inverting Input Offset Configuration Value
bits : 26 - 30 (5 bit)
access : read-write


CH1CTRL

Channel 1 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1CTRL CH1CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONVMODE TRIGMODE PRSASYNC PRSSEL

CONVMODE : Conversion Mode
bits : 0 - 0 (1 bit)
access : read-write

TRIGMODE : Channel 1 Trigger Mode
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x00000000 : SW

Channel 1 is triggered by CH1DATA or COMBDATA write

0x00000001 : PRS

Channel 1 is triggered by PRS input

0x00000002 : REFRESH

Channel 1 is triggered by Refresh timer

0x00000003 : SWPRS

Channel 1 is triggered by CH1DATA/COMBDATA write or PRS input

0x00000004 : SWREFRESH

Channel 1 is triggered by CH1DATA/COMBDATA write or Refresh timer

0x00000005 : LESENSE

Channel 1 is triggered by LESENSE

End of enumeration elements list.

PRSASYNC : Channel 1 PRS Asynchronous Enable
bits : 8 - 8 (1 bit)
access : read-write

PRSSEL : Channel 1 PRS Trigger Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 triggers a conversion.

0x00000001 : PRSCH1

PRS ch 1 triggers a conversion.

0x00000002 : PRSCH2

PRS ch 2 triggers a conversion.

0x00000003 : PRSCH3

PRS ch 3 triggers a conversion.

0x00000004 : PRSCH4

PRS ch 4 triggers a conversion.

0x00000005 : PRSCH5

PRS ch 5 triggers a conversion.

0x00000006 : PRSCH6

PRS ch 6 triggers a conversion.

0x00000007 : PRSCH7

PRS ch 7 triggers a conversion.

End of enumeration elements list.


OPA1_APORTREQ

Operational Amplifier APORT Request Status Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA1_APORTREQ OPA1_APORTREQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XREQ APORT1YREQ APORT2XREQ APORT2YREQ APORT3XREQ APORT3YREQ APORT4XREQ APORT4YREQ

APORT1XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 2 - 2 (1 bit)
access : read-only

APORT1YREQ : 1 If the Bus Connected to APORT1X is Requested
bits : 3 - 3 (1 bit)
access : read-only

APORT2XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 4 - 4 (1 bit)
access : read-only

APORT2YREQ : 1 If the Bus Connected to APORT2Y is Requested
bits : 5 - 5 (1 bit)
access : read-only

APORT3XREQ : 1 If the Bus Connected to APORT3X is Requested
bits : 6 - 6 (1 bit)
access : read-only

APORT3YREQ : 1 If the Bus Connected to APORT3Y is Requested
bits : 7 - 7 (1 bit)
access : read-only

APORT4XREQ : 1 If the Bus Connected to APORT4X is Requested
bits : 8 - 8 (1 bit)
access : read-only

APORT4YREQ : 1 If the Bus Connected to APORT4Y is Requested
bits : 9 - 9 (1 bit)
access : read-only


OPA1_APORTCONFLICT

Operational Amplifier APORT Conflict Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA1_APORTCONFLICT OPA1_APORTCONFLICT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XCONFLICT APORT1YCONFLICT APORT2XCONFLICT APORT2YCONFLICT APORT3XCONFLICT APORT3YCONFLICT APORT4XCONFLICT APORT4YCONFLICT

APORT1XCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 2 - 2 (1 bit)
access : read-only

APORT1YCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 3 - 3 (1 bit)
access : read-only

APORT2XCONFLICT : 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral
bits : 4 - 4 (1 bit)
access : read-only

APORT2YCONFLICT : 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral
bits : 5 - 5 (1 bit)
access : read-only

APORT3XCONFLICT : 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral
bits : 6 - 6 (1 bit)
access : read-only

APORT3YCONFLICT : 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral
bits : 7 - 7 (1 bit)
access : read-only

APORT4XCONFLICT : 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral
bits : 8 - 8 (1 bit)
access : read-only

APORT4YCONFLICT : 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral
bits : 9 - 9 (1 bit)
access : read-only


OPA1_CTRL

Operational Amplifier Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA1_CTRL OPA1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRIVESTRENGTH INCBW HCMDIS OUTSCALE PRSEN PRSMODE PRSSEL PRSOUTMODE APORTXMASTERDIS APORTYMASTERDIS

DRIVESTRENGTH : OPAx Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : 0

Lower accuracy with Low drive strength.

0x00000001 : 1

Low accuracy with Low drive strength.

0x00000002 : 2

High accuracy with High drive strength.

0x00000003 : 3

Higher accuracy with High drive strength.

End of enumeration elements list.

INCBW : OPAx Unity Gain Bandwidth Scale
bits : 2 - 2 (1 bit)
access : read-write

HCMDIS : High Common Mode Disable
bits : 3 - 3 (1 bit)
access : read-write

OUTSCALE : Scale OPAx Output Driving Strength
bits : 4 - 4 (1 bit)
access : read-write

PRSEN : OPAx PRS Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write

PRSMODE : OPAx PRS Trigger Mode
bits : 9 - 9 (1 bit)
access : read-write

PRSSEL : OPAx PRS Trigger Select
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 triggers OPA.

0x00000001 : PRSCH1

PRS ch 1 triggers OPA.

0x00000002 : PRSCH2

PRS ch 2 triggers OPA.

0x00000003 : PRSCH3

PRS ch 3 triggers OPA.

0x00000004 : PRSCH4

PRS ch 4 triggers OPA.

0x00000005 : PRSCH5

PRS ch 5 triggers OPA.

0x00000006 : PRSCH6

PRS ch 6 triggers OPA.

0x00000007 : PRSCH7

PRS ch 7 triggers OPA.

End of enumeration elements list.

PRSOUTMODE : OPAx PRS Output Select
bits : 16 - 16 (1 bit)
access : read-write

APORTXMASTERDIS : APORT Bus Master Disable
bits : 20 - 20 (1 bit)
access : read-write

APORTYMASTERDIS : APORT Bus Master Disable
bits : 21 - 21 (1 bit)
access : read-write


OPA1_TIMER

Operational Amplifier Timer Control Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA1_TIMER OPA1_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTUPDLY WARMUPTIME SETTLETIME

STARTUPDLY : OPAx Startup Delay Count Value
bits : 0 - 5 (6 bit)
access : read-write

WARMUPTIME : OPAx Warmup Time Count Value
bits : 8 - 14 (7 bit)
access : read-write

SETTLETIME : OPAx Output Settling Timeout Value
bits : 16 - 25 (10 bit)
access : read-write


OPA1_MUX

Operational Amplifier Mux Configuration Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA1_MUX OPA1_MUX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSSEL NEGSEL RESINMUX GAIN3X RESSEL

POSSEL : OPAx Non-inverting Input Mux
bits : 0 - 7 (8 bit)
access : read-write

NEGSEL : OPAx Inverting Input Mux
bits : 8 - 15 (8 bit)
access : read-write

RESINMUX : OPAx Resistor Ladder Input Mux
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Set for Unity Gain

0x00000001 : OPANEXT

Set for NEXTOUT(x-1) input

0x00000002 : NEGPAD

NEG pad connected

0x00000003 : POSPAD

POS pad connected

0x00000004 : COMPAD

Neg pad of OPA0 connected. Direct input to support common reference.

0x00000005 : CENTER

OPA0 and OPA1 Resmux connected to form fully differential instrumentation amplifier.

0x00000006 : VSS

VSS connected

End of enumeration elements list.

GAIN3X : OPAx Dedicated 3x Gain Resistor Ladder
bits : 20 - 20 (1 bit)
access : read-write

RESSEL : OPAx Resistor Ladder Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : RES0

Gain of 1/3

0x00000001 : RES1

Gain of 1

0x00000002 : RES2

Gain of 1 2/3

0x00000003 : RES3

Gain of 2 1/5

0x00000004 : RES4

Gain of 3

0x00000005 : RES5

Gain of 4 1/3

0x00000006 : RES6

Gain of 7

0x00000007 : RES7

Gain of 15

End of enumeration elements list.


OPA1_OUT

Operational Amplifier Output Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA1_OUT OPA1_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAINOUTEN ALTOUTEN APORTOUTEN SHORT ALTOUTPADEN APORTOUTSEL

MAINOUTEN : OPAx Main Output Enable
bits : 0 - 0 (1 bit)
access : read-write

ALTOUTEN : OPAx Alternative Output Enable
bits : 1 - 1 (1 bit)
access : read-write

APORTOUTEN : OPAx Aport Output Enable
bits : 2 - 2 (1 bit)
access : read-write

SHORT : OPAx Main and Alternative Output Short
bits : 3 - 3 (1 bit)
access : read-write

ALTOUTPADEN : OPAx Output Enable Value
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0x00000001 : OUT0

Alternate Output 0

0x00000002 : OUT1

Alternate Output 1

0x00000004 : OUT2

Alternate Output 2

0x00000008 : OUT3

Alternate Output 3

0x00000010 : OUT4

Alternate Output 4

End of enumeration elements list.

APORTOUTSEL : OPAx APORT Output
bits : 16 - 23 (8 bit)
access : read-write


OPA1_CAL

Operational Amplifier Calibration Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA1_CAL OPA1_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM1 CM2 CM3 GM GM3 OFFSETP OFFSETN

CM1 : Compensation Cap Cm1 Trim Value
bits : 0 - 3 (4 bit)
access : read-write

CM2 : Compensation Cap Cm2 Trim Value
bits : 5 - 8 (4 bit)
access : read-write

CM3 : Compensation Cap Cm3 Trim Value
bits : 10 - 11 (2 bit)
access : read-write

GM : Gm Trim Value
bits : 13 - 15 (3 bit)
access : read-write

GM3 : Gm3 Trim Value
bits : 17 - 18 (2 bit)
access : read-write

OFFSETP : OPAx Non-Inverting Input Offset Configuration Value
bits : 20 - 24 (5 bit)
access : read-write

OFFSETN : OPAx Inverting Input Offset Configuration Value
bits : 26 - 30 (5 bit)
access : read-write


OPA2_APORTREQ

Operational Amplifier APORT Request Status Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA2_APORTREQ OPA2_APORTREQ read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XREQ APORT1YREQ APORT2XREQ APORT2YREQ APORT3XREQ APORT3YREQ APORT4XREQ APORT4YREQ

APORT1XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 2 - 2 (1 bit)
access : read-only

APORT1YREQ : 1 If the Bus Connected to APORT1X is Requested
bits : 3 - 3 (1 bit)
access : read-only

APORT2XREQ : 1 If the Bus Connected to APORT2X is Requested
bits : 4 - 4 (1 bit)
access : read-only

APORT2YREQ : 1 If the Bus Connected to APORT2Y is Requested
bits : 5 - 5 (1 bit)
access : read-only

APORT3XREQ : 1 If the Bus Connected to APORT3X is Requested
bits : 6 - 6 (1 bit)
access : read-only

APORT3YREQ : 1 If the Bus Connected to APORT3Y is Requested
bits : 7 - 7 (1 bit)
access : read-only

APORT4XREQ : 1 If the Bus Connected to APORT4X is Requested
bits : 8 - 8 (1 bit)
access : read-only

APORT4YREQ : 1 If the Bus Connected to APORT4Y is Requested
bits : 9 - 9 (1 bit)
access : read-only


OPA2_APORTCONFLICT

Operational Amplifier APORT Conflict Status Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA2_APORTCONFLICT OPA2_APORTCONFLICT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APORT1XCONFLICT APORT1YCONFLICT APORT2XCONFLICT APORT2YCONFLICT APORT3XCONFLICT APORT3YCONFLICT APORT4XCONFLICT APORT4YCONFLICT

APORT1XCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 2 - 2 (1 bit)
access : read-only

APORT1YCONFLICT : 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral
bits : 3 - 3 (1 bit)
access : read-only

APORT2XCONFLICT : 1 If the Bus Connected to APORT2X is in Conflict With Another Peripheral
bits : 4 - 4 (1 bit)
access : read-only

APORT2YCONFLICT : 1 If the Bus Connected to APORT2Y is in Conflict With Another Peripheral
bits : 5 - 5 (1 bit)
access : read-only

APORT3XCONFLICT : 1 If the Bus Connected to APORT3X is in Conflict With Another Peripheral
bits : 6 - 6 (1 bit)
access : read-only

APORT3YCONFLICT : 1 If the Bus Connected to APORT3Y is in Conflict With Another Peripheral
bits : 7 - 7 (1 bit)
access : read-only

APORT4XCONFLICT : 1 If the Bus Connected to APORT4X is in Conflict With Another Peripheral
bits : 8 - 8 (1 bit)
access : read-only

APORT4YCONFLICT : 1 If the Bus Connected to APORT4Y is in Conflict With Another Peripheral
bits : 9 - 9 (1 bit)
access : read-only


OPA2_CTRL

Operational Amplifier Control Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA2_CTRL OPA2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRIVESTRENGTH INCBW HCMDIS OUTSCALE PRSEN PRSMODE PRSSEL PRSOUTMODE APORTXMASTERDIS APORTYMASTERDIS

DRIVESTRENGTH : OPAx Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : 0

Lower accuracy with Low drive strength.

0x00000001 : 1

Low accuracy with Low drive strength.

0x00000002 : 2

High accuracy with High drive strength.

0x00000003 : 3

Higher accuracy with High drive strength.

End of enumeration elements list.

INCBW : OPAx Unity Gain Bandwidth Scale
bits : 2 - 2 (1 bit)
access : read-write

HCMDIS : High Common Mode Disable
bits : 3 - 3 (1 bit)
access : read-write

OUTSCALE : Scale OPAx Output Driving Strength
bits : 4 - 4 (1 bit)
access : read-write

PRSEN : OPAx PRS Trigger Enable
bits : 8 - 8 (1 bit)
access : read-write

PRSMODE : OPAx PRS Trigger Mode
bits : 9 - 9 (1 bit)
access : read-write

PRSSEL : OPAx PRS Trigger Select
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS ch 0 triggers OPA.

0x00000001 : PRSCH1

PRS ch 1 triggers OPA.

0x00000002 : PRSCH2

PRS ch 2 triggers OPA.

0x00000003 : PRSCH3

PRS ch 3 triggers OPA.

0x00000004 : PRSCH4

PRS ch 4 triggers OPA.

0x00000005 : PRSCH5

PRS ch 5 triggers OPA.

0x00000006 : PRSCH6

PRS ch 6 triggers OPA.

0x00000007 : PRSCH7

PRS ch 7 triggers OPA.

End of enumeration elements list.

PRSOUTMODE : OPAx PRS Output Select
bits : 16 - 16 (1 bit)
access : read-write

APORTXMASTERDIS : APORT Bus Master Disable
bits : 20 - 20 (1 bit)
access : read-write

APORTYMASTERDIS : APORT Bus Master Disable
bits : 21 - 21 (1 bit)
access : read-write


OPA2_TIMER

Operational Amplifier Timer Control Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA2_TIMER OPA2_TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTUPDLY WARMUPTIME SETTLETIME

STARTUPDLY : OPAx Startup Delay Count Value
bits : 0 - 5 (6 bit)
access : read-write

WARMUPTIME : OPAx Warmup Time Count Value
bits : 8 - 14 (7 bit)
access : read-write

SETTLETIME : OPAx Output Settling Timeout Value
bits : 16 - 25 (10 bit)
access : read-write


OPA2_MUX

Operational Amplifier Mux Configuration Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA2_MUX OPA2_MUX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSSEL NEGSEL RESINMUX GAIN3X RESSEL

POSSEL : OPAx Non-inverting Input Mux
bits : 0 - 7 (8 bit)
access : read-write

NEGSEL : OPAx Inverting Input Mux
bits : 8 - 15 (8 bit)
access : read-write

RESINMUX : OPAx Resistor Ladder Input Mux
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Set for Unity Gain

0x00000001 : OPANEXT

Set for NEXTOUT(x-1) input

0x00000002 : NEGPAD

NEG pad connected

0x00000003 : POSPAD

POS pad connected

0x00000004 : COMPAD

Neg pad of OPA0 connected. Direct input to support common reference.

0x00000005 : CENTER

OPA0 and OPA1 Resmux connected to form fully differential instrumentation amplifier.

0x00000006 : VSS

VSS connected

End of enumeration elements list.

GAIN3X : OPAx Dedicated 3x Gain Resistor Ladder
bits : 20 - 20 (1 bit)
access : read-write

RESSEL : OPAx Resistor Ladder Select
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0x00000000 : RES0

Gain of 1/3

0x00000001 : RES1

Gain of 1

0x00000002 : RES2

Gain of 1 2/3

0x00000003 : RES3

Gain of 2 1/5

0x00000004 : RES4

Gain of 3

0x00000005 : RES5

Gain of 4 1/3

0x00000006 : RES6

Gain of 7

0x00000007 : RES7

Gain of 15

End of enumeration elements list.


OPA2_OUT

Operational Amplifier Output Configuration Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA2_OUT OPA2_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAINOUTEN ALTOUTEN APORTOUTEN SHORT ALTOUTPADEN APORTOUTSEL

MAINOUTEN : OPAx Main Output Enable
bits : 0 - 0 (1 bit)
access : read-write

ALTOUTEN : OPAx Alternative Output Enable
bits : 1 - 1 (1 bit)
access : read-write

APORTOUTEN : OPAx Aport Output Enable
bits : 2 - 2 (1 bit)
access : read-write

SHORT : OPAx Main and Alternative Output Short
bits : 3 - 3 (1 bit)
access : read-write

ALTOUTPADEN : OPAx Output Enable Value
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

0x00000001 : OUT0

Alternate Output 0

0x00000002 : OUT1

Alternate Output 1

0x00000004 : OUT2

Alternate Output 2

0x00000008 : OUT3

Alternate Output 3

0x00000010 : OUT4

Alternate Output 4

End of enumeration elements list.

APORTOUTSEL : OPAx APORT Output
bits : 16 - 23 (8 bit)
access : read-write


OPA2_CAL

Operational Amplifier Calibration Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA2_CAL OPA2_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CM1 CM2 CM3 GM GM3 OFFSETP OFFSETN

CM1 : Compensation Cap Cm1 Trim Value
bits : 0 - 3 (4 bit)
access : read-write

CM2 : Compensation Cap Cm2 Trim Value
bits : 5 - 8 (4 bit)
access : read-write

CM3 : Compensation Cap Cm3 Trim Value
bits : 10 - 11 (2 bit)
access : read-write

GM : Gm Trim Value
bits : 13 - 15 (3 bit)
access : read-write

GM3 : Gm3 Trim Value
bits : 17 - 18 (2 bit)
access : read-write

OFFSETP : OPAx Non-Inverting Input Offset Configuration Value
bits : 20 - 24 (5 bit)
access : read-write

OFFSETN : OPAx Inverting Input Offset Configuration Value
bits : 26 - 30 (5 bit)
access : read-write



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