\n

RTCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TIME

RET0_REG

RET1_REG

RET2_REG

RET3_REG

RET4_REG

RET5_REG

RET6_REG

RET7_REG

RET8_REG

RET9_REG

RET10_REG

RET11_REG

RET12_REG

RET13_REG

RET14_REG

DATE

RET15_REG

RET16_REG

RET17_REG

RET18_REG

RET19_REG

RET20_REG

RET21_REG

RET22_REG

RET23_REG

RET24_REG

RET25_REG

RET26_REG

RET27_REG

RET28_REG

RET29_REG

RET30_REG

IF

RET31_REG

IFS

IFC

IEN

STATUS

CMD

SYNCBUSY

POWERDOWN

LOCK

EM4WUEN

PRECNT

CC0_CTRL

CC0_CCV

CC0_TIME

CC0_DATE

CC1_CTRL

CC1_CCV

CC1_TIME

CC1_DATE

CC2_CTRL

CC2_CCV

CC2_TIME

CC2_DATE

CNT

COMBCNT


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE DEBUGRUN PRECCV0TOP CCV1TOP CNTPRESC CNTTICK BUMODETSEN OSCFDETEN CNTMODE LYEARCORRDIS

ENABLE : RTCC Enable
bits : 0 - 0 (1 bit)
access : read-write

DEBUGRUN : Debug Mode Run Enable
bits : 2 - 2 (1 bit)
access : read-write

PRECCV0TOP : Pre-counter CCV0 Top Value Enable
bits : 4 - 4 (1 bit)
access : read-write

CCV1TOP : CCV1 Top Value Enable
bits : 5 - 5 (1 bit)
access : read-write

CNTPRESC : Counter Prescaler Value
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

CLKCNT = LFECLKRTCC/1

0x00000001 : DIV2

CLKCNT = LFECLKRTCC/2

0x00000002 : DIV4

CLKCNT = LFECLKRTCC/4

0x00000003 : DIV8

CLKCNT = LFECLKRTCC/8

0x00000004 : DIV16

CLKCNT = LFECLKRTCC/16

0x00000005 : DIV32

CLKCNT = LFECLKRTCC/32

0x00000006 : DIV64

CLKCNT = LFECLKRTCC/64

0x00000007 : DIV128

CLKCNT = LFECLKRTCC/128

0x00000008 : DIV256

CLKCNT = LFECLKRTCC/256

0x00000009 : DIV512

CLKCNT = LFECLKRTCC/512

0x0000000A : DIV1024

CLKCNT = LFECLKRTCC/1024

0x0000000B : DIV2048

CLKCNT = LFECLKRTCC/2048

0x0000000C : DIV4096

CLKCNT = LFECLKRTCC/4096

0x0000000D : DIV8192

CLKCNT = LFECLKRTCC/8192

0x0000000E : DIV16384

CLKCNT = LFECLKRTCC/16384

0x0000000F : DIV32768

CLKCNT = LFECLKRTCC/32768

End of enumeration elements list.

CNTTICK : Counter Prescaler Mode
bits : 12 - 12 (1 bit)
access : read-write

BUMODETSEN : Backup Mode Timestamp Enable
bits : 14 - 14 (1 bit)
access : read-write

OSCFDETEN : Oscillator Failure Detection Enable
bits : 15 - 15 (1 bit)
access : read-write

CNTMODE : Main Counter Mode
bits : 16 - 16 (1 bit)
access : read-write

LYEARCORRDIS : Leap Year Correction Disabled
bits : 17 - 17 (1 bit)
access : read-write


TIME

Time of Day Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIME TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECU SECT MINU MINT HOURU HOURT

SECU : Seconds, Units
bits : 0 - 3 (4 bit)
access : read-write

SECT : Seconds, Tens
bits : 4 - 6 (3 bit)
access : read-write

MINU : Minutes, Units
bits : 8 - 11 (4 bit)
access : read-write

MINT : Minutes, Tens
bits : 12 - 14 (3 bit)
access : read-write

HOURU : Hours, Units
bits : 16 - 19 (4 bit)
access : read-write

HOURT : Hours, Tens
bits : 20 - 21 (2 bit)
access : read-write


RET0_REG

Retention Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET0_REG RET0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET1_REG

Retention Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET1_REG RET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET2_REG

Retention Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET2_REG RET2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET3_REG

Retention Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET3_REG RET3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET4_REG

Retention Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET4_REG RET4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET5_REG

Retention Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET5_REG RET5_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET6_REG

Retention Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET6_REG RET6_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET7_REG

Retention Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET7_REG RET7_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET8_REG

Retention Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET8_REG RET8_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET9_REG

Retention Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET9_REG RET9_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET10_REG

Retention Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET10_REG RET10_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET11_REG

Retention Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET11_REG RET11_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET12_REG

Retention Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET12_REG RET12_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET13_REG

Retention Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET13_REG RET13_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET14_REG

Retention Register
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET14_REG RET14_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


DATE

Date Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYOMU DAYOMT MONTHU MONTHT YEARU YEART DAYOW

DAYOMU : Day of Month, Units
bits : 0 - 3 (4 bit)
access : read-write

DAYOMT : Day of Month, Tens
bits : 4 - 5 (2 bit)
access : read-write

MONTHU : Month, Units
bits : 8 - 11 (4 bit)
access : read-write

MONTHT : Month, Tens
bits : 12 - 12 (1 bit)
access : read-write

YEARU : Year, Units
bits : 16 - 19 (4 bit)
access : read-write

YEART : Year, Tens
bits : 20 - 23 (4 bit)
access : read-write

DAYOW : Day of Week
bits : 24 - 26 (3 bit)
access : read-write


RET15_REG

Retention Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET15_REG RET15_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET16_REG

Retention Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET16_REG RET16_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET17_REG

Retention Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET17_REG RET17_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET18_REG

Retention Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET18_REG RET18_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET19_REG

Retention Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET19_REG RET19_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET20_REG

Retention Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET20_REG RET20_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET21_REG

Retention Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET21_REG RET21_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET22_REG

Retention Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET22_REG RET22_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET23_REG

Retention Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET23_REG RET23_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET24_REG

Retention Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET24_REG RET24_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET25_REG

Retention Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET25_REG RET25_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET26_REG

Retention Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET26_REG RET26_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET27_REG

Retention Register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET27_REG RET27_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET28_REG

Retention Register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET28_REG RET28_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET29_REG

Retention Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET29_REG RET29_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


RET30_REG

Retention Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET30_REG RET30_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


IF

RTCC Interrupt Flags
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF CC0 CC1 CC2 OSCFAIL CNTTICK MINTICK HOURTICK DAYTICK DAYOWOF MONTHTICK

OF : Overflow Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

CC0 : Channel 0 Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

CC1 : Channel 1 Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

CC2 : Channel 2 Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

OSCFAIL : Oscillator Failure Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

CNTTICK : Main Counter Tick
bits : 5 - 5 (1 bit)
access : read-only

MINTICK : Minute Tick
bits : 6 - 6 (1 bit)
access : read-only

HOURTICK : Hour Tick
bits : 7 - 7 (1 bit)
access : read-only

DAYTICK : Day Tick
bits : 8 - 8 (1 bit)
access : read-only

DAYOWOF : Day of Week Overflow
bits : 9 - 9 (1 bit)
access : read-only

MONTHTICK : Month Tick
bits : 10 - 10 (1 bit)
access : read-only


RET31_REG

Retention Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET31_REG RET31_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG

REG : General Purpose Retention Register
bits : 0 - 31 (32 bit)
access : read-write


IFS

Interrupt Flag Set Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF CC0 CC1 CC2 OSCFAIL CNTTICK MINTICK HOURTICK DAYTICK DAYOWOF MONTHTICK

OF : Set OF Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

CC0 : Set CC0 Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

CC1 : Set CC1 Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

CC2 : Set CC2 Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

OSCFAIL : Set OSCFAIL Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

CNTTICK : Set CNTTICK Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

MINTICK : Set MINTICK Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

HOURTICK : Set HOURTICK Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

DAYTICK : Set DAYTICK Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

DAYOWOF : Set DAYOWOF Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

MONTHTICK : Set MONTHTICK Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF CC0 CC1 CC2 OSCFAIL CNTTICK MINTICK HOURTICK DAYTICK DAYOWOF MONTHTICK

OF : Clear OF Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

CC0 : Clear CC0 Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

CC1 : Clear CC1 Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

CC2 : Clear CC2 Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

OSCFAIL : Clear OSCFAIL Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

CNTTICK : Clear CNTTICK Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

MINTICK : Clear MINTICK Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

HOURTICK : Clear HOURTICK Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

DAYTICK : Clear DAYTICK Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

DAYOWOF : Clear DAYOWOF Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

MONTHTICK : Clear MONTHTICK Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF CC0 CC1 CC2 OSCFAIL CNTTICK MINTICK HOURTICK DAYTICK DAYOWOF MONTHTICK

OF : OF Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

CC0 : CC0 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

CC1 : CC1 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

CC2 : CC2 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

OSCFAIL : OSCFAIL Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

CNTTICK : CNTTICK Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

MINTICK : MINTICK Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

HOURTICK : HOURTICK Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

DAYTICK : DAYTICK Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

DAYOWOF : DAYOWOF Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

MONTHTICK : MONTHTICK Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write


STATUS

Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUMODETS

BUMODETS : Timestamp for Backup Mode Entry Stored
bits : 0 - 0 (1 bit)
access : read-only


CMD

Command Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRSTATUS

CLRSTATUS : Clear RTCC_STATUS Register
bits : 0 - 0 (1 bit)
access : write-only


SYNCBUSY

Synchronization Busy Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : CMD Register Busy
bits : 5 - 5 (1 bit)
access : read-only


POWERDOWN

Retention RAM Power-down Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWERDOWN POWERDOWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM

RAM : Retention RAM Power-down
bits : 0 - 0 (1 bit)
access : read-write


LOCK

Configuration Lock Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


EM4WUEN

Wake Up Enable
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM4WUEN EM4WUEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4WU

EM4WU : EM4 Wake-up Enable
bits : 0 - 0 (1 bit)
access : read-write


PRECNT

Pre-Counter Value Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRECNT PRECNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRECNT

PRECNT : Pre-Counter Value
bits : 0 - 14 (15 bit)
access : read-write


CC0_CTRL

CC Channel Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_CTRL CC0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CMOA ICEDGE PRSSEL COMPBASE COMPMASK DAYCC

MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Compare/Capture channel turned off

0x00000001 : INPUTCAPTURE

Input capture

0x00000002 : OUTPUTCOMPARE

Output compare

End of enumeration elements list.

CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x00000000 : PULSE

A single clock cycle pulse is generated on output

0x00000001 : TOGGLE

Toggle output on compare match

0x00000002 : CLEAR

Clear output on compare match

0x00000003 : SET

Set output on compare match

End of enumeration elements list.

ICEDGE : Input Capture Edge Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : RISING

Rising edges detected

0x00000001 : FALLING

Falling edges detected

0x00000002 : BOTH

Both edges detected

0x00000003 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.

PRSSEL : Compare/Capture Channel PRS Input Channel Selection
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

End of enumeration elements list.

COMPBASE : Capture Compare Channel Comparison Base
bits : 11 - 11 (1 bit)
access : read-write

COMPMASK : Capture Compare Channel Comparison Mask
bits : 12 - 16 (5 bit)
access : read-write

DAYCC : Day Capture/Compare Selection
bits : 17 - 17 (1 bit)
access : read-write


CC0_CCV

Capture/Compare Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_CCV CC0_CCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Capture/Compare Value
bits : 0 - 31 (32 bit)
access : read-write


CC0_TIME

Capture/Compare Time Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_TIME CC0_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECU SECT MINU MINT HOURU HOURT

SECU : Seconds, Units
bits : 0 - 3 (4 bit)
access : read-write

SECT : Seconds, Tens
bits : 4 - 6 (3 bit)
access : read-write

MINU : Minutes, Units
bits : 8 - 11 (4 bit)
access : read-write

MINT : Minutes, Tens
bits : 12 - 14 (3 bit)
access : read-write

HOURU : Hours, Units
bits : 16 - 19 (4 bit)
access : read-write

HOURT : Hours, Tens
bits : 20 - 21 (2 bit)
access : read-write


CC0_DATE

Capture/Compare Date Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC0_DATE CC0_DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYU DAYT MONTHU MONTHT

DAYU : Day of Month/week, Units
bits : 0 - 3 (4 bit)
access : read-write

DAYT : Day of Month/week, Tens
bits : 4 - 5 (2 bit)
access : read-write

MONTHU : Month, Units
bits : 8 - 11 (4 bit)
access : read-write

MONTHT : Month, Tens
bits : 12 - 12 (1 bit)
access : read-write


CC1_CTRL

CC Channel Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_CTRL CC1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CMOA ICEDGE PRSSEL COMPBASE COMPMASK DAYCC

MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Compare/Capture channel turned off

0x00000001 : INPUTCAPTURE

Input capture

0x00000002 : OUTPUTCOMPARE

Output compare

End of enumeration elements list.

CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x00000000 : PULSE

A single clock cycle pulse is generated on output

0x00000001 : TOGGLE

Toggle output on compare match

0x00000002 : CLEAR

Clear output on compare match

0x00000003 : SET

Set output on compare match

End of enumeration elements list.

ICEDGE : Input Capture Edge Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : RISING

Rising edges detected

0x00000001 : FALLING

Falling edges detected

0x00000002 : BOTH

Both edges detected

0x00000003 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.

PRSSEL : Compare/Capture Channel PRS Input Channel Selection
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

End of enumeration elements list.

COMPBASE : Capture Compare Channel Comparison Base
bits : 11 - 11 (1 bit)
access : read-write

COMPMASK : Capture Compare Channel Comparison Mask
bits : 12 - 16 (5 bit)
access : read-write

DAYCC : Day Capture/Compare Selection
bits : 17 - 17 (1 bit)
access : read-write


CC1_CCV

Capture/Compare Value Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_CCV CC1_CCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Capture/Compare Value
bits : 0 - 31 (32 bit)
access : read-write


CC1_TIME

Capture/Compare Time Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_TIME CC1_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECU SECT MINU MINT HOURU HOURT

SECU : Seconds, Units
bits : 0 - 3 (4 bit)
access : read-write

SECT : Seconds, Tens
bits : 4 - 6 (3 bit)
access : read-write

MINU : Minutes, Units
bits : 8 - 11 (4 bit)
access : read-write

MINT : Minutes, Tens
bits : 12 - 14 (3 bit)
access : read-write

HOURU : Hours, Units
bits : 16 - 19 (4 bit)
access : read-write

HOURT : Hours, Tens
bits : 20 - 21 (2 bit)
access : read-write


CC1_DATE

Capture/Compare Date Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC1_DATE CC1_DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYU DAYT MONTHU MONTHT

DAYU : Day of Month/week, Units
bits : 0 - 3 (4 bit)
access : read-write

DAYT : Day of Month/week, Tens
bits : 4 - 5 (2 bit)
access : read-write

MONTHU : Month, Units
bits : 8 - 11 (4 bit)
access : read-write

MONTHT : Month, Tens
bits : 12 - 12 (1 bit)
access : read-write


CC2_CTRL

CC Channel Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_CTRL CC2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CMOA ICEDGE PRSSEL COMPBASE COMPMASK DAYCC

MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Compare/Capture channel turned off

0x00000001 : INPUTCAPTURE

Input capture

0x00000002 : OUTPUTCOMPARE

Output compare

End of enumeration elements list.

CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x00000000 : PULSE

A single clock cycle pulse is generated on output

0x00000001 : TOGGLE

Toggle output on compare match

0x00000002 : CLEAR

Clear output on compare match

0x00000003 : SET

Set output on compare match

End of enumeration elements list.

ICEDGE : Input Capture Edge Select
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : RISING

Rising edges detected

0x00000001 : FALLING

Falling edges detected

0x00000002 : BOTH

Both edges detected

0x00000003 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.

PRSSEL : Compare/Capture Channel PRS Input Channel Selection
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

0x00000006 : PRSCH6

PRS Channel 6 selected as input

0x00000007 : PRSCH7

PRS Channel 7 selected as input

End of enumeration elements list.

COMPBASE : Capture Compare Channel Comparison Base
bits : 11 - 11 (1 bit)
access : read-write

COMPMASK : Capture Compare Channel Comparison Mask
bits : 12 - 16 (5 bit)
access : read-write

DAYCC : Day Capture/Compare Selection
bits : 17 - 17 (1 bit)
access : read-write


CC2_CCV

Capture/Compare Value Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_CCV CC2_CCV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : Capture/Compare Value
bits : 0 - 31 (32 bit)
access : read-write


CC2_TIME

Capture/Compare Time Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_TIME CC2_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECU SECT MINU MINT HOURU HOURT

SECU : Seconds, Units
bits : 0 - 3 (4 bit)
access : read-write

SECT : Seconds, Tens
bits : 4 - 6 (3 bit)
access : read-write

MINU : Minutes, Units
bits : 8 - 11 (4 bit)
access : read-write

MINT : Minutes, Tens
bits : 12 - 14 (3 bit)
access : read-write

HOURU : Hours, Units
bits : 16 - 19 (4 bit)
access : read-write

HOURT : Hours, Tens
bits : 20 - 21 (2 bit)
access : read-write


CC2_DATE

Capture/Compare Date Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CC2_DATE CC2_DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAYU DAYT MONTHU MONTHT

DAYU : Day of Month/week, Units
bits : 0 - 3 (4 bit)
access : read-write

DAYT : Day of Month/week, Tens
bits : 4 - 5 (2 bit)
access : read-write

MONTHU : Month, Units
bits : 8 - 11 (4 bit)
access : read-write

MONTHT : Month, Tens
bits : 12 - 12 (1 bit)
access : read-write


CNT

Counter Value Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value
bits : 0 - 31 (32 bit)
access : read-write


COMBCNT

Combined Pre-Counter and Counter Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COMBCNT COMBCNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRECNT CNTLSB

PRECNT : Pre-Counter Value
bits : 0 - 14 (15 bit)
access : read-only

CNTLSB : Counter Value
bits : 15 - 31 (17 bit)
access : read-only



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