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MSC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

ADDRB

WDATA

STATUS

IF

IFS

IFC

IEN

LOCK

READCTRL

CMD

CACHEHITS

CACHEMISSES

TIMEBASE

MASSLOCK

WRITECTRL

WRITECMD


CTRL

Memory System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSFAULT

BUSFAULT : Bus Fault Response Enable
bits : 0 - 0 (1 bit)
access : read-write


ADDRB

Page Erase/Write Address Buffer
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDRB ADDRB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRB

ADDRB : Page Erase or Write Address Buffer
bits : 0 - 31 (32 bit)
access : read-write


WDATA

Write Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDATA WDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDATA

WDATA : Write Data
bits : 0 - 31 (32 bit)
access : read-write


STATUS

Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY LOCKED INVADDR WDATAREADY WORDTIMEOUT ERASEABORTED PCRUNNING

BUSY : Erase/Write Busy
bits : 0 - 0 (1 bit)
access : read-only

LOCKED : Access Locked
bits : 1 - 1 (1 bit)
access : read-only

INVADDR : Invalid Write Address or Erase Page
bits : 2 - 2 (1 bit)
access : read-only

WDATAREADY : WDATA Write Ready
bits : 3 - 3 (1 bit)
access : read-only

WORDTIMEOUT : Flash Write Word Timeout
bits : 4 - 4 (1 bit)
access : read-only

ERASEABORTED : The Current Flash Erase Operation Aborted
bits : 5 - 5 (1 bit)
access : read-only

PCRUNNING : Performance Counters Running
bits : 6 - 6 (1 bit)
access : read-only


IF

Interrupt Flag Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF

ERASE : Erase Done Interrupt Read Flag
bits : 0 - 0 (1 bit)
access : read-only

WRITE : Write Done Interrupt Read Flag
bits : 1 - 1 (1 bit)
access : read-only

CHOF : Cache Hits Overflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

CMOF : Cache Misses Overflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF

ERASE : Erase Done Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

WRITE : Write Done Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

CHOF : Cache Hits Overflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

CMOF : Cache Misses Overflow Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF

ERASE : Erase Done Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

WRITE : Write Done Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

CHOF : Cache Hits Overflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

CMOF : Cache Misses Overflow Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERASE WRITE CHOF CMOF

ERASE : Erase Done Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

WRITE : Write Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

CHOF : Cache Hits Overflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

CMOF : Cache Misses Overflow Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write


LOCK

Configuration Lock Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED


0x00000001 : LOCKED


End of enumeration elements list.


READCTRL

Read Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READCTRL READCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE IFCDIS AIDIS ICCDIS EBICDIS RAMCEN BUSSTRATEGY

MODE : Read Mode
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0x00000000 : WS0

Zero wait-states inserted in fetch or read transfers.

0x00000001 : WS1

One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz.

0x00000002 : WS0SCBTP

Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty.

0x00000003 : WS1SCBTP

One wait-state access with SCBTP enabled.

0x00000004 : WS2

Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz.

0x00000005 : WS2SCBTP

Two wait-state access with SCBTP enabled.

End of enumeration elements list.

IFCDIS : Internal Flash Cache Disable
bits : 3 - 3 (1 bit)
access : read-write

AIDIS : Automatic Invalidate Disable
bits : 4 - 4 (1 bit)
access : read-write

ICCDIS : Interrupt Context Cache Disable
bits : 5 - 5 (1 bit)
access : read-write

EBICDIS : External Bus Interface Cache Disable
bits : 6 - 6 (1 bit)
access : read-write

RAMCEN : RAM Cache Enable
bits : 7 - 7 (1 bit)
access : read-write

BUSSTRATEGY : Strategy for bus matrix
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0x00000000 : CPU


0x00000001 : DMA


0x00000002 : DMAEM1


0x00000003 : NONE


End of enumeration elements list.


CMD

Command Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INVCACHE STARTPC STOPPC

INVCACHE : Invalidate Instruction Cache
bits : 0 - 0 (1 bit)
access : write-only

STARTPC : Start Performance Counters
bits : 1 - 1 (1 bit)
access : write-only

STOPPC : Stop Performance Counters
bits : 2 - 2 (1 bit)
access : write-only


CACHEHITS

Cache Hits Performance Counter
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CACHEHITS CACHEHITS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHEHITS

CACHEHITS : Cache hits since last performance counter start command.
bits : 0 - 19 (20 bit)
access : read-only


CACHEMISSES

Cache Misses Performance Counter
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CACHEMISSES CACHEMISSES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHEMISSES

CACHEMISSES : Cache misses since last performance counter start command.
bits : 0 - 19 (20 bit)
access : read-only


TIMEBASE

Flash Write and Erase Timebase
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMEBASE TIMEBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE PERIOD

BASE : Timebase used by MSC to time flash writes and erases
bits : 0 - 5 (6 bit)
access : read-write

PERIOD : Sets the timebase period
bits : 16 - 16 (1 bit)
access : read-write


MASSLOCK

Mass Erase Lock Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASSLOCK MASSLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Mass Erase Lock
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

Mass erase unlocked.

0x00000001 : LOCKED

Mass erase locked.

End of enumeration elements list.


WRITECTRL

Write Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WRITECTRL WRITECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WREN IRQERASEABORT

WREN : Enable Write/Erase Controller
bits : 0 - 0 (1 bit)
access : read-write

IRQERASEABORT : Abort Page Erase on Interrupt
bits : 1 - 1 (1 bit)
access : read-write


WRITECMD

Write Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WRITECMD WRITECMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LADDRIM ERASEPAGE WRITEEND WRITEONCE WRITETRIG ERASEABORT ERASEMAIN0 CLEARWDATA

LADDRIM : Load MSC_ADDRB into ADDR
bits : 0 - 0 (1 bit)
access : write-only

ERASEPAGE : Erase Page
bits : 1 - 1 (1 bit)
access : write-only

WRITEEND : End Write Mode
bits : 2 - 2 (1 bit)
access : write-only

WRITEONCE : Word Write-Once Trigger
bits : 3 - 3 (1 bit)
access : write-only

WRITETRIG : Word Write Sequence Trigger
bits : 4 - 4 (1 bit)
access : write-only

ERASEABORT : Abort erase sequence
bits : 5 - 5 (1 bit)
access : write-only

ERASEMAIN0 : Mass erase region 0
bits : 8 - 8 (1 bit)
access : write-only

CLEARWDATA : Clear WDATA state
bits : 12 - 12 (1 bit)
access : write-only



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