\n

PRS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SWPULSE

CH0_CTRL

CH1_CTRL

CH2_CTRL

CH3_CTRL

CH4_CTRL

CH5_CTRL

CH6_CTRL

CH7_CTRL

CH8_CTRL

CH9_CTRL

CH10_CTRL

CH11_CTRL

SWLEVEL

ROUTE


SWPULSE

Software Pulse Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPULSE SWPULSE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PULSE CH1PULSE CH2PULSE CH3PULSE CH4PULSE CH5PULSE CH6PULSE CH7PULSE CH8PULSE CH9PULSE CH10PULSE CH11PULSE

CH0PULSE : Channel 0 Pulse Generation
bits : 0 - 0 (1 bit)
access : write-only

CH1PULSE : Channel 1 Pulse Generation
bits : 1 - 1 (1 bit)
access : write-only

CH2PULSE : Channel 2 Pulse Generation
bits : 2 - 2 (1 bit)
access : write-only

CH3PULSE : Channel 3 Pulse Generation
bits : 3 - 3 (1 bit)
access : write-only

CH4PULSE : Channel 4 Pulse Generation
bits : 4 - 4 (1 bit)
access : write-only

CH5PULSE : Channel 5 Pulse Generation
bits : 5 - 5 (1 bit)
access : write-only

CH6PULSE : Channel 6 Pulse Generation
bits : 6 - 6 (1 bit)
access : write-only

CH7PULSE : Channel 7 Pulse Generation
bits : 7 - 7 (1 bit)
access : write-only

CH8PULSE : Channel 8 Pulse Generation
bits : 8 - 8 (1 bit)
access : write-only

CH9PULSE : Channel 9 Pulse Generation
bits : 9 - 9 (1 bit)
access : write-only

CH10PULSE : Channel 10 Pulse Generation
bits : 10 - 10 (1 bit)
access : write-only

CH11PULSE : Channel 11 Pulse Generation
bits : 11 - 11 (1 bit)
access : write-only


CH0_CTRL

Channel Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CTRL CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH1_CTRL

Channel Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CTRL CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH2_CTRL

Channel Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CTRL CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH3_CTRL

Channel Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CTRL CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH4_CTRL

Channel Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CTRL CH4_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH5_CTRL

Channel Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CTRL CH5_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH6_CTRL

Channel Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CTRL CH6_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH7_CTRL

Channel Control Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CTRL CH7_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH8_CTRL

Channel Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH8_CTRL CH8_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH9_CTRL

Channel Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH9_CTRL CH9_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH10_CTRL

Channel Control Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH10_CTRL CH10_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH11_CTRL

Channel Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH11_CTRL CH11_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000003 : ACMP1

Analog Comparator 1

0x00000006 : DAC0

Digital to Analog Converter 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000010 : USART0

Universal Synchronous/Asynchronous Receiver/Transmitter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x00000012 : USART2

Universal Synchronous/Asynchronous Receiver/Transmitter 2

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x0000001E : TIMER2

Timer 2

0x0000001F : TIMER3

Timer 3

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000034 : LETIMER0

Low Energy Timer 0

0x00000037 : BURTC

Backup RTC

0x00000039 : LESENSEL

Low Energy Sensor Interface

0x0000003A : LESENSEH

Low Energy Sensor Interface

0x0000003B : LESENSED

Low Energy Sensor Interface

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


SWLEVEL

Software Level Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWLEVEL SWLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0LEVEL CH1LEVEL CH2LEVEL CH3LEVEL CH4LEVEL CH5LEVEL CH6LEVEL CH7LEVEL CH8LEVEL CH9LEVEL CH10LEVEL CH11LEVEL

CH0LEVEL : Channel 0 Software Level
bits : 0 - 0 (1 bit)
access : read-write

CH1LEVEL : Channel 1 Software Level
bits : 1 - 1 (1 bit)
access : read-write

CH2LEVEL : Channel 2 Software Level
bits : 2 - 2 (1 bit)
access : read-write

CH3LEVEL : Channel 3 Software Level
bits : 3 - 3 (1 bit)
access : read-write

CH4LEVEL : Channel 4 Software Level
bits : 4 - 4 (1 bit)
access : read-write

CH5LEVEL : Channel 5 Software Level
bits : 5 - 5 (1 bit)
access : read-write

CH6LEVEL : Channel 6 Software Level
bits : 6 - 6 (1 bit)
access : read-write

CH7LEVEL : Channel 7 Software Level
bits : 7 - 7 (1 bit)
access : read-write

CH8LEVEL : Channel 8 Software Level
bits : 8 - 8 (1 bit)
access : read-write

CH9LEVEL : Channel 9 Software Level
bits : 9 - 9 (1 bit)
access : read-write

CH10LEVEL : Channel 10 Software Level
bits : 10 - 10 (1 bit)
access : read-write

CH11LEVEL : Channel 11 Software Level
bits : 11 - 11 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PEN CH1PEN CH2PEN CH3PEN LOCATION

CH0PEN : CH0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

CH1PEN : CH1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CH2PEN : CH2 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CH3PEN : CH3 Pin Enable
bits : 3 - 3 (1 bit)
access : read-write

LOCATION : I/O Location
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.