\n
address_offset : 0x0 Bytes (0x0)
size : 0x355 byte (0x0)
mem_usage : registers
protection : not protected
Interrupt Set-Enable Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : SETENA
bits : 0 - 31 (32 bit)
Interrupt Set-Pending Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : SETPEND
bits : 0 - 31 (32 bit)
Interrupt Set-Pending Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : SETPEND
bits : 0 - 31 (32 bit)
Interrupt Set-Pending Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : SETPEND
bits : 0 - 31 (32 bit)
Interrupt Clear-Pending Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)
Interrupt Clear-Pending Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)
Interrupt Clear-Pending Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : CLRPEND
bits : 0 - 31 (32 bit)
Interrupt Active Bit Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)
Interrupt Active Bit Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)
Interrupt Active Bit Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : ACTIVE
bits : 0 - 31 (32 bit)
Interrupt Priority Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Priority Register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IPR_N0 : IPR_N0
bits : 0 - 7 (8 bit)
IPR_N1 : IPR_N1
bits : 8 - 15 (8 bit)
IPR_N2 : IPR_N2
bits : 16 - 23 (8 bit)
IPR_N3 : IPR_N3
bits : 24 - 31 (8 bit)
Interrupt Set-Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : SETENA
bits : 0 - 31 (32 bit)
Interrupt Set-Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : SETENA
bits : 0 - 31 (32 bit)
Interrupt Clear-Enable Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : CLRENA
bits : 0 - 31 (32 bit)
Interrupt Clear-Enable Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : CLRENA
bits : 0 - 31 (32 bit)
Interrupt Clear-Enable Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : CLRENA
bits : 0 - 31 (32 bit)
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