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PRS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SWPULSE

CH0_CTRL

CH1_CTRL

CH2_CTRL

CH3_CTRL

SWLEVEL

ROUTE


SWPULSE

Software Pulse Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWPULSE SWPULSE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PULSE CH1PULSE CH2PULSE CH3PULSE

CH0PULSE : Channel 0 Pulse Generation
bits : 0 - 0 (1 bit)
access : write-only

CH1PULSE : Channel 1 Pulse Generation
bits : 1 - 1 (1 bit)
access : write-only

CH2PULSE : Channel 2 Pulse Generation
bits : 2 - 2 (1 bit)
access : write-only

CH3PULSE : Channel 3 Pulse Generation
bits : 3 - 3 (1 bit)
access : write-only


CH0_CTRL

Channel Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CTRL CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000036 : PCNT0

Pulse Counter 0

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH1_CTRL

Channel Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CTRL CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000036 : PCNT0

Pulse Counter 0

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH2_CTRL

Channel Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CTRL CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000036 : PCNT0

Pulse Counter 0

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


CH3_CTRL

Channel Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CTRL CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL EDSEL ASYNC

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0x00000000 : NONE

No source selected

0x00000001 : VCMP

Voltage Comparator

0x00000002 : ACMP0

Analog Comparator 0

0x00000008 : ADC0

Analog to Digital Converter 0

0x00000011 : USART1

Universal Synchronous/Asynchronous Receiver/Transmitter 1

0x0000001C : TIMER0

Timer 0

0x0000001D : TIMER1

Timer 1

0x00000028 : RTC

Real-Time Counter

0x00000030 : GPIOL

General purpose Input/Output

0x00000031 : GPIOH

General purpose Input/Output

0x00000036 : PCNT0

Pulse Counter 0

End of enumeration elements list.

EDSEL : Edge Detect Select
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Signal is left as it is

0x00000001 : POSEDGE

A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal

0x00000002 : NEGEDGE

A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal

0x00000003 : BOTHEDGES

A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal

End of enumeration elements list.

ASYNC : Asynchronous reflex
bits : 28 - 28 (1 bit)
access : read-write


SWLEVEL

Software Level Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWLEVEL SWLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0LEVEL CH1LEVEL CH2LEVEL CH3LEVEL

CH0LEVEL : Channel 0 Software Level
bits : 0 - 0 (1 bit)
access : read-write

CH1LEVEL : Channel 1 Software Level
bits : 1 - 1 (1 bit)
access : read-write

CH2LEVEL : Channel 2 Software Level
bits : 2 - 2 (1 bit)
access : read-write

CH3LEVEL : Channel 3 Software Level
bits : 3 - 3 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PEN CH1PEN CH2PEN CH3PEN LOCATION

CH0PEN : CH0 Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

CH1PEN : CH1 Pin Enable
bits : 1 - 1 (1 bit)
access : read-write

CH2PEN : CH2 Pin Enable
bits : 2 - 2 (1 bit)
access : read-write

CH3PEN : CH3 Pin Enable
bits : 3 - 3 (1 bit)
access : read-write

LOCATION : I/O Location
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

End of enumeration elements list.



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