\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXLENGTH : Max Frame Length Value
bits : 0 - 11 (12 bit)
access : read-write
INILENGTH : Initial Frame Length Value
bits : 12 - 15 (4 bit)
access : read-write
No Description
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x104 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x108 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x10C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x110 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x114 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x118 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x11C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x120 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x124 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x128 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x12C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x130 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x134 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x138 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x13C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENT : Interleaver element data
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Address Filter Enable
bits : 0 - 0 (1 bit)
access : read-write
BRDCST00EN : Broadcast Address 0x00 Enable
bits : 1 - 1 (1 bit)
access : read-write
BRDCSTFFEN : Broadcast Address 0xFF Enable
bits : 2 - 2 (1 bit)
access : read-write
ADDRESS : Address
bits : 8 - 15 (8 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATABUFFER : Frame Controller data buffer
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WCNT : Word Counter Value
bits : 0 - 11 (12 bit)
access : read-only
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMELENGTH : Word Counter Frame Length Value
bits : 0 - 11 (12 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENGTHFIELDLOC : Length field location
bits : 0 - 11 (12 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRFIELDLOC : Address field location
bits : 0 - 11 (12 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXABORT : RX Abort
bits : 0 - 0 (1 bit)
access : write-only
FRAMEDETRESUME : FRAMEDET resume
bits : 1 - 1 (1 bit)
access : write-only
INTERLEAVEWRITERESUME : Interleaver write resume
bits : 2 - 2 (1 bit)
access : write-only
INTERLEAVEREADRESUME : Interleaver read resume
bits : 3 - 3 (1 bit)
access : write-only
CONVRESUME : Convolutional coder resume
bits : 4 - 4 (1 bit)
access : write-only
CONVTERMINATE : Convolutional coder termination
bits : 5 - 5 (1 bit)
access : write-only
TXSUBFRAMERESUME : TX subframe resume
bits : 6 - 6 (1 bit)
access : write-only
INTERLEAVEINIT : Interleaver initialization
bits : 7 - 7 (1 bit)
access : write-only
INTERLEAVECNTCLEAR : Interleaver counter clear
bits : 8 - 8 (1 bit)
access : write-only
CONVINIT : Convolutional coder initialize
bits : 9 - 9 (1 bit)
access : write-only
BLOCKINIT : Block coder initialize
bits : 10 - 10 (1 bit)
access : write-only
STATEINIT : FRC State initialize
bits : 11 - 11 (1 bit)
access : write-only
RXRAWUNBLOCK : Clear RXRAWBLOCKED status flag
bits : 12 - 12 (1 bit)
access : write-only
No Description
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEEDBACKSEL : LFSR Feedback selector
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : BIT0
Select bit 0 as feedback
1 : BIT1
Select bit 1 as feedback
2 : BIT2
Select bit 2 as feedback
3 : BIT3
Select bit 3 as feedback
4 : BIT4
Select bit 4 as feedback
5 : BIT5
Select bit 5 as feedback
6 : BIT6
Select bit 6 as feedback
7 : BIT7
Select bit 7 as feedback
8 : BIT8
Select bit 8 as feedback
9 : BIT9
Select bit 9 as feedback
10 : BIT10
Select bit 10 as feedback
11 : BIT11
Select bit 11 as feedback
12 : BIT12
Select bit 12 as feedback
13 : BIT13
Select bit 13 as feedback
14 : BIT14
Select bit 14 as feedback
15 : BIT15
Select bit 15 as feedback
16 : INPUT
Select data input as feedback
17 : ZERO
Select zero as feedback
18 : ONE
Select one as feedback
19 : TXLASTWORD
In transmit mode, the feedback is one during the last transmit word and zero otherwise. In receive mode, the feedback is always zero.
End of enumeration elements list.
XORFEEDBACK : LFSR Feedback XOR setting
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : DIRECT
The signal defined by FEEDBACKSEL is used directly as Feedback.
1 : XOR
The signal defined by FEEDBACKSEL is XOR'ed with bit 15, and the result is used as Feedback
2 : ZERO
Feedback is set to 0
End of enumeration elements list.
SHROUTPUTSEL : Shift Register Output Selector
bits : 8 - 11 (4 bit)
access : read-write
BLOCKERRORCORRECT : Block Errors Correction enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : X0
Block decoding errors are not corrected, only the BLOCKERR interrupt is set on detection.
1 : X1
Block decoding errors are attempted corrected by memory lookup tables. The BLOCKERR interrupt is also set on error detection.
End of enumeration elements list.
No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POLY : Whitener Polynomial
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WHITEINIT : Whitener Initial Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCKWHITEMODE : Block Coder Whitener Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DIRECT
The input data is passed directly to the output without any other operations.
1 : WHITE
Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every bit period.
2 : BYTEWHITE
Data is whitened in TX and de-whitened in RX with the whitener feedback register updated every byte period, recommended only for compatibility purposes.
3 : INTERLEAVEDWHITE0
Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving.
4 : INTERLEAVEDWHITE1
Data is whitened in TX after symbol interleaving and de-whitened in RX before symbol de-interleaving. The first 16 (if INTERLEAVEWIDTH is 0) or 32 (if INTERLEAVEWIDTH is 1) RF symbols are not whitened or de-whitened.
5 : BLOCKCODEINSERT
Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will insert parity bits between the bit stream provided from the transmit buffer. In receive mode, the block decoder will remove parity bits and they will not further be provided to the receive buffer.
6 : BLOCKCODEREPLACE
Parity bits are added in TX and checked and removed in RX to perform block coding forward error correction (FEC). In transmit mode, the block encoder will replace bits provided by the transmit buffer with parity bits. In receive mode, the block decoder will output both data bits and parity bits to the receive buffer.
7 : BLOCKLOOKUP
A lookup table is used to implement table lookup block coding in TX, and table lookup block decoding in RX.
End of enumeration elements list.
CONVMODE : Convolutional Encoder / Decoder mode.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Convolutional encoding / decoding is disabled
1 : CONVOLUTIONAL
Normal convolutional encoding / decoding is enabled
2 : REPEAT
Repeat-mode convolutional encoding / decoding is enabled
End of enumeration elements list.
CONVDECODEMODE : Convolutional decoding mode setting.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : SOFT
Use soft decision convolutional decoding, recommended in most cases.
1 : HARD
Use hard decision convolutional decoding.
End of enumeration elements list.
CONVTRACEBACKDISABLE : Convolutional traceback disabling
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : X0
Traceback history is enabled, and convolutional decoding will use RAM to store state information. In receive mode, output from convolutional decoding will be generated after the traceback history has reached a certain level.
1 : X1
Traceback history is disabled, and convolutional decoding will not use RAM to store state information. No trellis termination sequence will be automatically appended to the transmit data. In receive mode, output from convolutional decoding will be generated after every state transition. This will not provide any convolutional decoding gain, but can be used to decode very simple codes without using any RAM memory.
End of enumeration elements list.
CONVINV : Convolutional code symbol inversion
bits : 8 - 9 (2 bit)
access : read-write
INTERLEAVEMODE : Interleaver mode.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
Interleaving is disabled
1 : ENABLE
Interleaving is enabled
2 : RXBUFFER
No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive mode. This may, for instance, be used for receiver pause functionality.
3 : RXTXBUFFER
No symbol interleaving is performed, but the interleaver data storage is used as a data buffer in receive and transmit mode. This may, for instance, be used for receiver and transmitter pause functionality.
End of enumeration elements list.
INTERLEAVEFIRSTINDEX : 4-bit index of the first interleaver
bits : 12 - 15 (4 bit)
access : read-write
INTERLEAVEWIDTH : Interleave symbol width.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : ONE
Each interleaver element consists of one RF symbol
1 : TWO
Each interleaver element consists of two RF symbols
End of enumeration elements list.
CONVBUSLOCK : Convolutional decoding bus lock
bits : 17 - 17 (1 bit)
access : read-write
CONVSUBFRAMETERMINATE : Enable trellis termination for subframes
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : X0
Trellis termination is applied at the end of the frame.
1 : X1
Trellis termination is applied at the end of each subframe and at the end of the frame.
End of enumeration elements list.
SINGLEBLOCK : Single block code per frame
bits : 19 - 19 (1 bit)
access : read-write
FORCE2FSK : Force use of 2-FSK
bits : 20 - 20 (1 bit)
access : read-write
CONVHARDERROR : Enable convolutional decoding hard error
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : X0
Convolutional hard error decoding is disabled.
1 : X1
Convolutional hard error decoding is enabled.
End of enumeration elements list.
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLOCKRAMADDR : Block decoding RAM address
bits : 2 - 18 (17 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONVRAMADDR : Convolutional decoding RAM address
bits : 2 - 18 (17 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDOMTX : Random TX Mode
bits : 0 - 0 (1 bit)
access : read-write
UARTMODE : Data Uart Mode
bits : 1 - 1 (1 bit)
access : read-write
BITORDER : Data Bit Order.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LSBFIRST
Least Significant bit in each word is sent/received first.
1 : MSBFIRST
Most Significant bit in each word is sent/received first.
End of enumeration elements list.
TXFCDMODE : TX Frame Control Descriptor Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : FCDMODE0
FCD0 is reloaded when SCNT reaches 0
1 : FCDMODE1
Use FCD0 for the first sub-frame, then switching between FCD0 and FCD1 for following sub-frames
2 : FCDMODE2
Use FCD0 for the first sub-frame, then FCD1 is used for all following sub-frames
3 : FCDMODE3
Use alternating FCD0 / FCD1 for each complete frame
End of enumeration elements list.
RXFCDMODE : RX Frame Control Descriptor Mode
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : FCDMODE0
FCD2 is reloaded when SCNT reaches 0
1 : FCDMODE1
Use FCD2 for the first sub-frame, then switching between FCD2 and FCD3 for following sub-frames
2 : FCDMODE2
Use FCD2 for the first sub-frame, then FCD3 is used for all following sub-frames
3 : FCDMODE3
Use alternating FCD2 / FCD3 for each complete frame
End of enumeration elements list.
BITSPERWORD : Bits Per Word, for first word in a frame
bits : 8 - 10 (3 bit)
access : read-write
RATESELECT : MODEM rate select
bits : 11 - 12 (2 bit)
access : read-write
TXPREFETCH : Transmit prefetch data
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : X0
The frame controller will start preparing transmit data when entering the TX state. This setting may be used in most cases.
1 : X1
The frame controller will start preparing transmit data already in the TXWARM, RX2TX or TX2TX state. This setting must be used to avoid transmit underflow in the cases where no preamble or frame synchronization is inserted by the modulator (i.e. typically when the MODEM control fields TXBASES is zero and SYNCDATA is set).
End of enumeration elements list.
SEQHANDSHAKE : Sequencer data handshake
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : X0
The sequencer may read transmit or read data through the FRCRD command, but it will not wait for the sequencer to do so before proceeding to parse transmit or receive data.
1 : X1
The frame controller will require that the sequencer program uses the FRCRD command to read both transmit and receive data which the frame controller stores in the DATABUFFER register. If data is not read with this field set, the overflow (RXOF) or underflow (TXUF) will be set.
End of enumeration elements list.
PRBSTEST : Pseudo-Random Bit Sequence Testmode
bits : 17 - 17 (1 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STORECRC : Store CRC value.
bits : 0 - 0 (1 bit)
access : read-write
ACCEPTCRCERRORS : Accept CRC Errors.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : REJECT
Frames with one or more detected CRC errors will be cleared from the receiver buffer.
1 : ACCEPT
Frames will always be written to the receive buffer, regardless of CRC errors.
End of enumeration elements list.
ACCEPTBLOCKERRORS : Accept Block Decoding Errors.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : REJECT
Frame reception will be stopped when a block decoding error is found.
1 : ACCEPT
Frame reception will continue even in the case of a block decoding error.
End of enumeration elements list.
TRACKABFRAME : Track Aborted RX Frame
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : X0
When a frame abort is triggered, the frame reception is immediately aborted, the RXABORTED interrupt flag is set, and the receiver may start searching for a new frame.
1 : X1
When a frame abort is triggered, the receiver is still enabled for the duration of the frame (as defined by the frame length), but no data output is generated. Only when the complete frame is received, the RXABORTED interrupt flag is set and a new frame reception may begin. This mode may, for instance, be used to avoid finding a new FRAMEDET event inside the payload data of a discarded frame.
End of enumeration elements list.
BUFCLEAR : Buffer Clear
bits : 4 - 4 (1 bit)
access : read-write
BUFRESTOREFRAMEERROR : Buffer restore on frame error
bits : 5 - 5 (1 bit)
access : read-write
BUFRESTORERXABORTED : Buffer restore on RXABORTED
bits : 6 - 6 (1 bit)
access : read-write
RXFRAMEENDAHEADBYTES : RX frame almost end of packet timing
bits : 7 - 10 (4 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRAILTXDATA : Trailing Data value
bits : 0 - 7 (8 bit)
access : read-write
TRAILTXDATACNT : Trailing data bit count
bits : 8 - 10 (3 bit)
access : read-write
TRAILTXDATAFORCE : Force trailing TX data insertion
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : X0
Trailing data in transmit is only applied in order to fill up an integer number of block coding and interleaver buffers. If block coding and interleaving is not used, no trailing data is transmitted.
1 : X1
The number of bits defined by TRAILTXDATACNT is always appended to the transmit data, in addition to the necessary bits to fill up an integer number of block coding and interleaver buffers.
End of enumeration elements list.
No Description
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSI : Append RSSI
bits : 0 - 0 (1 bit)
access : read-write
CRCOK : Append CRC OK Indicator
bits : 1 - 1 (1 bit)
access : read-write
PROTIMERCC0BASE : PROTIMER Capture Compare channel 0 Base
bits : 2 - 2 (1 bit)
access : read-write
PROTIMERCC0WRAPL : PROTIMER Capture Compare channel 0 WrapL
bits : 3 - 3 (1 bit)
access : read-write
PROTIMERCC0WRAPH : PROTIMER Capture Compare channel 0 WrapH
bits : 4 - 4 (1 bit)
access : read-write
RTCSTAMP : RTCC Time Stamp
bits : 5 - 5 (1 bit)
access : read-write
No Description
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCNT : Sub-Frame Counter Value
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GENERATOR0 : Output 0 Generator Polynomial
bits : 0 - 6 (7 bit)
access : read-write
GENERATOR1 : Output 1 Generator Polynomial
bits : 8 - 14 (7 bit)
access : read-write
RECURSIVE : Convolutional encoding
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : X0
Non-recursive convolutional coding is used
1 : X1
Recursive convolutional coding is used
End of enumeration elements list.
NONSYSTEMATIC : Non systematic recursive code
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : X0
The recursive code is systematic
1 : X1
The recursive code is not systematic
End of enumeration elements list.
No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUNCT0 : Puncturing Matrix Row for Output 0
bits : 0 - 6 (7 bit)
access : read-write
PUNCT1 : Puncturing Matrix Row for Output 1
bits : 8 - 14 (7 bit)
access : read-write
No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAMEDETPAUSEEN : Frame detect pause enable
bits : 0 - 0 (1 bit)
access : read-write
TXINTERLEAVEWRITEPAUSEEN : Transmit interleaver write pause enable
bits : 1 - 1 (1 bit)
access : read-write
RXINTERLEAVEWRITEPAUSEEN : Receive interleaver write pause enable
bits : 2 - 2 (1 bit)
access : read-write
INTERLEAVEREADPAUSEEN : Interleaver read pause enable
bits : 3 - 3 (1 bit)
access : read-write
TXSUBFRAMEPAUSEEN : Transmit subframe pause enable
bits : 4 - 4 (1 bit)
access : read-write
CONVPAUSECNT : Convolutional decoder pause setting
bits : 5 - 10 (6 bit)
access : read-write
INTERLEAVEWRITEPAUSECNT : Interleaver write pause count
bits : 11 - 15 (5 bit)
access : read-write
INTERLEAVEREADPAUSECNT : Interleaver read pause count
bits : 16 - 20 (5 bit)
access : read-write
No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDONE : TX Done Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
TXAFTERFRAMEDONE : TX after frame Done Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
TXABORTED : Transmit Aborted Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
TXUF : Transmit Underflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
RXDONE : RX Done Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
RXABORTED : RX Aborted Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
FRAMEERROR : Frame Error Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
BLOCKERROR : Block Error Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write
RXOF : Receive Overflow Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
WCNTCMP0 : Word Counter Compare 0 Event
bits : 9 - 9 (1 bit)
access : read-write
WCNTCMP1 : Word Counter Compare 1 Event
bits : 10 - 10 (1 bit)
access : read-write
WCNTCMP2 : Word Counter Compare 2 Event
bits : 11 - 11 (1 bit)
access : read-write
ADDRERROR : Receive address error event
bits : 12 - 12 (1 bit)
access : read-write
BUSERROR : A bus error event occurred
bits : 13 - 13 (1 bit)
access : read-write
RXRAWEVENT : Receiver raw data event
bits : 14 - 14 (1 bit)
access : read-write
TXRAWEVENT : Transmit raw data event
bits : 15 - 15 (1 bit)
access : read-write
SNIFFOF : Data sniffer overflow
bits : 16 - 16 (1 bit)
access : read-write
FRAMEDETPAUSED : Frame detected pause event active
bits : 24 - 24 (1 bit)
access : read-write
INTERLEAVEWRITEPAUSED : Interleaver write pause event active
bits : 25 - 25 (1 bit)
access : read-write
INTERLEAVEREADPAUSED : Interleaver read pause event active
bits : 26 - 26 (1 bit)
access : read-write
TXSUBFRAMEPAUSED : Transmit subframe pause event active
bits : 27 - 27 (1 bit)
access : read-write
CONVPAUSED : Convolutional coder pause event active
bits : 28 - 28 (1 bit)
access : read-write
RXWORD : Receive Word Interrupt Flag
bits : 29 - 29 (1 bit)
access : read-write
TXWORD : Transmit Word Interrupt Flag
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDONE : TX Done Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
TXAFTERFRAMEDONE : TX after frame Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
TXABORTED : Transmit Aborted Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
TXUF : Transmit Underflow Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
RXDONE : RX Done Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
RXABORTED : RX Aborted Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
FRAMEERROR : Frame Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BLOCKERROR : Block Error Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
RXOF : Receive Overflow Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
WCNTCMP0 : Word Counter Compare 0 Enable
bits : 9 - 9 (1 bit)
access : read-write
WCNTCMP1 : Word Counter Compare 1 Enable
bits : 10 - 10 (1 bit)
access : read-write
WCNTCMP2 : Word Counter Compare 2 Enable
bits : 11 - 11 (1 bit)
access : read-write
ADDRERROR : Receive address error enable
bits : 12 - 12 (1 bit)
access : read-write
BUSERROR : Bus error enable
bits : 13 - 13 (1 bit)
access : read-write
RXRAWEVENT : Receiver raw data enable
bits : 14 - 14 (1 bit)
access : read-write
TXRAWEVENT : Transmit raw data enable
bits : 15 - 15 (1 bit)
access : read-write
SNIFFOF : Data sniffer overflow enable
bits : 16 - 16 (1 bit)
access : read-write
FRAMEDETPAUSED : Frame detected pause event enable
bits : 24 - 24 (1 bit)
access : read-write
INTERLEAVEWRITEPAUSED : Interleaver write pause event enable
bits : 25 - 25 (1 bit)
access : read-write
INTERLEAVEREADPAUSED : Interleaver read pause event enable
bits : 26 - 26 (1 bit)
access : read-write
TXSUBFRAMEPAUSED : Transmit subframe pause event enable
bits : 27 - 27 (1 bit)
access : read-write
CONVPAUSED : Convolutional coder pause event enable
bits : 28 - 28 (1 bit)
access : read-write
RXWORD : Receive Word Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write
TXWORD : Transmit Word Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDONE : TX Done Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
TXAFTERFRAMEDONE : TX after frame Done Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
TXABORTED : Transmit Aborted Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only
TXUF : Transmit Underflow Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only
RXDONE : RX Done Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only
RXABORTED : RX Aborted Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only
FRAMEERROR : Frame Error Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only
BLOCKERROR : Block Error Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only
RXOF : Receive Overflow Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only
ADDRERROR : Receive address error event
bits : 9 - 9 (1 bit)
access : read-only
BUSERROR : A bus error event occurred
bits : 10 - 10 (1 bit)
access : read-only
SNIFFOF : Data sniffer overflow
bits : 11 - 11 (1 bit)
access : read-only
FRAMEDETPAUSED : Frame detected pause event active
bits : 12 - 12 (1 bit)
access : read-only
INTERLEAVEWRITEPAUSED : Interleaver write pause event active
bits : 13 - 13 (1 bit)
access : read-only
INTERLEAVEREADPAUSED : Interleaver read pause event active
bits : 14 - 14 (1 bit)
access : read-only
TXSUBFRAMEPAUSED : Transmit subframe pause event active
bits : 15 - 15 (1 bit)
access : read-only
CONVPAUSED : Convolutional coder pause event active
bits : 16 - 16 (1 bit)
access : read-only
IFMIRRORCLEAR : Clear bit for the FRC IF MIRROR Register
bits : 17 - 17 (1 bit)
access : read-write
No Description
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBUFFERMODE : Transmit Buffer Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : BUFC
The Frame Controller fetches data from the Buffer Controller (BUFC) in transmit mode.
1 : REGISTER
The Frame Controller does not fetch data from the Buffer Controller in transmit mode. Instead, data must be written to the DATABUFFER register when the TXWORD interrupt flag is set.
End of enumeration elements list.
RXBUFFERMODE : Receive Buffer Mode
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : BUFC
The Frame Controller write data to the Buffer Controller (BUFC) in receive mode.
1 : REGISTER
The Frame Controller does not write data to the Buffer Controller in receive mode. Instead, data must be read from the DATABUFFER register when the RXWORD interrupt flag is set.
2 : DISABLE
The Frame Controller will not output demodulated data. This mode can, for instance, be used together with storing RAW frame data.
End of enumeration elements list.
RXFRCBUFMUX : RX FRC Buffer Mux
bits : 3 - 3 (1 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SNIFFDCOUNT : Sniffer data count
bits : 0 - 4 (5 bit)
access : read-only
ACTIVETXFCD : Active Transmit Frame Descriptor
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : FCD0
FCD0 is active
1 : FCD1
FCD1 is active
End of enumeration elements list.
ACTIVERXFCD : Active Receive Frame Descriptor
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : FCD2
FCD2 is active
1 : FCD3
FCD3 is active
End of enumeration elements list.
SNIFFDFRAME : Sniffer data frame active status
bits : 7 - 7 (1 bit)
access : read-only
RXRAWBLOCKED : Receiver raw trigger block is active
bits : 8 - 8 (1 bit)
access : read-only
FRAMEOK : Frame valid
bits : 9 - 9 (1 bit)
access : read-only
RXABORTINPROGRESS : Receive aborted in progress status flag
bits : 10 - 10 (1 bit)
access : read-only
TXWORD : Transmit Word Flag
bits : 11 - 11 (1 bit)
access : read-only
RXWORD : Receive Word Flag
bits : 12 - 12 (1 bit)
access : read-only
CONVPAUSED : Convolutional coder pause event active
bits : 13 - 13 (1 bit)
access : read-only
TXSUBFRAMEPAUSED : Transmit subframe pause event active
bits : 14 - 14 (1 bit)
access : read-only
INTERLEAVEREADPAUSED : Interleaver read pause event active
bits : 15 - 15 (1 bit)
access : read-only
INTERLEAVEWRITEPAUSED : Interleaver write pause event active
bits : 16 - 16 (1 bit)
access : read-only
FRAMEDETPAUSED : Frame detected pause event active
bits : 17 - 17 (1 bit)
access : read-only
FRAMELENGTHERROR : Frame Length Error for RX and TX
bits : 18 - 18 (1 bit)
access : read-only
DEMODERROR : Demod Error in RX
bits : 19 - 19 (1 bit)
access : read-only
No Description
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNIFFMODE : Data Sniff Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
FRC Packet Sniffer mode is disabled
1 : UART
UART encoded data is transmitted on the DOUT pin.
2 : SPI
SPI data is transmitted on the DOUT pin and a data clock is output to the DCLK pin.
End of enumeration elements list.
SNIFFBITS : Data sniff data bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : EIGHT
Each sniffer output word contains 8 data bits
1 : NINE
Each sniffer output word contains 9 data bits
End of enumeration elements list.
SNIFFRXDATA : Enable sniffing of received data.
bits : 3 - 3 (1 bit)
access : read-write
SNIFFTXDATA : Enable sniffing of transmitted data.
bits : 4 - 4 (1 bit)
access : read-write
SNIFFRSSI : Enable sniffing of RSSI
bits : 5 - 5 (1 bit)
access : read-write
SNIFFSTATE : Enable sniffing of state information
bits : 6 - 6 (1 bit)
access : read-write
SNIFFAUXDATA : Enable sniffing of auxiliary data
bits : 7 - 7 (1 bit)
access : read-write
SNIFFBR : Sniffer baudrate setting
bits : 8 - 15 (8 bit)
access : read-write
SNIFFSYNCWORD : Sniffer baudrate setting
bits : 17 - 17 (1 bit)
access : read-write
No Description
address_offset : 0x88 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
AUXDATA : Auxiliary sniffer data output
bits : 0 - 8 (9 bit)
access : write-only
No Description
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXRAWMODE : Transmitter raw data mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : DISABLE
RAW transmit mode is disabled
1 : SINGLEBUFFER
RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) once before transmit is completed.
2 : REPEATBUFFER
RAW transmit mode is enabled, transmitting the configured raw data (fetched from RAM) repeatedly until the transmitter is disabled.
End of enumeration elements list.
RXRAWMODE : Receiver raw data mode
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : DISABLE
RAW receive mode is disabled
1 : SINGLEITEM
RAW receive mode is enabled, fetching a single item which is stored in the RXRAWDATA register. A new item is fetched when the RXRAWBLOCKED flag is cleared. In this mode, the flag is cleared automatically when RXRAWDATA is read.
2 : SINGLEBUFFER
RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception.
3 : SINGLEBUFFERFRAME
This mode is identical to the SINGLEBUFFER mode, except that the FRC will treat the end of the filled buffer as the end of a frame reception (i.e. also trigger the RXDONE interrupt and signal to the RAC that frame reception is complete.)
4 : REPEATBUFFER
RAW receive mode is enabled, fetching multiple items which are stored to RAM. The RXRAWBLOCKED flag must be cleared in order to start raw data reception.
End of enumeration elements list.
RXRAWRANDOM : Receive raw data random number generator
bits : 5 - 5 (1 bit)
access : read-write
RXRAWTRIGGER : Receiver raw data trigger setting
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : IMMEDIATE
RAW data storage is triggered immediately when demodulator is enabled.
1 : PRS
RAW data storage is triggered by the selected RXRAWPRSSEL PRS channel.
End of enumeration elements list.
DEMODRAWDATAMUX : Raw data mux control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DEMODRAWDATASEL
RAW data is selected using modem register DEMODRAWDATASEL.
1 : DEMODRAWDATASEL2
RAW data is selected using modem register DEMODRAWDATASEL2.
End of enumeration elements list.
No Description
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRAWDATA : Receiver RAW data register
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x94 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PAUSEDATA : Receiver pause data register
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x98 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LIKELYCONVSTATE : Most likely convolutional decoder state
bits : 0 - 5 (6 bit)
access : read-only
No Description
address_offset : 0x9C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTELEMENTNEXT : Interleaver element value
bits : 0 - 7 (8 bit)
access : read-only
No Description
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTWRITEPOINT : Interleaver buffer write pointer
bits : 0 - 4 (5 bit)
access : read-write
No Description
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTREADPOINT : Interleaver buffer read pointer
bits : 0 - 4 (5 bit)
access : read-write
No Description
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUTOCGEN : Automatic clock gate enable
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORCEOFF : Force off
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMBASEADDR : RAM BASE ADDR
bits : 12 - 31 (20 bit)
access : read-write
No Description
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORDS : No of Words in sub-frame
bits : 0 - 7 (8 bit)
access : read-write
BUFFER : Buffer to Access
bits : 8 - 9 (2 bit)
access : read-write
INCLUDECRC : Include CRC
bits : 10 - 10 (1 bit)
access : read-write
CALCCRC : Calculate CRC
bits : 11 - 11 (1 bit)
access : read-write
SKIPCRC : Skip First Words in CRC Calculation
bits : 12 - 13 (2 bit)
access : read-write
SKIPWHITE : Skip data whitening in this subframe
bits : 14 - 14 (1 bit)
access : read-write
ADDTRAILTXDATA : Add trailing TX data in this subframe
bits : 15 - 15 (1 bit)
access : read-write
EXCLUDESUBFRAMEWCNT : Exclude subframe from WCNT
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORDS : No of Words in sub-frame
bits : 0 - 7 (8 bit)
access : read-write
BUFFER : Buffer to Access
bits : 8 - 9 (2 bit)
access : read-write
INCLUDECRC : Include CRC
bits : 10 - 10 (1 bit)
access : read-write
CALCCRC : Calculate CRC
bits : 11 - 11 (1 bit)
access : read-write
SKIPCRC : Skip First Words in CRC Calculation
bits : 12 - 13 (2 bit)
access : read-write
SKIPWHITE : Skip data whitening in this subframe
bits : 14 - 14 (1 bit)
access : read-write
ADDTRAILTXDATA : Add trailing TX data in this subframe
bits : 15 - 15 (1 bit)
access : read-write
EXCLUDESUBFRAMEWCNT : Exclude subframe from WCNT
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORDS : No of Words in sub-frame
bits : 0 - 7 (8 bit)
access : read-write
BUFFER : Buffer to Access
bits : 8 - 9 (2 bit)
access : read-write
INCLUDECRC : Include CRC
bits : 10 - 10 (1 bit)
access : read-write
CALCCRC : Calculate CRC
bits : 11 - 11 (1 bit)
access : read-write
SKIPCRC : Skip First Words in CRC Calculation
bits : 12 - 13 (2 bit)
access : read-write
SKIPWHITE : Skip data whitening in this subframe
bits : 14 - 14 (1 bit)
access : read-write
ADDTRAILTXDATA : Add trailing TX data in this subframe
bits : 15 - 15 (1 bit)
access : read-write
EXCLUDESUBFRAMEWCNT : Exclude subframe from WCNT
bits : 16 - 16 (1 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DFLMODE : Dynamic Frame Length Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : DISABLE
Dynamic Frame Length support is disabled, and the frame length is controlled by writing directly to the FRAMELENGTH field
1 : SINGLEBYTE
Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the least significant byte of the extracted length field
2 : SINGLEBYTEMSB
Dynamic Frame Length is enabled and located in a single byte over air. This byte is loaded into the most significant byte of the extracted length field
3 : DUALBYTELSBFIRST
Dynamic Frame Length is enabled and located in two bytes over air, of which the least significant byte is transferred first
4 : DUALBYTEMSBFIRST
Dynamic Frame Length is enabled and located in two bytes over air, of which the most significant byte is transferred first
5 : INFINITE
Dynamic Frame Length support is disabled, and infinite frame lengths are transmitted and received. RXABORT may be used to abort active receive operations, while the TXDIS command (available in the RAC) may be used to abort active transmit operations.
6 : BLOCKERROR
In transmit mode, the frame length must be written directly to the FRAMELENGTH field. In receive mode, data will be received until a block decoding error is found.
End of enumeration elements list.
DFLBITORDER : Dynamic Frame Length Bit order
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NORMAL
Bit ordering is defined by the BITORDER field
1 : REVERSE
Bit ordering is reversed, compared to what is defined by the BITORDER field
End of enumeration elements list.
DFLSHIFT : Dynamic Frame Length bitshift
bits : 4 - 6 (3 bit)
access : read-write
DFLOFFSET : Length Field Offset Value
bits : 8 - 11 (4 bit)
access : read-write
DFLBITS : Length field number of bits
bits : 12 - 15 (4 bit)
access : read-write
MINLENGTH : Minimum decoded length
bits : 16 - 19 (4 bit)
access : read-write
DFLINCLUDECRC : Length field includes CRC values or not
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : X0
The CRC values are not included in the frame length
1 : X1
The CRC values are included in the frame length
End of enumeration elements list.
No Description
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORDS : No of Words in sub-frame
bits : 0 - 7 (8 bit)
access : read-write
BUFFER : Buffer to Access
bits : 8 - 9 (2 bit)
access : read-write
INCLUDECRC : Include CRC
bits : 10 - 10 (1 bit)
access : read-write
CALCCRC : Calculate CRC
bits : 11 - 11 (1 bit)
access : read-write
SKIPCRC : Skip First Words in CRC Calculation
bits : 12 - 13 (2 bit)
access : read-write
SKIPWHITE : Skip data whitening in this subframe
bits : 14 - 14 (1 bit)
access : read-write
ADDTRAILTXDATA : Add trailing TX data in this subframe
bits : 15 - 15 (1 bit)
access : read-write
EXCLUDESUBFRAMEWCNT : Exclude subframe from WCNT
bits : 16 - 16 (1 bit)
access : read-write
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