\n

EMU_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DECBOD

BOD3SENSE

LOCK

IF

IEN

EM4CTRL

CMD

CTRL

TEMPLIMITS

STATUS

TEMP

RSTCTRL

RSTCAUSE

DGIF

DGIEN

SEIF

SEIEN


DECBOD

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DECBOD DECBOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DECBODEN DECBODMASK DECOVMBODEN DECOVMBODMASK

DECBODEN : DECBOD enable
bits : 0 - 0 (1 bit)
access : read-write

DECBODMASK : DECBOD Mask
bits : 1 - 1 (1 bit)
access : read-write

DECOVMBODEN : Over Voltage Monitor enable
bits : 4 - 4 (1 bit)
access : read-write

DECOVMBODMASK : Over Voltage Monitor Mask
bits : 5 - 5 (1 bit)
access : read-write


BOD3SENSE

No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOD3SENSE BOD3SENSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVDDBODEN IOVDD0BODEN IOVDD1BODEN

AVDDBODEN : AVDD BOD enable
bits : 0 - 0 (1 bit)
access : read-write

IOVDD0BODEN : VDDIO0 BOD enable
bits : 1 - 1 (1 bit)
access : read-write

IOVDD1BODEN : VDDIO1 BOD enable
bits : 2 - 2 (1 bit)
access : read-write


LOCK

No Description
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Lock Key
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

44520 : UNLOCK

Unlock EMU register

End of enumeration elements list.


IF

No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVDDBOD IOVDD0BOD EM23WAKEUP TEMP TEMPLOW TEMPHIGH

AVDDBOD : AVDD BOD Interrupt flag
bits : 16 - 16 (1 bit)
access : read-write

IOVDD0BOD : VDDIO0 BOD Interrupt flag
bits : 17 - 17 (1 bit)
access : read-write

EM23WAKEUP : EM23 Wake up Interrupt flag
bits : 24 - 24 (1 bit)
access : read-write

TEMP : Temperature Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt flag
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt flag
bits : 31 - 31 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVDDBOD IOVDD0BOD EM23WAKEUP TEMP TEMPLOW TEMPHIGH

AVDDBOD : AVDD BOD Interrupt enable
bits : 16 - 16 (1 bit)
access : read-write

IOVDD0BOD : VDDIO0 BOD Interrupt enable
bits : 17 - 17 (1 bit)
access : read-write

EM23WAKEUP : EM23 Wake up Interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

TEMP : Temperature Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt enable
bits : 31 - 31 (1 bit)
access : read-write


EM4CTRL

No Description
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM4CTRL EM4CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4ENTRY EM4IORETMODE

EM4ENTRY : EM4 entry request
bits : 0 - 1 (2 bit)
access : read-write

EM4IORETMODE : EM4 IO retention mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : DISABLE

No Retention: Pads enter reset state when entering EM4

1 : EM4EXIT

Retention through EM4: Pads enter reset state when exiting EM4

2 : SWUNLATCH

Retention through EM4 and Wakeup: software sets EM4UNLATCH in EMU_CMD register to remove retention

End of enumeration elements list.


CMD

No Description
address_offset : 0x70 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4UNLATCH RSTCAUSECLR

EM4UNLATCH : EM4 unlatch
bits : 1 - 1 (1 bit)
access : write-only

RSTCAUSECLR : Reset Cause Clear
bits : 17 - 17 (1 bit)
access : write-only


CTRL

No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM2DBGEN FLASHPWRUPONDEMAND

EM2DBGEN : Enable debugging in EM2
bits : 0 - 0 (1 bit)
access : read-write

FLASHPWRUPONDEMAND : Enable flash on demand wakeup
bits : 16 - 16 (1 bit)
access : read-write


TEMPLIMITS

No Description
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEMPLIMITS TEMPLIMITS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMPLOW TEMPHIGH

TEMPLOW : Temp Low limit
bits : 0 - 8 (9 bit)
access : read-write

TEMPHIGH : Temp High limit
bits : 16 - 24 (9 bit)
access : read-write


STATUS

No Description
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK FIRSTTEMPDONE TEMPACTIVE RACACTIVE EM4IORET EM2ENTERED

LOCK : Lock status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

All EMU lockable registers are unlocked.

1 : LOCKED

All EMU lockable registers are locked.

End of enumeration elements list.

FIRSTTEMPDONE : First Temp done
bits : 1 - 1 (1 bit)
access : read-only

TEMPACTIVE : Temp active
bits : 2 - 2 (1 bit)
access : read-only

RACACTIVE : RAC active
bits : 10 - 10 (1 bit)
access : read-only

EM4IORET : EM4 IO retention status
bits : 12 - 12 (1 bit)
access : read-only

EM2ENTERED : EM2 entered
bits : 14 - 14 (1 bit)
access : read-only


TEMP

No Description
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TEMP TEMP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMPLSB TEMP

TEMPLSB : Temperature measured decimal part
bits : 0 - 1 (2 bit)
access : read-only

TEMP : Temperature measured
bits : 2 - 10 (9 bit)
access : read-only


RSTCTRL

No Description
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCTRL RSTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDOG0RMODE WDOG1RMODE SYSRMODE LOCKUPRMODE AVDDBODRMODE IOVDD0BODRMODE DECBODRMODE SESYSRMODE SELOCKUPRMODE

WDOG0RMODE : Enable WDOG0 reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

WDOG1RMODE : Enable WDOG1 reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

SYSRMODE : Enable M33 System reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

Device is reset except some EMU registers

End of enumeration elements list.

LOCKUPRMODE : Enable M33 Lockup reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset Request is Block

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

AVDDBODRMODE : Enable AVDD BOD reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset Request is block

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

IOVDD0BODRMODE : Enable VDDIO0 BOD reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

DECBODRMODE : Enable DECBOD reset
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset

End of enumeration elements list.

SESYSRMODE : Enable SE System reset
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.

SELOCKUPRMODE : Enable SE Lockup reset
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLED

Reset request is blocked

1 : ENABLED

The entire device is reset except some EMU registers

End of enumeration elements list.


RSTCAUSE

No Description
address_offset : 0x94 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSTCAUSE RSTCAUSE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR PIN EM4 WDOG0 WDOG1 LOCKUP SYSREQ DVDDBOD DVDDLEBOD DECBOD AVDDBOD IOVDD0BOD SETAMPER SESYSREQ SELOCKUP

POR : Power On Reset
bits : 0 - 0 (1 bit)
access : read-only

PIN : Pin Reset
bits : 1 - 1 (1 bit)
access : read-only

EM4 : EM4 Wakeup Reset
bits : 2 - 2 (1 bit)
access : read-only

WDOG0 : Watchdog 0 Reset
bits : 3 - 3 (1 bit)
access : read-only

WDOG1 : Watchdog 1 Reset
bits : 4 - 4 (1 bit)
access : read-only

LOCKUP : M33 Core Lockup Reset
bits : 5 - 5 (1 bit)
access : read-only

SYSREQ : M33 Core Sys Reset
bits : 6 - 6 (1 bit)
access : read-only

DVDDBOD : HVBOD Reset
bits : 7 - 7 (1 bit)
access : read-only

DVDDLEBOD : LEBOD Reset
bits : 8 - 8 (1 bit)
access : read-only

DECBOD : LVBOD Reset
bits : 9 - 9 (1 bit)
access : read-only

AVDDBOD : LEBOD1 Reset
bits : 10 - 10 (1 bit)
access : read-only

IOVDD0BOD : LEBOD2 Reset
bits : 11 - 11 (1 bit)
access : read-only

SETAMPER : SE Tamper event Reset
bits : 13 - 13 (1 bit)
access : read-only

SESYSREQ : SE System Reset
bits : 14 - 14 (1 bit)
access : read-only

SELOCKUP : SE Lockup Reset
bits : 15 - 15 (1 bit)
access : read-only


DGIF

No Description
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGIF DGIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM23WAKEUP TEMP TEMPLOW TEMPHIGH

EM23WAKEUP : EM23 Wake up Interrupt flag
bits : 24 - 24 (1 bit)
access : read-write

TEMP : Temperature Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt flag
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt flag
bits : 31 - 31 (1 bit)
access : read-write


DGIEN

No Description
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DGIEN DGIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM23WAKEUP TEMP TEMPLOW TEMPHIGH

EM23WAKEUP : EM23 Wake up Interrupt enable
bits : 24 - 24 (1 bit)
access : read-write

TEMP : Temperature Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt enable
bits : 31 - 31 (1 bit)
access : read-write


SEIF

No Description
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEIF SEIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMP TEMPLOW TEMPHIGH

TEMP : Temperature Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature Interrupt flag
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature low Interrupt flag
bits : 31 - 31 (1 bit)
access : read-write


SEIEN

No Description
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEIEN SEIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMP TEMPLOW TEMPHIGH

TEMP : Temperature Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : Temperature low Interrupt enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : Temperature high Interrupt enable
bits : 31 - 31 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.