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USART2_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

TRIGCTRL

CMD

STATUS

CLKDIV

RXDATAX

RXDATA

RXDOUBLEX

RXDOUBLE

RXDATAXP

RXDOUBLEXP

TXDATAX

TXDATA

EN

TXDOUBLEX

TXDOUBLE

IF

IEN

IRCTRL

I2SCTRL

TIMING

CTRLX

TIMECMP0

TIMECMP1

TIMECMP2

CTRL

FRAME


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IPVERSION
bits : 0 - 31 (32 bit)
access : read-only


TRIGCTRL

No Description
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIGCTRL TRIGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN AUTOTXTEN TXARX0EN TXARX1EN TXARX2EN RXATX0EN RXATX1EN RXATX2EN

RXTEN : Receive Trigger Enable
bits : 4 - 4 (1 bit)
access : read-write

TXTEN : Transmit Trigger Enable
bits : 5 - 5 (1 bit)
access : read-write

AUTOTXTEN : AUTOTX Trigger Enable
bits : 6 - 6 (1 bit)
access : read-write

TXARX0EN : Enable Transmit Trigger after RX End of
bits : 7 - 7 (1 bit)
access : read-write

TXARX1EN : Enable Transmit Trigger after RX End of
bits : 8 - 8 (1 bit)
access : read-write

TXARX2EN : Enable Transmit Trigger after RX End of
bits : 9 - 9 (1 bit)
access : read-write

RXATX0EN : Enable Receive Trigger after TX end of f
bits : 10 - 10 (1 bit)
access : read-write

RXATX1EN : Enable Receive Trigger after TX end of f
bits : 11 - 11 (1 bit)
access : read-write

RXATX2EN : Enable Receive Trigger after TX end of f
bits : 12 - 12 (1 bit)
access : read-write


CMD

No Description
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN RXDIS TXEN TXDIS MASTEREN MASTERDIS RXBLOCKEN RXBLOCKDIS TXTRIEN TXTRIDIS CLEARTX CLEARRX

RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only

RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only

TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : write-only

TXDIS : Transmitter Disable
bits : 3 - 3 (1 bit)
access : write-only

MASTEREN : Master Enable
bits : 4 - 4 (1 bit)
access : write-only

MASTERDIS : Master Disable
bits : 5 - 5 (1 bit)
access : write-only

RXBLOCKEN : Receiver Block Enable
bits : 6 - 6 (1 bit)
access : write-only

RXBLOCKDIS : Receiver Block Disable
bits : 7 - 7 (1 bit)
access : write-only

TXTRIEN : Transmitter Tristate Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTRIDIS : Transmitter Tristate Disable
bits : 9 - 9 (1 bit)
access : write-only

CLEARTX : Clear TX
bits : 10 - 10 (1 bit)
access : write-only

CLEARRX : Clear RX
bits : 11 - 11 (1 bit)
access : write-only


STATUS

No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXENS TXENS MASTER RXBLOCK TXTRI TXC TXBL RXDATAV RXFULL TXBDRIGHT TXBSRIGHT RXDATAVRIGHT RXFULLRIGHT TXIDLE TIMERRESTARTED TXBUFCNT

RXENS : Receiver Enable Status
bits : 0 - 0 (1 bit)
access : read-only

TXENS : Transmitter Enable Status
bits : 1 - 1 (1 bit)
access : read-only

MASTER : SPI Master Mode
bits : 2 - 2 (1 bit)
access : read-only

RXBLOCK : Block Incoming Data
bits : 3 - 3 (1 bit)
access : read-only

TXTRI : Transmitter Tristated
bits : 4 - 4 (1 bit)
access : read-only

TXC : TX Complete
bits : 5 - 5 (1 bit)
access : read-only

TXBL : TX Buffer Level
bits : 6 - 6 (1 bit)
access : read-only

RXDATAV : RX Data Valid
bits : 7 - 7 (1 bit)
access : read-only

RXFULL : RX FIFO Full
bits : 8 - 8 (1 bit)
access : read-only

TXBDRIGHT : TX Buffer Expects Double Right Data
bits : 9 - 9 (1 bit)
access : read-only

TXBSRIGHT : TX Buffer Expects Single Right Data
bits : 10 - 10 (1 bit)
access : read-only

RXDATAVRIGHT : RX Data Right
bits : 11 - 11 (1 bit)
access : read-only

RXFULLRIGHT : RX Full of Right Data
bits : 12 - 12 (1 bit)
access : read-only

TXIDLE : TX Idle
bits : 13 - 13 (1 bit)
access : read-only

TIMERRESTARTED : The USART Timer restarted itself
bits : 14 - 14 (1 bit)
access : read-only

TXBUFCNT : TX Buffer Count
bits : 16 - 17 (2 bit)
access : read-only


CLKDIV

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV AUTOBAUDEN

DIV : Fractional Clock Divider
bits : 3 - 22 (20 bit)
access : read-write

AUTOBAUDEN : AUTOBAUD detection enable
bits : 31 - 31 (1 bit)
access : read-write


RXDATAX

No Description
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAX RXDATAX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA PERR FERR

RXDATA : RX Data
bits : 0 - 8 (9 bit)
access : read-only

PERR : Data Parity Error
bits : 14 - 14 (1 bit)
access : read-only

FERR : Data Framing Error
bits : 15 - 15 (1 bit)
access : read-only


RXDATA

No Description
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATA RXDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLEX

No Description
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEX RXDOUBLEX read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 PERR0 FERR0 RXDATA1 PERR1 FERR1

RXDATA0 : RX Data 0
bits : 0 - 8 (9 bit)
access : read-only

PERR0 : Data Parity Error 0
bits : 14 - 14 (1 bit)
access : read-only

FERR0 : Data Framing Error 0
bits : 15 - 15 (1 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 16 - 24 (9 bit)
access : read-only

PERR1 : Data Parity Error 1
bits : 30 - 30 (1 bit)
access : read-only

FERR1 : Data Framing Error 1
bits : 31 - 31 (1 bit)
access : read-only


RXDOUBLE

No Description
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLE RXDOUBLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 RXDATA1

RXDATA0 : RX Data 0
bits : 0 - 7 (8 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 8 - 15 (8 bit)
access : read-only


RXDATAXP

No Description
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAXP RXDATAXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP PERRP FERRP

RXDATAP : RX Data Peek
bits : 0 - 8 (9 bit)
access : read-only

PERRP : Data Parity Error Peek
bits : 14 - 14 (1 bit)
access : read-only

FERRP : Data Framing Error Peek
bits : 15 - 15 (1 bit)
access : read-only


RXDOUBLEXP

No Description
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEXP RXDOUBLEXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP0 PERRP0 FERRP0 RXDATAP1 PERRP1 FERRP1

RXDATAP0 : RX Data 0 Peek
bits : 0 - 8 (9 bit)
access : read-only

PERRP0 : Data Parity Error 0 Peek
bits : 14 - 14 (1 bit)
access : read-only

FERRP0 : Data Framing Error 0 Peek
bits : 15 - 15 (1 bit)
access : read-only

RXDATAP1 : RX Data 1 Peek
bits : 16 - 24 (9 bit)
access : read-only

PERRP1 : Data Parity Error 1 Peek
bits : 30 - 30 (1 bit)
access : read-only

FERRP1 : Data Framing Error 1 Peek
bits : 31 - 31 (1 bit)
access : read-only


TXDATAX

No Description
address_offset : 0x38 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDATAX TXDATAX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATAX UBRXAT TXTRIAT TXBREAK TXDISAT RXENAT

TXDATAX : TX Data
bits : 0 - 8 (9 bit)
access : write-only

UBRXAT : Unblock RX After Transmission
bits : 11 - 11 (1 bit)
access : write-only

TXTRIAT : Set TXTRI After Transmission
bits : 12 - 12 (1 bit)
access : write-only

TXBREAK : Transmit Data As Break
bits : 13 - 13 (1 bit)
access : write-only

TXDISAT : Clear TXEN After Transmission
bits : 14 - 14 (1 bit)
access : write-only

RXENAT : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : write-only


TXDATA

No Description
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDATA TXDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7 (8 bit)
access : write-only


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : USART Enable
bits : 0 - 0 (1 bit)
access : read-write


TXDOUBLEX

No Description
address_offset : 0x40 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLEX TXDOUBLEX write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 UBRXAT0 TXTRIAT0 TXBREAK0 TXDISAT0 RXENAT0 TXDATA1 UBRXAT1 TXTRIAT1 TXBREAK1 TXDISAT1 RXENAT1

TXDATA0 : TX Data
bits : 0 - 8 (9 bit)
access : write-only

UBRXAT0 : Unblock RX After Transmission
bits : 11 - 11 (1 bit)
access : write-only

TXTRIAT0 : Set TXTRI After Transmission
bits : 12 - 12 (1 bit)
access : write-only

TXBREAK0 : Transmit Data As Break
bits : 13 - 13 (1 bit)
access : write-only

TXDISAT0 : Clear TXEN After Transmission
bits : 14 - 14 (1 bit)
access : write-only

RXENAT0 : Enable RX After Transmission
bits : 15 - 15 (1 bit)
access : write-only

TXDATA1 : TX Data
bits : 16 - 24 (9 bit)
access : write-only

UBRXAT1 : Unblock RX After Transmission
bits : 27 - 27 (1 bit)
access : write-only

TXTRIAT1 : Set TXTRI After Transmission
bits : 28 - 28 (1 bit)
access : write-only

TXBREAK1 : Transmit Data As Break
bits : 29 - 29 (1 bit)
access : write-only

TXDISAT1 : Clear TXEN After Transmission
bits : 30 - 30 (1 bit)
access : write-only

RXENAT1 : Enable RX After Transmission
bits : 31 - 31 (1 bit)
access : write-only


TXDOUBLE

No Description
address_offset : 0x44 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLE TXDOUBLE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 TXDATA1

TXDATA0 : TX Data
bits : 0 - 7 (8 bit)
access : write-only

TXDATA1 : TX Data
bits : 8 - 15 (8 bit)
access : write-only


IF

No Description
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF TXIDLE TCMP0 TCMP1 TCMP2

TXC : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

TXBL : TX Buffer Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

RXDATAV : RX Data Valid Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

RXFULL : RX Buffer Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

RXOF : RX Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

RXUF : RX Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

TXOF : TX Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write

TXUF : TX Underflow Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write

PERR : Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write

FERR : Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write

MPAF : Multi-Processor Address Frame Interrupt
bits : 10 - 10 (1 bit)
access : read-write

SSM : Slave-Select In Master Mode Interrupt Fl
bits : 11 - 11 (1 bit)
access : read-write

CCF : Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write

TXIDLE : TX Idle Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write

TCMP0 : Timer comparator 0 Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-write

TCMP1 : Timer comparator 1 Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-write

TCMP2 : Timer comparator 2 Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXFULL RXOF RXUF TXOF TXUF PERR FERR MPAF SSM CCF TXIDLE TCMP0 TCMP1 TCMP2

TXC : TX Complete Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

TXBL : TX Buffer Level Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

RXDATAV : RX Data Valid Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

RXFULL : RX Buffer Full Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

RXOF : RX Overflow Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

RXUF : RX Underflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

TXOF : TX Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

TXUF : TX Underflow Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

PERR : Parity Error Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

FERR : Framing Error Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

MPAF : Multi-Processor Address Frame Interrupt
bits : 10 - 10 (1 bit)
access : read-write

SSM : Slave-Select In Master Mode Interrupt Fl
bits : 11 - 11 (1 bit)
access : read-write

CCF : Collision Check Fail Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

TXIDLE : TX Idle Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

TCMP0 : Timer comparator 0 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

TCMP1 : Timer comparator 1 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write

TCMP2 : Timer comparator 2 Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write


IRCTRL

No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRCTRL IRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IREN IRPW IRFILT IRPRSEN

IREN : Enable IrDA Module
bits : 0 - 0 (1 bit)
access : read-write

IRPW : IrDA TX Pulse Width
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : ONE

IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1

1 : TWO

IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1

2 : THREE

IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1

3 : FOUR

IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1

End of enumeration elements list.

IRFILT : IrDA RX Filter
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

No filter enabled

1 : ENABLE

Filter enabled. IrDA pulse must be high for at least 5 consecutive clock cycles to be detected

End of enumeration elements list.

IRPRSEN : IrDA PRS Channel Enable
bits : 7 - 7 (1 bit)
access : read-write


I2SCTRL

No Description
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2SCTRL I2SCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MONO JUSTIFY DMASPLIT DELAY FORMAT

EN : Enable I2S Mode
bits : 0 - 0 (1 bit)
access : read-write

MONO : Stero or Mono
bits : 1 - 1 (1 bit)
access : read-write

JUSTIFY : Justification of I2S Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : LEFT

Data is left-justified

1 : RIGHT

Data is right-justified

End of enumeration elements list.

DMASPLIT : Separate DMA Request For Left/Right Data
bits : 3 - 3 (1 bit)
access : read-write

DELAY : Delay on I2S data
bits : 4 - 4 (1 bit)
access : read-write

FORMAT : I2S Word Format
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : W32D32

32-bit word, 32-bit data

1 : W32D24M

32-bit word, 32-bit data with 8 lsb masked

2 : W32D24

32-bit word, 24-bit data

3 : W32D16

32-bit word, 16-bit data

4 : W32D8

32-bit word, 8-bit data

5 : W16D16

16-bit word, 16-bit data

6 : W16D8

16-bit word, 8-bit data

7 : W8D8

8-bit word, 8-bit data

End of enumeration elements list.


TIMING

No Description
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMING TIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDELAY CSSETUP ICS CSHOLD

TXDELAY : TX frame start delay
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable - TXDELAY in USARTn_CTRL can be used for legacy

1 : ONE

Start of transmission is delayed for 1 baud-times

2 : TWO

Start of transmission is delayed for 2 baud-times

3 : THREE

Start of transmission is delayed for 3 baud-times

4 : SEVEN

Start of transmission is delayed for 7 baud-times

5 : TCMP0

Start of transmission is delayed for TCMPVAL0 baud-times

6 : TCMP1

Start of transmission is delayed for TCMPVAL1 baud-times

7 : TCMP2

Start of transmission is delayed for TCMPVAL2 baud-times

End of enumeration elements list.

CSSETUP : Chip Select Setup
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0 : ZERO

CS is not asserted before start of transmission

1 : ONE

CS is asserted for 1 baud-times before start of transmission

2 : TWO

CS is asserted for 2 baud-times before start of transmission

3 : THREE

CS is asserted for 3 baud-times before start of transmission

4 : SEVEN

CS is asserted for 7 baud-times before start of transmission

5 : TCMP0

CS is asserted before the start of transmission for TCMPVAL0 baud-times

6 : TCMP1

CS is asserted before the start of transmission for TCMPVAL1 baud-times

7 : TCMP2

CS is asserted before the start of transmission for TCMPVAL2 baud-times

End of enumeration elements list.

ICS : Inter-character spacing
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : ZERO

There is no space between charcters

1 : ONE

Create a space of 1 baud-times before start of transmission

2 : TWO

Create a space of 2 baud-times before start of transmission

3 : THREE

Create a space of 3 baud-times before start of transmission

4 : SEVEN

Create a space of 7 baud-times before start of transmission

5 : TCMP0

Create a space of before the start of transmission for TCMPVAL0 baud-times

6 : TCMP1

Create a space of before the start of transmission for TCMPVAL1 baud-times

7 : TCMP2

Create a space of before the start of transmission for TCMPVAL2 baud-times

End of enumeration elements list.

CSHOLD : Chip Select Hold
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

0 : ZERO

Disable CS being asserted after the end of transmission

1 : ONE

CS is asserted for 1 baud-times after the end of transmission

2 : TWO

CS is asserted for 2 baud-times after the end of transmission

3 : THREE

CS is asserted for 3 baud-times after the end of transmission

4 : SEVEN

CS is asserted for 7 baud-times after the end of transmission

5 : TCMP0

CS is asserted after the end of transmission for TCMPVAL0 baud-times

6 : TCMP1

CS is asserted after the end of transmission for TCMPVAL1 baud-times

7 : TCMP2

CS is asserted after the end of transmission for TCMPVAL2 baud-times

End of enumeration elements list.


CTRLX

No Description
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRLX CTRLX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGHALT CTSINV CTSEN RTSINV RXPRSEN CLKPRSEN

DBGHALT : Debug halt
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Continue to transmit until TX buffer is empty

1 : ENABLE

Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock otherwise, each single step could transmit multiple frames instead of just transmitting one frame.

End of enumeration elements list.

CTSINV : CTS Pin Inversion
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

The USn_CTS pin is low true

1 : ENABLE

The USn_CTS pin is high true

End of enumeration elements list.

CTSEN : CTS Function enabled
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Ingore CTS

1 : ENABLE

Stop transmitting when CTS is negated

End of enumeration elements list.

RTSINV : RTS Pin Inversion
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

The USn_RTS pin is low true

1 : ENABLE

The USn_RTS pin is high true

End of enumeration elements list.

RXPRSEN : PRS RX Enable
bits : 7 - 7 (1 bit)
access : read-write

CLKPRSEN : PRS CLK Enable
bits : 15 - 15 (1 bit)
access : read-write


TIMECMP0

No Description
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMECMP0 TIMECMP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMPVAL TSTART TSTOP RESTARTEN

TCMPVAL : Timer comparator 0.
bits : 0 - 7 (8 bit)
access : read-write

TSTART : Timer start source
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : DISABLE

Comparator 0 is disabled

1 : TXEOF

Comparator 0 and timer are started at TX end of frame

2 : TXC

Comparator 0 and timer are started at TX Complete

3 : RXACT

Comparator 0 and timer are started at RX going going Active (default: low)

4 : RXEOF

Comparator 0 and timer are started at RX end of frame

End of enumeration elements list.

TSTOP : Source used to disable comparator 0
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0 : TCMP0

Comparator 0 is disabled when the counter equals TCMPVAL and triggers a TCMP0 event

1 : TXST

Comparator 0 is disabled at TX start TX Engine

2 : RXACT

Comparator 0 is disabled on RX going going Active (default: low)

3 : RXACTN

Comparator 0 is disabled on RX going Inactive

End of enumeration elements list.

RESTARTEN : Restart Timer on TCMP0
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable the timer restarting on TCMP0

1 : ENABLE

Enable the timer restarting on TCMP0

End of enumeration elements list.


TIMECMP1

No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMECMP1 TIMECMP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMPVAL TSTART TSTOP RESTARTEN

TCMPVAL : Timer comparator 1.
bits : 0 - 7 (8 bit)
access : read-write

TSTART : Timer start source
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : DISABLE

Comparator 1 is disabled

1 : TXEOF

Comparator 1 and timer are started at TX end of frame

2 : TXC

Comparator 1 and timer are started at TX Complete

3 : RXACT

Comparator 1 and timer are started at RX going going Active (default: low)

4 : RXEOF

Comparator 1 and timer are started at RX end of frame

End of enumeration elements list.

TSTOP : Source used to disable comparator 1
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0 : TCMP1

Comparator 1 is disabled when the counter equals TCMPVAL and triggers a TCMP1 event

1 : TXST

Comparator 1 is disabled at TX start TX Engine

2 : RXACT

Comparator 1 is disabled on RX going going Active (default: low)

3 : RXACTN

Comparator 1 is disabled on RX going Inactive

End of enumeration elements list.

RESTARTEN : Restart Timer on TCMP1
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable the timer restarting on TCMP1

1 : ENABLE

Enable the timer restarting on TCMP1

End of enumeration elements list.


TIMECMP2

No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMECMP2 TIMECMP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMPVAL TSTART TSTOP RESTARTEN

TCMPVAL : Timer comparator 2.
bits : 0 - 7 (8 bit)
access : read-write

TSTART : Timer start source
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : DISABLE

Comparator 2 is disabled

1 : TXEOF

Comparator 2 and timer are started at TX end of frame

2 : TXC

Comparator 2 and timer are started at TX Complete

3 : RXACT

Comparator 2 and timer are started at RX going going Active (default: low)

4 : RXEOF

Comparator 2 and timer are started at RX end of frame

End of enumeration elements list.

TSTOP : Source used to disable comparator 2
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

0 : TCMP2

Comparator 2 is disabled when the counter equals TCMPVAL and triggers a TCMP2 event

1 : TXST

Comparator 2 is disabled at TX start TX Engine

2 : RXACT

Comparator 2 is disabled on RX going going Active (default: low)

3 : RXACTN

Comparator 2 is disabled on RX going Inactive

End of enumeration elements list.

RESTARTEN : Restart Timer on TCMP2
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable the timer restarting on TCMP2

1 : ENABLE

Enable the timer restarting on TCMP2

End of enumeration elements list.


CTRL

No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC LOOPBK CCEN MPM MPAB OVS CLKPOL CLKPHA MSBF CSMA TXBIL RXINV TXINV CSINV AUTOCS AUTOTRI SCMODE SCRETRANS SKIPPERRF BIT8DV ERRSDMA ERRSRX ERRSTX SSSEARLY BYTESWAP AUTOTX MVDIS SMSDELAY

SYNC : USART Synchronous Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

The USART operates in asynchronous mode

1 : ENABLE

The USART operates in synchronous mode

End of enumeration elements list.

LOOPBK : Loopback Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

The receiver is connected to and receives data from U(S)n_RX

1 : ENABLE

The receiver is connected to and receives data from U(S)n_TX

End of enumeration elements list.

CCEN : Collision Check Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Collision check is disabled

1 : ENABLE

Collision check is enabled. The receiver must be enabled for the check to be performed

End of enumeration elements list.

MPM : Multi-Processor Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

The 9th bit of incoming frames has no special function

1 : ENABLE

An incoming frame with the 9th bit equal to MPAB will be loaded into the receive buffer regardless of RXBLOCK and will result in the MPAB interrupt flag being set

End of enumeration elements list.

MPAB : Multi-Processor Address-Bit
bits : 4 - 4 (1 bit)
access : read-write

OVS : Oversampling
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : X16

Regular UART mode with 16X oversampling in asynchronous mode

1 : X8

Double speed with 8X oversampling in asynchronous mode

2 : X6

6X oversampling in asynchronous mode

3 : X4

Quadruple speed with 4X oversampling in asynchronous mode

End of enumeration elements list.

CLKPOL : Clock Polarity
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : IDLELOW

The bus clock used in synchronous mode has a low base value

1 : IDLEHIGH

The bus clock used in synchronous mode has a high base value

End of enumeration elements list.

CLKPHA : Clock Edge For Setup/Sample
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : SAMPLELEADING

Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode

1 : SAMPLETRAILING

Data is set-up on the leading edge and sampled on the trailing edge of the bus clock in synchronous mode

End of enumeration elements list.

MSBF : Most Significant Bit First
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Data is sent with the least significant bit first

1 : ENABLE

Data is sent with the most significant bit first

End of enumeration elements list.

CSMA : Action On Slave-Select In Master Mode
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : NOACTION

No action taken

1 : GOTOSLAVEMODE

Go to slave mode

End of enumeration elements list.

TXBIL : TX Buffer Interrupt Level
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : EMPTY

TXBL and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty.

1 : HALFFULL

TXBL and TXBLIF are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full.

End of enumeration elements list.

RXINV : Receiver Input Invert
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Input is passed directly to the receiver

1 : ENABLE

Input is inverted before it is passed to the receiver

End of enumeration elements list.

TXINV : Transmitter output Invert
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Output from the transmitter is passed unchanged to U(S)n_TX

1 : ENABLE

Output from the transmitter is inverted before it is passed to U(S)n_TX

End of enumeration elements list.

CSINV : Chip Select Invert
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Chip select is active low

1 : ENABLE

Chip select is active high

End of enumeration elements list.

AUTOCS : Automatic Chip Select
bits : 16 - 16 (1 bit)
access : read-write

AUTOTRI : Automatic TX Tristate
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

The output on U(S)n_TX when the transmitter is idle is defined by TXINV

1 : ENABLE

U(S)n_TX is tristated whenever the transmitter is idle

End of enumeration elements list.

SCMODE : SmartCard Mode
bits : 18 - 18 (1 bit)
access : read-write

SCRETRANS : SmartCard Retransmit
bits : 19 - 19 (1 bit)
access : read-write

SKIPPERRF : Skip Parity Error Frames
bits : 20 - 20 (1 bit)
access : read-write

BIT8DV : Bit 8 Default Value
bits : 21 - 21 (1 bit)
access : read-write

ERRSDMA : Halt DMA On Error
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Framing and parity errors have no effect on DMA requests from the USART

1 : ENABLE

DMA requests from the USART are blocked while the PERR or FERR interrupt flags are set

End of enumeration elements list.

ERRSRX : Disable RX On Error
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Framing and parity errors have no effect on receiver

1 : ENABLE

Framing and parity errors disable the receiver

End of enumeration elements list.

ERRSTX : Disable TX On Error
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Received framing and parity errors have no effect on transmitter

1 : ENABLE

Received framing and parity errors disable the transmitter

End of enumeration elements list.

SSSEARLY : Synchronous Slave Setup Early
bits : 25 - 25 (1 bit)
access : read-write

BYTESWAP : Byteswap In Double Accesses
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Normal byte order

1 : ENABLE

Byte order swapped

End of enumeration elements list.

AUTOTX : Always Transmit When RX Not Full
bits : 29 - 29 (1 bit)
access : read-write

MVDIS : Majority Vote Disable
bits : 30 - 30 (1 bit)
access : read-write

SMSDELAY : Synchronous Master Sample Delay
bits : 31 - 31 (1 bit)
access : read-write


FRAME

No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAME FRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATABITS PARITY STOPBITS

DATABITS : Data-Bit Mode
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

1 : FOUR

Each frame contains 4 data bits

2 : FIVE

Each frame contains 5 data bits

3 : SIX

Each frame contains 6 data bits

4 : SEVEN

Each frame contains 7 data bits

5 : EIGHT

Each frame contains 8 data bits

6 : NINE

Each frame contains 9 data bits

7 : TEN

Each frame contains 10 data bits

8 : ELEVEN

Each frame contains 11 data bits

9 : TWELVE

Each frame contains 12 data bits

10 : THIRTEEN

Each frame contains 13 data bits

11 : FOURTEEN

Each frame contains 14 data bits

12 : FIFTEEN

Each frame contains 15 data bits

13 : SIXTEEN

Each frame contains 16 data bits

End of enumeration elements list.

PARITY : Parity-Bit Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : NONE

Parity bits are not used

2 : EVEN

Even parity are used. Parity bits are automatically generated and checked by hardware.

3 : ODD

Odd parity is used. Parity bits are automatically generated and checked by hardware.

End of enumeration elements list.

STOPBITS : Stop-Bit Mode
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : HALF

The transmitter generates a half stop bit. Stop-bits are not verified by receiver

1 : ONE

One stop bit is generated and verified

2 : ONEANDAHALF

The transmitter generates one and a half stop bit. The receiver verifies the first stop bit

3 : TWO

The transmitter generates two stop bits. The receiver checks the first stop-bit only

End of enumeration elements list.



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