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ACMP0_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

INPUTCTRL

STATUS

IF

IEN

SYNCBUSY

EN

CFG

CTRL


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP version ID
bits : 0 - 31 (32 bit)
access : read-only


INPUTCTRL

No Description
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INPUTCTRL INPUTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSSEL NEGSEL VREFDIV CSRESSEL

POSSEL : Positive Input Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : VSS

VSS

16 : VREFDIVAVDD

Divided AVDD

17 : VREFDIVAVDDLP

Low-Power Divided AVDD

18 : VREFDIV1V25

Divided 1V25 reference

19 : VREFDIV1V25LP

Low-power Divided 1V25 reference

20 : VREFDIV2V5

Divided 2V5 reference

21 : VREFDIV2V5LP

Low-power Divided 2V5 reference

32 : VSENSE01DIV4

VSENSE0 divided by 4

33 : VSENSE01DIV4LP

Low-power VSENSE0 divided by 4

34 : VSENSE11DIV4

VSENSE1 divided by 4

35 : VSENSE11DIV4LP

Low-power VSENSE1 divided by 4

128 : PA0

Port A, Pin0

129 : PA1

Port A, Pin1

130 : PA2

Port A, Pin2

131 : PA3

Port A, Pin3

132 : PA4

Port A, Pin4

133 : PA5

Port A, Pin5

134 : PA6

Port A, Pin6

135 : PA7

Port A, Pin7

136 : PA8

Port A, Pin8

137 : PA9

Port A, Pin9

138 : PA10

Port A, Pin10

139 : PA11

Port A, Pin11

140 : PA12

Port A, Pin12

141 : PA13

Port A, Pin13

142 : PA14

Port A, Pin14

143 : PA15

Port A, Pin15

144 : PB0

Port B, Pin0

145 : PB1

Port B, Pin1

146 : PB2

Port B, Pin2

147 : PB3

Port B, Pin3

148 : PB4

Port B, Pin4

149 : PB5

Port B, Pin5

150 : PB6

Port B, Pin6

151 : PB7

Port B, Pin7

152 : PB8

Port B, Pin8

153 : PB9

Port B, Pin9

154 : PB10

Port B, Pin10

155 : PB11

Port B, Pin11

156 : PB12

Port B, Pin12

157 : PB13

Port B, Pin13

158 : PB14

Port B, Pin14

159 : PB15

Port B, Pin15

160 : PC0

Port C, Pin0

161 : PC1

Port C, Pin1

162 : PC2

Port C, Pin2

163 : PC3

Port C, Pin3

164 : PC4

Port C, Pin4

165 : PC5

Port C, Pin5

166 : PC6

Port C, Pin6

167 : PC7

Port C, Pin7

168 : PC8

Port C, Pin8

169 : PC9

Port C, Pin9

170 : PC10

Port C, Pin10

171 : PC11

Port C, Pin11

172 : PC12

Port C, Pin12

173 : PC13

Port C, Pin13

174 : PC14

Port C, Pin14

175 : PC15

Port C, Pin15

176 : PD0

Port D, Pin0

177 : PD1

Port D, Pin1

178 : PD2

Port D, Pin2

179 : PD3

Port D, Pin3

180 : PD4

Port D, Pin4

181 : PD5

Port D, Pin5

182 : PD6

Port D, Pin6

183 : PD7

Port D, Pin7

184 : PD8

Port D, Pin8

185 : PD9

Port D, Pin9

186 : PD10

Port D, Pin10

187 : PD11

Port D, Pin11

188 : PD12

Port D, Pin12

189 : PD13

Port D, Pin13

190 : PD14

Port D, Pin14

191 : PD15

Port D, Pin15

End of enumeration elements list.

NEGSEL : Negative Input Select
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

0 : VSS

VSS

16 : VREFDIVAVDD

Divided AVDD

17 : VREFDIVAVDDLP

Low-Power Divided AVDD

18 : VREFDIV1V25

Divided 1V25 reference

19 : VREFDIV1V25LP

Low-power Divided 1V25 reference

20 : VREFDIV2V5

Divided 2V5 reference

21 : VREFDIV2V5LP

Low-power Divided 2V5 reference

32 : VSENSE01DIV4

VSENSE0 divided by 4

33 : VSENSE01DIV4LP

Low-power VSENSE0 divided by 4

34 : VSENSE11DIV4

VSENSE1 divided by 4

35 : VSENSE11DIV4LP

Low-power VSENSE1 divided by 4

48 : CAPSENSE

Capsense mode

128 : PA0

Port A, Pin0

129 : PA1

Port A, Pin1

130 : PA2

Port A, Pin2

131 : PA3

Port A, Pin3

132 : PA4

Port A, Pin4

133 : PA5

Port A, Pin5

134 : PA6

Port A, Pin6

135 : PA7

Port A, Pin7

136 : PA8

Port A, Pin8

137 : PA9

Port A, Pin9

138 : PA10

Port A, Pin10

139 : PA11

Port A, Pin11

140 : PA12

Port A, Pin12

141 : PA13

Port A, Pin13

142 : PA14

Port A, Pin14

143 : PA15

Port A, Pin15

144 : PB0

Port B, Pin0

145 : PB1

Port B, Pin1

146 : PB2

Port B, Pin2

147 : PB3

Port B, Pin3

148 : PB4

Port B, Pin4

149 : PB5

Port B, Pin5

150 : PB6

Port B, Pin6

151 : PB7

Port B, Pin7

152 : PB8

Port B, Pin8

153 : PB9

Port B, Pin9

154 : PB10

Port B, Pin10

155 : PB11

Port B, Pin11

156 : PB12

Port B, Pin12

157 : PB13

Port B, Pin13

158 : PB14

Port B, Pin14

159 : PB15

Port B, Pin15

160 : PC0

Port C, Pin0

161 : PC1

Port C, Pin1

162 : PC2

Port C, Pin2

163 : PC3

Port C, Pin3

164 : PC4

Port C, Pin4

165 : PC5

Port C, Pin5

166 : PC6

Port C, Pin6

167 : PC7

Port C, Pin7

168 : PC8

Port C, Pin8

169 : PC9

Port C, Pin9

170 : PC10

Port C, Pin10

171 : PC11

Port C, Pin11

172 : PC12

Port C, Pin12

173 : PC13

Port C, Pin13

174 : PC14

Port C, Pin14

175 : PC15

Port C, Pin15

176 : PD0

Port D, Pin0

177 : PD1

Port D, Pin1

178 : PD2

Port D, Pin2

179 : PD3

Port D, Pin3

180 : PD4

Port D, Pin4

181 : PD5

Port D, Pin5

182 : PD6

Port D, Pin6

183 : PD7

Port D, Pin7

184 : PD8

Port D, Pin8

185 : PD9

Port D, Pin9

186 : PD10

Port D, Pin10

187 : PD11

Port D, Pin11

188 : PD12

Port D, Pin12

189 : PD13

Port D, Pin13

190 : PD14

Port D, Pin14

191 : PD15

Port D, Pin15

End of enumeration elements list.

VREFDIV : VREF division
bits : 16 - 21 (6 bit)
access : read-write

CSRESSEL : Capacitive Sense Mode Internal Resistor
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

0 : RES0

Internal capacitive sense resistor value 0

1 : RES1

Internal capacitive sense resistor value 1

2 : RES2

Internal capacitive sense resistor value 2

3 : RES3

Internal capacitive sense resistor value 3

4 : RES4

Internal capacitive sense resistor value 4

5 : RES5

Internal capacitive sense resistor value 5

6 : RES6

Internal capacitive sense resistor value 6

End of enumeration elements list.


STATUS

No Description
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPOUT ACMPRDY INPUTCONFLICT PORTALLOCERR

ACMPOUT : Analog Comparator Output
bits : 0 - 0 (1 bit)
access : read-only

ACMPRDY : Analog Comparator Ready
bits : 2 - 2 (1 bit)
access : read-only

INPUTCONFLICT : INPUT conflict
bits : 3 - 3 (1 bit)
access : read-only

PORTALLOCERR : Port allocation error
bits : 4 - 4 (1 bit)
access : read-only


IF

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RISE FALL ACMPRDY INPUTCONFLICT PORTALLOCERR

RISE : Rising Edge Triggered Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

FALL : Falling Edge Triggered Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

ACMPRDY : ACMP ready Interrupt flag
bits : 2 - 2 (1 bit)
access : read-write

INPUTCONFLICT : Input conflict
bits : 3 - 3 (1 bit)
access : read-write

PORTALLOCERR : Port allocation error
bits : 4 - 4 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RISE FALL ACMPRDY INPUTCONFLICT PORTALLOCERR

RISE : Rising edge interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

FALL : Falling edge interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

ACMPRDY : ACMP ready interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

INPUTCONFLICT : Input conflict interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

PORTALLOCERR : Port allocation error interrupt enable
bits : 4 - 4 (1 bit)
access : read-write


SYNCBUSY

No Description
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTCTRL

INPUTCTRL : Syncbusy for INPUTCTRL
bits : 0 - 0 (1 bit)
access : read-only


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Module enable
bits : 0 - 0 (1 bit)
access : read-write


CFG

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIAS HYST INPUTRANGE ACCURACY

BIAS : Bias Configuration
bits : 0 - 2 (3 bit)
access : read-write

HYST : Hysteresis mode
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0 : DISABLED

Hysteresis disabled

1 : SYM10MV

10mV symmetrical hysteresis

2 : SYM20MV

20mV symmetrical hysteresis

3 : SYM30MV

30mV symmetrical hysteresis

4 : POS10MV

10mV hysteresis on positive edge transitions

5 : POS20MV

20mV hysteresis on positive edge transitions

6 : POS30MV

30mV hysteresis on positive edge transitions

8 : NEG10MV

10mV hysteresis on negative edge transitions

9 : NEG20MV

20mV hysteresis on negative edge transitions

10 : NEG30MV

30mV hysteresis on negative edge transitions

End of enumeration elements list.

INPUTRANGE : Input Range
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : FULL

Use this setting when the input to the comparator core can be from 0 to AVDD.

1 : REDUCED

It is recommended to use this setting when the input to the comparator core will always be less than AVDD-0.7V.

End of enumeration elements list.

ACCURACY : ACMP accuracy mode
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : LOW

ACMP operates in low-accuracy mode but consumes less current.

1 : HIGH

ACMP operates in high-accuracy mode but consumes more current.

End of enumeration elements list.


CTRL

No Description
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTRDYVAL GPIOINV

NOTRDYVAL : Not Ready Value
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : LOW

ACMP output is 0 when the ACMP is not ready.

1 : HIGH

ACMP output is 1 when the ACMP is not ready.

End of enumeration elements list.

GPIOINV : Comparator GPIO Output Invert
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : NOTINV

The comparator output to GPIO is not inverted

1 : INV

The comparator output to GPIO is inverted

End of enumeration elements list.



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