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I2C0_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

STATE

STATUS

CLKDIV

SADDR

SADDRMASK

RXDATA

RXDOUBLE

RXDATAP

RXDOUBLEP

TXDATA

TXDOUBLE

IF

EN

IEN

CTRL

CMD


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP version ID
bits : 0 - 31 (32 bit)
access : read-only


STATE

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATE STATE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY MASTER TRANSMITTER NACKED BUSHOLD STATE

BUSY : Bus Busy
bits : 0 - 0 (1 bit)
access : read-only

MASTER : Master
bits : 1 - 1 (1 bit)
access : read-only

TRANSMITTER : Transmitter
bits : 2 - 2 (1 bit)
access : read-only

NACKED : Nack Received
bits : 3 - 3 (1 bit)
access : read-only

BUSHOLD : Bus Held
bits : 4 - 4 (1 bit)
access : read-only

STATE : Transmission State
bits : 5 - 7 (3 bit)
access : read-only

Enumeration:

0 : IDLE

No transmission is being performed.

1 : WAIT

Waiting for idle. Will send a start condition as soon as the bus is idle.

2 : START

Start transmit phase

3 : ADDR

Address transmit or receive phase

4 : ADDRACK

Address ack/nack transmit or receive phase

5 : DATA

Data transmit or receive phase

6 : DATAACK

Data ack/nack transmit or receive phase

End of enumeration elements list.


STATUS

No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTART PSTOP PACK PNACK PCONT PABORT TXC TXBL RXDATAV RXFULL TXBUFCNT

PSTART : Pending START
bits : 0 - 0 (1 bit)
access : read-only

PSTOP : Pending STOP
bits : 1 - 1 (1 bit)
access : read-only

PACK : Pending ACK
bits : 2 - 2 (1 bit)
access : read-only

PNACK : Pending NACK
bits : 3 - 3 (1 bit)
access : read-only

PCONT : Pending continue
bits : 4 - 4 (1 bit)
access : read-only

PABORT : Pending abort
bits : 5 - 5 (1 bit)
access : read-only

TXC : TX Complete
bits : 6 - 6 (1 bit)
access : read-only

TXBL : TX Buffer Level
bits : 7 - 7 (1 bit)
access : read-only

RXDATAV : RX Data Valid
bits : 8 - 8 (1 bit)
access : read-only

RXFULL : RX FIFO Full
bits : 9 - 9 (1 bit)
access : read-only

TXBUFCNT : TX Buffer Count
bits : 10 - 11 (2 bit)
access : read-only


CLKDIV

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock Divider
bits : 0 - 8 (9 bit)
access : read-write


SADDR

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR SADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Slave address
bits : 1 - 7 (7 bit)
access : read-write


SADDRMASK

No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDRMASK SADDRMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SADDRMASK

SADDRMASK : Slave Address Mask
bits : 1 - 7 (7 bit)
access : read-write


RXDATA

No Description
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATA RXDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLE

No Description
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLE RXDOUBLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 RXDATA1

RXDATA0 : RX Data 0
bits : 0 - 7 (8 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 8 - 15 (8 bit)
access : read-only


RXDATAP

No Description
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAP RXDATAP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP

RXDATAP : RX Data Peek
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLEP

No Description
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEP RXDOUBLEP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP0 RXDATAP1

RXDATAP0 : RX Data 0 Peek
bits : 0 - 7 (8 bit)
access : read-only

RXDATAP1 : RX Data 1 Peek
bits : 8 - 15 (8 bit)
access : read-only


TXDATA

No Description
address_offset : 0x34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDATA TXDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7 (8 bit)
access : write-only


TXDOUBLE

No Description
address_offset : 0x38 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLE TXDOUBLE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 TXDATA1

TXDATA0 : TX Data
bits : 0 - 7 (8 bit)
access : write-only

TXDATA1 : TX Data
bits : 8 - 15 (8 bit)
access : write-only


IF

No Description
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC TXBL RXDATAV ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP RXFULL CLERR SCLERR SDAERR

START : START condition Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

RSTART : Repeated START condition Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

ADDR : Address Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

TXC : Transfer Completed Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

TXBL : Transmit Buffer Level Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

RXDATAV : Receive Data Valid Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

ACK : Acknowledge Received Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write

NACK : Not Acknowledge Received Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write

MSTOP : Master STOP Condition Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write

ARBLOST : Arbitration Lost Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write

BUSERR : Bus Error Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-write

BUSHOLD : Bus Held Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write

TXOF : Transmit Buffer Overflow Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write

RXUF : Receive Buffer Underflow Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write

BITO : Bus Idle Timeout Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-write

CLTO : Clock Low Timeout Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-write

SSTOP : Slave STOP condition Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write

RXFULL : Receive Buffer Full Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write

CLERR : Clock Low Error Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write

SCLERR : SCL Error Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-write

SDAERR : SDA Error Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : module enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable Peripheral Clock

1 : ENABLE

Enable Peripheral Clock

End of enumeration elements list.


IEN

No Description
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC TXBL RXDATAV ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP RXFULL CLERR SCLERR SDAERR

START : START condition Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

RSTART : Repeated START condition Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

ADDR : Address Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

TXC : Transfer Completed Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

TXBL : Transmit Buffer Level Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

RXDATAV : Receive Data Valid Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

ACK : Acknowledge Received Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write

NACK : Not Acknowledge Received Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write

MSTOP : Master STOP Condition Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write

ARBLOST : Arbitration Lost Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write

BUSERR : Bus Error Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-write

BUSHOLD : Bus Held Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write

TXOF : Transmit Buffer Overflow Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write

RXUF : Receive Buffer Underflow Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write

BITO : Bus Idle Timeout Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-write

CLTO : Clock Low Timeout Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-write

SSTOP : Slave STOP condition Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write

RXFULL : Receive Buffer Full Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write

CLERR : Clock Low Error Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write

SCLERR : SCL Error Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-write

SDAERR : SDA Error Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write


CTRL

No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORERST SLAVE AUTOACK AUTOSE AUTOSN ARBDIS GCAMEN TXBIL CLHR BITO GIBITO CLTO SCLMONEN SDAMONEN

CORERST : Soft Reset the internal state registers
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

No change to internal state registers

1 : ENABLE

Reset the internal state registers

End of enumeration elements list.

SLAVE : Addressable as Slave
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

All addresses will be responded to with a NACK

1 : ENABLE

Addresses matching the programmed slave address or the general call address (if enabled) require a response from software. Other addresses are automatically responded to with a NACK.

End of enumeration elements list.

AUTOACK : Automatic Acknowledge
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Software must give one ACK command for each ACK transmitted on the I2C bus.

1 : ENABLE

Addresses that are not automatically NACK'ed, and all data is automatically acknowledged.

End of enumeration elements list.

AUTOSE : Automatic STOP when Empty
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

A stop must be sent manually when no more data is to be transmitted.

1 : ENABLE

The master automatically sends a STOP when no more data is available for transmission.

End of enumeration elements list.

AUTOSN : Automatic STOP on NACK
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Stop is not automatically sent if a NACK is received from a slave.

1 : ENABLE

The master automatically sends a STOP if a NACK is received from a slave.

End of enumeration elements list.

ARBDIS : Arbitration Disable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

When a device loses arbitration, the ARBIF interrupt flag is set and the bus is released.

1 : ENABLE

When a device loses arbitration, the ARBIF interrupt flag is set, but communication proceeds.

End of enumeration elements list.

GCAMEN : General Call Address Match Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

General call address will be NACK'ed if it is not included by the slave address and address mask.

1 : ENABLE

When a general call address is received, a software response is required

End of enumeration elements list.

TXBIL : TX Buffer Interrupt Level
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : EMPTY

TXBL status and the TXBL interrupt flag are set when the transmit buffer becomes empty. TXBL is cleared when the buffer becomes nonempty.

1 : HALF_FULL

TXBL status and the TXBL interrupt flag are set when the transmit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full

End of enumeration elements list.

CLHR : Clock Low High Ratio
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : STANDARD

Nlow=4 and Nhigh=4, and the Nlow:Nhigh ratio is 4:4

1 : ASYMMETRIC

Nlow=6 and Nhigh=3, and the Nlow:Nhigh ratio is 6:3

2 : FAST

Nlow=11 and Nhigh=6, and the Nlow:Nhigh ratio is 11:6

End of enumeration elements list.

BITO : Bus Idle Timeout
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : OFF

Timeout disabled

1 : I2C40PCC

Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

2 : I2C80PCC

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

3 : I2C160PCC

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

End of enumeration elements list.

GIBITO : Go Idle on Bus Idle Timeout
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

A bus idle timeout has no effect on the bus state.

1 : ENABLE

A bus idle timeout tells the I2C module that the bus is idle, allowing new transfers to be initiated.

End of enumeration elements list.

CLTO : Clock Low Timeout
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0 : OFF

Timeout disabled

1 : I2C40PCC

Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

2 : I2C80PCC

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

3 : I2C160PCC

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

4 : I2C320PCC

Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout.

5 : I2C1024PCC

Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout.

End of enumeration elements list.

SCLMONEN : SCL Monitor Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable SCL monitor

1 : ENABLE

Enable SCL monitor

End of enumeration elements list.

SDAMONEN : SDA Monitor Enable
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable SDA Monitor

1 : ENABLE

Enable SDA Monitor

End of enumeration elements list.


CMD

No Description
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP ACK NACK CONT ABORT CLEARTX CLEARPC

START : Send start condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send stop condition
bits : 1 - 1 (1 bit)
access : write-only

ACK : Send ACK
bits : 2 - 2 (1 bit)
access : write-only

NACK : Send NACK
bits : 3 - 3 (1 bit)
access : write-only

CONT : Continue transmission
bits : 4 - 4 (1 bit)
access : write-only

ABORT : Abort transmission
bits : 5 - 5 (1 bit)
access : write-only

CLEARTX : Clear TX
bits : 6 - 6 (1 bit)
access : write-only

CLEARPC : Clear Pending Commands
bits : 7 - 7 (1 bit)
access : write-only



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