\n

RAC_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

CMD

PATRIM1

PATRIM2

PACTRL

PGATRIM

PGACAL

PGACTRL

RFBIASCAL

RFBIASCTRL

RADIOEN

RFPATHEN1

RFPATHEN2

RX

TX

SYTRIM0

CTRL

SYTRIM1

SYCAL

SYEN

SYLOEN

SYMMDCTRL

DIGCLKRETIMECTRL

DIGCLKRETIMESTATUS

XORETIMECTRL

XORETIMESTATUS

XOSQBUFFILT

ANTDIV

FORCESTATE

IF

IEN

TESTCTRL

SEQSTATUS

SEQCMD

BREAKPOINT

R0

R1

R2

SCRATCH0

SCRATCH1

SCRATCH2

SCRATCH3

SCRATCH4

SCRATCH5

SCRATCH6

SCRATCH7

EN

R3

R4

R5

R6

R7

WAITMASK

WAITSNSH

STIMER

STIMERCOMP

VECTADDR

SEQCTRL

PRESC

SR0

SR1

SR2

SR3

RXENSRCEN

SYNTHENCTRL

SYNTHREGCTRL

VCOCTRL

SYNTHCTRL

STATUS2

IFPGACTRL

PAENCTRL

APC

AUXADCTRIM

AUXADCEN

AUXADCCTRL0

AUXADCCTRL1

AUXADCOUT

STATUS

CLKMULTEN0

CLKMULTEN1

CLKMULTCTRL

CLKMULTSTATUS

IFADCTRIM

IFADCCAL

IFADCSTATUS

LNAMIXTRIM0

LNAMIXTRIM1

LNAMIXTRIM2

LNAMIXCAL

LNAMIXEN

PRECTRL

PATRIM0


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only


CMD

No Description
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXEN FORCETX TXONCCA CLEARTXEN TXAFTERFRAME TXDIS CLEARRXOVERFLOW RXCAL RXDIS PAENSET PAENCLEAR LNAENSET LNAENCLEAR

TXEN : Transmitter Enable
bits : 0 - 0 (1 bit)
access : write-only

FORCETX : Force TX Command
bits : 1 - 1 (1 bit)
access : write-only

TXONCCA : Transmit On CCA
bits : 2 - 2 (1 bit)
access : write-only

CLEARTXEN : Clear TX Enable
bits : 3 - 3 (1 bit)
access : write-only

TXAFTERFRAME : TX After Frame
bits : 4 - 4 (1 bit)
access : write-only

TXDIS : TX Disable
bits : 5 - 5 (1 bit)
access : write-only

CLEARRXOVERFLOW : Clear RX Overflow
bits : 6 - 6 (1 bit)
access : write-only

RXCAL : Start an RX Calibration
bits : 7 - 7 (1 bit)
access : write-only

RXDIS : RX Disable
bits : 8 - 8 (1 bit)
access : write-only

PAENSET : PAEN Set
bits : 12 - 12 (1 bit)
access : write-only

PAENCLEAR : PAEN Clear
bits : 13 - 13 (1 bit)
access : write-only

LNAENSET : LNAEN Set
bits : 14 - 14 (1 bit)
access : write-only

LNAENCLEAR : LNAEN Clear
bits : 15 - 15 (1 bit)
access : write-only


PATRIM1


address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM1 PATRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PATRIM10DBMDUTYCYN PATRIM10DBMDUTYCYP PATRIM20DBMPREDRV PATRIMANTSWBIAS PATRIMBLEEDAUTOPREREG PATRIMCAPPAOUTM PATRIMCAPPAOUTP PATRIMCMGAIN PATRIMDLY0 PATRIMDLY1 PATRIMFBKATTPDRVLDO PATRIMIBIASMASTER

PATRIM10DBMDUTYCYN : PATRIM10DBMDUTYCYN
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : up_0pct


1 : up_1pct


2 : up_2pct


3 : up_3pct


4 : up_4pct


5 : up_5pct


6 : up_6pct


7 : na


End of enumeration elements list.

PATRIM10DBMDUTYCYP : PATRIM10DBMDUTYCYP
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

0 : dn_0pct


1 : dn_1pct


2 : dn_2pct


3 : dn_3pct


4 : dn_4pct


5 : dn_5pct


6 : dn_6pct


7 : na


End of enumeration elements list.

PATRIM20DBMPREDRV : PATRIM20DBMPREDRV
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0 : trise_137ps


1 : trise_127ps


2 : trise_117ps


3 : trise_110ps


4 : trise_75ps


5 : trise_73ps


6 : trise_71ps


7 : trise_70ps


End of enumeration elements list.

PATRIMANTSWBIAS : PATRIMANTSWBIAS
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : vb_at_vdd


1 : vb_at_vdd_mp6v


2 : vb_at_vdd_m1p2v


3 : vb_at_vdd_m1p8v


End of enumeration elements list.

PATRIMBLEEDAUTOPREREG : PATRIMBLEEDAUTOPREREG
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : not_automatic


1 : automatic


End of enumeration elements list.

PATRIMCAPPAOUTM : PATRIMCAPPAOUTM
bits : 12 - 15 (4 bit)
access : read-write

PATRIMCAPPAOUTP : PATRIMCAPPAOUTP
bits : 16 - 19 (4 bit)
access : read-write

PATRIMCMGAIN : PATRIMCMGAIN
bits : 20 - 21 (2 bit)
access : read-write

PATRIMDLY0 : PATRIMDLY0
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

0 : tdly_0ps


1 : tdly_64ps


2 : tdly_65ps


3 : tdly_66ps


4 : tdly_68ps


5 : tdly_70ps


6 : tdly_75ps


7 : tdly_83ps


End of enumeration elements list.

PATRIMDLY1 : PATRIMDLY1
bits : 25 - 27 (3 bit)
access : read-write

Enumeration:

0 : tdly_0ps


1 : tdly_64ps


2 : tdly_65ps


3 : tdly_66ps


4 : tdly_68ps


5 : tdly_70ps


6 : tdly_75ps


7 : tdly_83ps


End of enumeration elements list.

PATRIMFBKATTPDRVLDO : PATRIMFBKATTPDRVLDO
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : less_bw


1 : more_bw


End of enumeration elements list.

PATRIMIBIASMASTER : PATRIMIBIASMASTER
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : Ibias_is_45u


1 : Ibias_is_47p5u


2 : Ibias_is_50u


3 : Ibias_is_52p5u


End of enumeration elements list.


PATRIM2


address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM2 PATRIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PATRIMLDOFBHVPDRVLDO PATRIMLDOFBHVPREREG PATRIMLDOHVPDRVLDO PATRIMLDOHVPREREG PATRIMLDOPSRPDRVLDO PATRIMLDOPSRPREREG PATRIMLDOSLICESPDRVLDO PATRIMLDOSLICESPREREG PATRIMPADACGLITCH PATRIMNBIAS PATRIMNCASC PATRIMPBIAS PATRIMPCASC

PATRIMLDOFBHVPDRVLDO : PATRIMLDOFBHVPDRVLDO
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : vreg_1p22


1 : vreg_1p28


2 : vreg_1p35


3 : vreg_1p44


End of enumeration elements list.

PATRIMLDOFBHVPREREG : PATRIMLDOFBHVPREREG
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : vreg_1p678


1 : vreg_1p735


2 : vreg_1p801


3 : vreg_1p875


4 : vreg_3p00


5 : vreg_3p14


6 : vreg_3p3


7 : vreg_3p477


End of enumeration elements list.

PATRIMLDOHVPDRVLDO : PATRIMLDOHVPDRVLDO
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : vref_0p675


1 : vref_0p700


2 : vref_0p725


3 : vref_0p750


4 : vref_0p775


5 : vref_0p800


6 : vref_0p825


7 : vref_0p850


End of enumeration elements list.

PATRIMLDOHVPREREG : PATRIMLDOHVPREREG
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0 : vref_0p651


1 : vref_0p663


2 : vref_0p676


3 : vref_0p688


4 : vref_0p701


5 : vref_0p713


6 : vref_0p726


7 : vref_0p738


8 : vref_0p751


9 : vref_0p763


10 : vref_0p776


11 : vref_0p788


12 : vref_0p801


13 : vref_0p813


14 : vref_0p826


15 : vref_0p838


End of enumeration elements list.

PATRIMLDOPSRPDRVLDO : PATRIMLDOPSRPDRVLDO
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : low_psr


1 : high_psr


End of enumeration elements list.

PATRIMLDOPSRPREREG : PATRIMLDOPSRPREREG
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : low_psr


1 : high_psr


End of enumeration elements list.

PATRIMLDOSLICESPDRVLDO : PATRIMLDOSLICESPDRVLDO
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : iload_7p5mA


1 : iload_15mA


2 : iload_22p5mA


3 : iload_30mA


End of enumeration elements list.

PATRIMLDOSLICESPREREG : PATRIMLDOSLICESPREREG
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : spare1


1 : spare2


2 : spare3


3 : spare4


End of enumeration elements list.

PATRIMPADACGLITCH : PATRIMPADACGLITCH
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : larger_glitch


1 : smaller_glitch


End of enumeration elements list.

PATRIMNBIAS : PATRIMNBIAS
bits : 19 - 22 (4 bit)
access : read-write

Enumeration:

0 : vnbias_dn104mv


1 : vnbias_dn91mv


2 : vnbias_dn78mv


3 : vnbias_dn65mv


4 : vnbias_dn52mv


5 : vnbias_dn39mv


6 : vnbias_dn26mv


7 : vnbias_dn13mv


8 : vnbias_default


9 : vnbias_up13mv


10 : vnbias_up26mv


11 : vnbias_up39mv


12 : vnbias_up52mv


13 : vnbias_up65mv


14 : vnbias_up78mv


15 : vnbias_up91mv


End of enumeration elements list.

PATRIMNCASC : PATRIMNCASC
bits : 23 - 24 (2 bit)
access : read-write

Enumeration:

0 : ncbias_m50mv


1 : ncbias_default


2 : ncbias_p50mv


3 : ncbias_p100mv


End of enumeration elements list.

PATRIMPBIAS : PATRIMPBIAS
bits : 25 - 28 (4 bit)
access : read-write

Enumeration:

0 : vpbias_up104mv


1 : vpbias_up91mv


2 : vpbias_up78mv


3 : vpbias_up65mv


4 : vpbias_up52mv


5 : vpbias_up39mv


6 : vpbias_up26mv


7 : vpbias_up13mv


8 : vpbias_default


9 : vpbias_dn13mv


10 : vpbias_dn26mv


11 : vpbias_dn38mv


12 : vpbias_dn52mv


13 : vpbias_dn65mv


14 : vpbias_dn78mv


15 : vpbias_dn91mv


End of enumeration elements list.

PATRIMPCASC : PATRIMPCASC
bits : 29 - 30 (2 bit)
access : read-write

Enumeration:

0 : pcbias_p50mv


1 : pcbias_default


2 : pcbias_m50mv


3 : pcbias_m100mv


End of enumeration elements list.


PACTRL


address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PACTRL PACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAEN10DBMVMID PAEN20DBMVMID PAENCAPATT PAENLATCHBYPASS PAENPOWERRAMPINGCLK PAPULLDOWNVDDPA PAREGBYPASSPDRVLDO PAREGBYPASSPREREG PASELLDOVDDPA PASELLDOVDDRF PASLICERST PAPOWER PASELSLICE

PAEN10DBMVMID : PAEN10DBMVMID
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAEN20DBMVMID : PAEN20DBMVMID
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENCAPATT : PAENCAPATT
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENLATCHBYPASS : PAENLATCHBYPASS
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENPOWERRAMPINGCLK : PAENPOWERRAMPINGCLK
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : silence_clk


1 : en_clk


End of enumeration elements list.

PAPULLDOWNVDDPA : PAPULLDOWNVDDPA
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : not_pull_down


1 : pull_down_vddpa


End of enumeration elements list.

PAREGBYPASSPDRVLDO : PAREGBYPASSPDRVLDO
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : not_bypass


1 : bypass


End of enumeration elements list.

PAREGBYPASSPREREG : PAREGBYPASSPREREG
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : not_bypass


1 : bypass


End of enumeration elements list.

PASELLDOVDDPA : PASELLDOVDDPA
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : not_selected


1 : selected


End of enumeration elements list.

PASELLDOVDDRF : PASELLDOVDDRF
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : not_selected


1 : selected


End of enumeration elements list.

PASLICERST : PASLICERST
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAPOWER : PAPOWER
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : t0stripeon


1 : t1stripeon


2 : t2stripeon


3 : t3stripeon


4 : t4stripeon


5 : t5stripeon


6 : t6stripeon


7 : t7stripeon


8 : t8stripeon


9 : t9stripeon


10 : t10stripeon


11 : t11stripeon


12 : t12stripeon


13 : t13stripeon


14 : t14stripeon


15 : t15stripeon


End of enumeration elements list.

PASELSLICE : PASELSLICE
bits : 20 - 23 (4 bit)
access : read-write


PGATRIM


address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGATRIM PGATRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGACTUNE PGADISANTILOCK PGAVCMOUTTRIM PGAVLDOTRIM

PGACTUNE : PGACTUNE
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : cfb_0p7


7 : cfb_nominal


15 : cfb_1p32


End of enumeration elements list.

PGADISANTILOCK : PGADISANTILOCK
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : antilock_enable


1 : antilock_disable


End of enumeration elements list.

PGAVCMOUTTRIM : PGAVCMOUTTRIM
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : vcm_out_0p4


1 : vcm_out_0p45


2 : vcm_out_0p5


3 : vcm_out_0p55


4 : vcm_out_0p6


5 : vcm_out_0p65


6 : vcm_out_0p7


7 : vcm_out_0p75


End of enumeration elements list.

PGAVLDOTRIM : PGAVLDOTRIM
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : vdda_1p15


1 : vdda_1p2


2 : vdda_1p25


3 : vdda_1p3


4 : vdda_1p35


5 : vdda_1p4


6 : vdda_1p5


7 : vdda_1p55


End of enumeration elements list.


PGACAL


address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGACAL PGACAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGAOFFNCALI PGAOFFNCALQ PGAOFFPCALI PGAOFFPCALQ

PGAOFFNCALI : PGAOFFNCALI
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : offset_m_300mv


63 : offset_p_300mv


End of enumeration elements list.

PGAOFFNCALQ : PGAOFFNCALQ
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : offset_m_300mv


63 : offset_p_300mv


End of enumeration elements list.

PGAOFFPCALI : PGAOFFPCALI
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : offset_m_300mv


63 : offset_p_300mv


End of enumeration elements list.

PGAOFFPCALQ : PGAOFFPCALQ
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0 : offset_m_300mv


63 : offset_p_300mv


End of enumeration elements list.


PGACTRL


address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGACTRL PGACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGABWMODE PGAENBIAS PGAENGHZ PGAENHYST PGAENLATCHI PGAENLATCHQ PGAENLDOLOAD PGAENOFFD PGAENPGAI PGAENPGAQ PGAENPKD PGAENRCMOUT PGAPOWERMODE PGATHRPKDLOSEL PGATHRPKDHISEL LNAMIXRFPKDTHRESHSEL

PGABWMODE : PGABWMODE
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : bw_5MHz


1 : bw_2p5MHz


2 : bw_1p67MHz


3 : bw_1p25MHz


End of enumeration elements list.

PGAENBIAS : PGAENBIAS
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : bias_disable


1 : bias_enable


End of enumeration elements list.

PGAENGHZ : PGAENGHZ
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : ghz_disable


1 : ghz_enable


End of enumeration elements list.

PGAENHYST : PGAENHYST
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : pkd_hyst_disable


1 : pkd_hyst_enable


End of enumeration elements list.

PGAENLATCHI : PGAENLATCHI
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : pkd_latch_i_disable


1 : pkd_latch_i_enable


End of enumeration elements list.

PGAENLATCHQ : PGAENLATCHQ
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : pkd_latch_q_disable


1 : pkd_latch_q_enable


End of enumeration elements list.

PGAENLDOLOAD : PGAENLDOLOAD
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable_ldo_load


1 : enable_ldo_load


End of enumeration elements list.

PGAENOFFD : PGAENOFFD
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : pkd_offd_disable


1 : pkd_offd_enable


End of enumeration elements list.

PGAENPGAI : PGAENPGAI
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : pgai_disable


1 : pgai_enable


End of enumeration elements list.

PGAENPGAQ : PGAENPGAQ
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : pgaq_disable


1 : pgaq_enable


End of enumeration elements list.

PGAENPKD : PGAENPKD
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : pkd_disable


1 : pkd_enable


End of enumeration elements list.

PGAENRCMOUT : PGAENRCMOUT
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : rcm_out_disable


1 : rcm_out_enable


End of enumeration elements list.

PGAPOWERMODE : PGAPOWERMODE
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : pm_typ


1 : pm_0p8


2 : pm_1p2


3 : pm_0p5


End of enumeration elements list.

PGATHRPKDLOSEL : PGATHRPKDLOSEL
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : vref50mv


1 : vref75mv


2 : vref100mv


3 : vref125mv


4 : vref150mv


5 : vref175mv


6 : vref200mv


7 : vref225mv


8 : vref250mv


9 : vref275mv


10 : vref300mv


End of enumeration elements list.

PGATHRPKDHISEL : PGATHRPKDHISEL
bits : 20 - 23 (4 bit)
access : read-write

Enumeration:

0 : vref50mv


1 : vref75mv


2 : vref100mv


3 : vref125mv


4 : verf150mv


5 : vref175mv


6 : vref200mv


7 : vref225mv


8 : vref250mv


9 : vref275mv


10 : vref300mv


End of enumeration elements list.

LNAMIXRFPKDTHRESHSEL : LNAMIXRFPKDTHRESHSEL
bits : 24 - 26 (3 bit)
access : read-write


RFBIASCAL


address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFBIASCAL RFBIASCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFBIASCALBIAS RFBIASCALTC RFBIASCALVREF RFBIASCALVREFSTARTUP

RFBIASCALBIAS : RFBIASCALBIAS
bits : 0 - 5 (6 bit)
access : read-write

RFBIASCALTC : RFBIASCALTC
bits : 8 - 13 (6 bit)
access : read-write

RFBIASCALVREF : RFBIASCALVREF
bits : 16 - 21 (6 bit)
access : read-write

RFBIASCALVREFSTARTUP : RFBIASCALVREFSTARTUP
bits : 24 - 29 (6 bit)
access : read-write


RFBIASCTRL


address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFBIASCTRL RFBIASCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFBIASDISABLEBOOTSTRAP RFBIASLDOHIGHCURRENT RFBIASNONFLASHMODE RFBIASSTARTUPCORE RFBIASSTARTUPSUPPLY RFBIASLDOVREFTRIM

RFBIASDISABLEBOOTSTRAP : RFBIASDISABLEBOOTSTRAP
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : enable_startup


1 : disable_startup


End of enumeration elements list.

RFBIASLDOHIGHCURRENT : RFBIASLDOHIGHCURRENT
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : low_current


1 : high_current


End of enumeration elements list.

RFBIASNONFLASHMODE : RFBIASNONFLASHMODE
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : flash_process


1 : non_flash_process


End of enumeration elements list.

RFBIASSTARTUPCORE : RFBIASSTARTUPCORE
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : default


1 : force_start


End of enumeration elements list.

RFBIASSTARTUPSUPPLY : RFBIASSTARTUPSUPPLY
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : default


1 : forc_start


End of enumeration elements list.

RFBIASLDOVREFTRIM : RFBIASLDOVREFTRIM
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : vref_v0p800


1 : vref_v0p813


2 : vref_v0p825


3 : vref_v0p837


4 : vref_v0p850


5 : vref_v0p863


6 : vref_v0p875


7 : vref_v0p887


8 : vref_v0p900


9 : vref_v0p913


10 : vref_v0p925


11 : vref_v0p938


12 : vref_v0p950


13 : vref_v0p963


14 : vref_v0p975


15 : vref_v0p988


End of enumeration elements list.


RADIOEN


address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RADIOEN RADIOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREEN PRESTB100UDIS RFBIASEN

PREEN : PREEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : powered_off


1 : powered_on


End of enumeration elements list.

PRESTB100UDIS : PRESTB100UDIS
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : i100ua_enabled


1 : i100ua_disabled


End of enumeration elements list.

RFBIASEN : RFBIASEN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable_dualbis_vtr


1 : enable_dualbis_vtr


End of enumeration elements list.


RFPATHEN1

No Description
address_offset : 0x128 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFPATHEN1 RFPATHEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXEN0DBMPA1 LNAMIXEN1 LNAMIXRFATTDCEN1 LNAMIXRFPKDENRF1 LNAMIXTRSW1 PAENANT1 PAENPA10DBM PAENPAPREDRV10DBM

LNAMIXEN0DBMPA1 : LNAMIXEN0DBMPA1
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXEN1 : LNAMIXEN1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXRFATTDCEN1 : LNAMIXRFATTDCEN1
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable_dc


1 : enable_dc


End of enumeration elements list.

LNAMIXRFPKDENRF1 : LNAMIXRFPKDENRF1
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable_path1


End of enumeration elements list.

LNAMIXTRSW1 : LNAMIXTRSW1
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disabled


1 : enabled


End of enumeration elements list.

PAENANT1 : PAENANT1
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENPA10DBM : PAENPA10DBM
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENPAPREDRV10DBM : PAENPAPREDRV10DBM
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


RFPATHEN2

No Description
address_offset : 0x12C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFPATHEN2 RFPATHEN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXEN0DBMPA2 LNAMIXEN2 LNAMIXRFATTDCEN2 LNAMIXRFPKDENRF2 LNAMIXTRSW2 PAENANT2 PAENPA20DBM PAENPAPREDRV20DBM

LNAMIXEN0DBMPA2 : LNAMIXEN0DBMPA2
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXEN2 : LNAMIXEN2
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXRFATTDCEN2 : LNAMIXRFATTDCEN2
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXRFPKDENRF2 : LNAMIXRFPKDENRF2
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable_path2


End of enumeration elements list.

LNAMIXTRSW2 : LNAMIXTRSW2
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENANT2 : PAENANT2
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENPA20DBM : PAENPA20DBM
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENPAPREDRV20DBM : PAENPAPREDRV20DBM
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


RX


address_offset : 0x130 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCCAPRESET IFADCENLDOSERIES IFADCENLDOSHUNT LNAMIXENRFPKD LNAMIXLDOLOWCUR LNAMIXREGLOADEN PGAENLDO SYCHPBIASTRIMBUF SYCHPQNC3EN SYMMDMODE SYPFDCHPLPEN SYPFDFPWEN

IFADCCAPRESET : IFADCCAPRESET
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : cap_reset_disable


1 : cap_reset_enable


End of enumeration elements list.

IFADCENLDOSERIES : IFADCENLDOSERIES
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : series_ldo_disable


1 : series_ldo_enable


End of enumeration elements list.

IFADCENLDOSHUNT : IFADCENLDOSHUNT
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : shunt_ldo_disable


1 : shunt_ldo_enable


End of enumeration elements list.

LNAMIXENRFPKD : LNAMIXENRFPKD
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXLDOLOWCUR : LNAMIXLDOLOWCUR
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : regular_mode


1 : low_current_mode


End of enumeration elements list.

LNAMIXREGLOADEN : LNAMIXREGLOADEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable_resistor


1 : enable_resistor


End of enumeration elements list.

PGAENLDO : PGAENLDO
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable_ldo


1 : enable_ldo


End of enumeration elements list.

SYCHPBIASTRIMBUF : SYCHPBIASTRIMBUF
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : i_tail_10u


1 : i_tail_20u


End of enumeration elements list.

SYCHPQNC3EN : SYCHPQNC3EN
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : qnc_2


1 : qnc_3


End of enumeration elements list.

SYMMDMODE : SYMMDMODE
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : rx_w_swctrl


1 : rx_wo_swctrl


2 : qnc_dsm2


3 : qnc_dsm3


4 : rxlp_wo_swctrl


5 : notuse_5


6 : notuse_6


7 : notuse_7


End of enumeration elements list.

SYPFDCHPLPEN : SYPFDCHPLPEN
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYPFDFPWEN : SYPFDFPWEN
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


TX


address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX TX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PABLEEDDRVREG0DBM PABLEEDREG0DBM PAENBIAS0DBM PAENDRVREG0DBM PAENDRVREGBIAS0DBM PAENLO0DBM PAENREG0DBM PAENTAPCAP0DBM ENPATRIMPASLICE0DBM PAEN10DBMM PAEN10DBMP PAEN10DBMPDRV PAEN20DBM PAEN20DBMPDRV PAENBLEEDPDRVLDO PAENBLEEDPREREG PAENLDOHVPDRVLDO PAENLDOHVPREREG PAENPAOUT ENXOSQBUFFILT ENPAPOWER ENPASELSLICE

PABLEEDDRVREG0DBM : PABLEEDDRVREG0DBM
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PABLEEDREG0DBM : PABLEEDREG0DBM
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENBIAS0DBM : PAENBIAS0DBM
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENDRVREG0DBM : PAENDRVREG0DBM
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENDRVREGBIAS0DBM : PAENDRVREGBIAS0DBM
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENLO0DBM : PAENLO0DBM
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENREG0DBM : PAENREG0DBM
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENTAPCAP0DBM : PAENTAPCAP0DBM
bits : 7 - 9 (3 bit)
access : read-write

Enumeration:

0 : cap_0f


1 : cap_0p35pF


2 : cap_0p7pF


3 : cap_1p05pF


4 : cap_1p4pF


5 : cap_1p75pF


6 : cap_2p1pF


7 : cap_2p45pF


End of enumeration elements list.

ENPATRIMPASLICE0DBM : Override
bits : 10 - 10 (1 bit)
access : read-write

PAEN10DBMM : PAEN10DBMM
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAEN10DBMP : PAEN10DBMP
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAEN10DBMPDRV : PAEN10DBMPDRV
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAEN20DBM : PAEN20DBM
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAEN20DBMPDRV : PAEN20DBMPDRV
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENBLEEDPDRVLDO : PAENBLEEDPDRVLDO
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENBLEEDPREREG : PAENBLEEDPREREG
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENLDOHVPDRVLDO : PAENLDOHVPDRVLDO
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENLDOHVPREREG : PAENLDOHVPREREG
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PAENPAOUT : PAENPAOUT
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

ENXOSQBUFFILT : Override
bits : 29 - 29 (1 bit)
access : read-write

ENPAPOWER : Override
bits : 30 - 30 (1 bit)
access : read-write

ENPASELSLICE : Override
bits : 31 - 31 (1 bit)
access : read-write


SYTRIM0


address_offset : 0x13C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYTRIM0 SYTRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYCHPBIAS SYCHPCURR SYCHPLEVNSRC SYCHPLEVPSRC SYCHPSRCEN SYCHPREPLICACURRADJ SYTRIMCHPREGAMPBIAS SYTRIMCHPREGAMPBW

SYCHPBIAS : SYCHPBIAS
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : bias_0


1 : bias_1


3 : bias_2


7 : bias_3


End of enumeration elements list.

SYCHPCURR : SYCHPCURR
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

0 : curr_1p5uA


1 : curr_2p0uA


2 : curr_2p5uA


3 : curr_3p0uA


4 : curr_3p5uA


5 : curr_4p0uA


6 : curr_4p5uA


7 : curr_5p0uA


End of enumeration elements list.

SYCHPLEVNSRC : SYCHPLEVNSRC
bits : 6 - 8 (3 bit)
access : read-write

SYCHPLEVPSRC : SYCHPLEVPSRC
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : vsrcp_n105m


1 : vsrcp_n90m


2 : vsrcp_n75m


3 : vsrcp_n60m


4 : vsrcp_n45m


5 : vsrcp_n30m


6 : vsrcp_n15m


7 : vsrcp_n0m


End of enumeration elements list.

SYCHPSRCEN : SYCHPSRCEN
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPREPLICACURRADJ : SYCHPREPLICACURRADJ
bits : 14 - 16 (3 bit)
access : read-write

Enumeration:

0 : load_8ua


1 : load_16ua


2 : load_20ua


3 : load_28ua


4 : load_24ua


5 : load_32ua


6 : load_36ua


7 : load_44ua


End of enumeration elements list.

SYTRIMCHPREGAMPBIAS : SYTRIMCHPREGAMPBIAS
bits : 17 - 19 (3 bit)
access : read-write

Enumeration:

0 : bias_14uA


1 : bias_20uA


2 : bias_26uA


3 : bias_32uA


4 : bias_38uA


5 : bias_44uA


6 : bias_50uA


7 : bias_56uA


End of enumeration elements list.

SYTRIMCHPREGAMPBW : SYTRIMCHPREGAMPBW
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : C_000f


1 : C_300f


2 : C_600f


3 : C_900f


End of enumeration elements list.


CTRL

No Description
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCEDISABLE PRSTXEN TXAFTERRX PRSMODE PRSCLR TXPOSTPONE ACTIVEPOL PAENPOL LNAENPOL PRSRXDIS PRSFORCETX

FORCEDISABLE : Force Radio Disable
bits : 0 - 0 (1 bit)
access : read-write

PRSTXEN : PRS TX Enable
bits : 1 - 1 (1 bit)
access : read-write

TXAFTERRX : TX After RX
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : X0

TX will not be started automatically.

1 : X1

A transition to TX is automatically started when a received frame is accepted by the FRC.

End of enumeration elements list.

PRSMODE : PRS RXEN Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : DIRECT

The PRS signal is used directly

1 : PULSE

The PRS signal is used as an RX enable pulse

End of enumeration elements list.

PRSCLR : PRS RXEN Clear
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : RXSEARCH

The PRS RXEN signal is cleared when the RSM state enters RXSEARCH

1 : PRSCH

The Selected PRS channel in PRSCLRSEL is used as a disable pulse

End of enumeration elements list.

TXPOSTPONE : TX Postpone
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : X0

In the TX state transmit data is output.

1 : X1

In the TX state an unmodulated carrier is output until this bit is cleared.

End of enumeration elements list.

ACTIVEPOL : ACTIVE signal polarity
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : X0

Active low

1 : X1

Active high

End of enumeration elements list.

PAENPOL : PAEN signal polarity
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : X0

Active low

1 : X1

Active high

End of enumeration elements list.

LNAENPOL : LNAEN signal polarity
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : X0

Active low

1 : X1

Active high

End of enumeration elements list.

PRSRXDIS : PRS RX Disable
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : X0

PRS will not disable RX

1 : X1

The channel selected by PRSRXDISSEL will generate a disable RX pulse

End of enumeration elements list.

PRSFORCETX : PRS Force RX
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : X0

PRS will not force TX

1 : X1

The channel selected by PRSFORCETXSEL will generate a force TX pulse

End of enumeration elements list.


SYTRIM1


address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYTRIM1 SYTRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYLODIVLDOTRIMCORE SYLODIVLDOTRIMNDIO SYMMDREPLICA1CURRADJ SYMMDREPLICA2CURRADJ SYTRIMMMDREGAMPBIAS SYTRIMMMDREGAMPBW

SYLODIVLDOTRIMCORE : SYLODIVLDOTRIMCORE
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : RXLO


3 : TXLO


End of enumeration elements list.

SYLODIVLDOTRIMNDIO : SYLODIVLDOTRIMNDIO
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : vreg_1p08


1 : vreg_1p11


2 : vreg_1p15


3 : vreg_1p18


4 : vreg_1p21


5 : vreg_1p24


6 : vreg_1p27


7 : vreg_1p29


8 : vreg_1p32


9 : vreg_1p34


End of enumeration elements list.

SYMMDREPLICA1CURRADJ : SYMMDREPLICA1CURRADJ
bits : 6 - 8 (3 bit)
access : read-write

Enumeration:

0 : load_8ua


1 : load_16u


2 : load_20ua


3 : load_28ua


4 : load_24ua


5 : load_32ua


6 : load_36ua


7 : load_44ua


End of enumeration elements list.

SYMMDREPLICA2CURRADJ : SYMMDREPLICA2CURRADJ
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

0 : load_32u


1 : load_64u


2 : load_96u


3 : load_128u


4 : load_160u


5 : load_192u


6 : load_224u


7 : load_256u


End of enumeration elements list.

SYTRIMMMDREGAMPBIAS : SYTRIMMMDREGAMPBIAS
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

0 : bias_14uA


1 : bias_20uA


2 : bias_26uA


3 : bias_32uA


4 : bias_38uA


5 : bias_44uA


6 : bias_50uA


7 : bias_56uA


End of enumeration elements list.

SYTRIMMMDREGAMPBW : SYTRIMMMDREGAMPBW
bits : 15 - 16 (2 bit)
access : read-write

Enumeration:

0 : C_000f


1 : C_300f


2 : C_600f


3 : C_900f


End of enumeration elements list.


SYCAL


address_offset : 0x144 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYCAL SYCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYVCOMODEPKD SYVCOMORECURRENT SYVCOSLOWNOISEFILTER SYVCOVCAPVCM SYHILOADCHPREG

SYVCOMODEPKD : SYVCOMODEPKD
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : t_openloop_0


1 : t_pkdetect_1


End of enumeration elements list.

SYVCOMORECURRENT : SYVCOMORECURRENT
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : more_current_0


1 : more_current_1


End of enumeration elements list.

SYVCOSLOWNOISEFILTER : SYVCOSLOWNOISEFILTER
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : slow_noise_filter_0


1 : slow_noise_filter_1


End of enumeration elements list.

SYVCOVCAPVCM : SYVCOVCAPVCM
bits : 15 - 16 (2 bit)
access : read-write

SYHILOADCHPREG : SYHILOADCHPREG
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : i_350uA


1 : i_500uA


2 : i_550uA


3 : i_700uA


End of enumeration elements list.


SYEN


address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYEN SYEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYCHPEN SYCHPLPEN SYENCHPREG SYENCHPREPLICA SYENMMDREG SYENMMDREPLICA1 SYENMMDREPLICA2 SYENVCOBIAS SYENVCOPFET SYENVCOREG SYLODIVEN SYLODIVLDOBIASEN SYLODIVLDOEN SYSTARTCHPREG SYSTARTMMDREG

SYCHPEN : SYCHPEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYCHPLPEN : SYCHPLPEN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYENCHPREG : SYENCHPREG
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : Disable


1 : Enable


End of enumeration elements list.

SYENCHPREPLICA : SYENCHPREPLICA
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYENMMDREG : SYENMMDREG
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : Disable


1 : Enable


End of enumeration elements list.

SYENMMDREPLICA1 : SYENMMDREPLICA1
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYENMMDREPLICA2 : SYENMMDREPLICA2
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : Disable


1 : Enable


End of enumeration elements list.

SYENVCOBIAS : SYENVCOBIAS
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : en_vco_bias_0


1 : en_vco_bias_1


End of enumeration elements list.

SYENVCOPFET : SYENVCOPFET
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : en_vco_pfet_0


1 : en_vco_pfet_1


End of enumeration elements list.

SYENVCOREG : SYENVCOREG
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : en_vco_reg_0


1 : en_vco_reg_1


End of enumeration elements list.

SYLODIVEN : SYLODIVEN
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVLDOBIASEN : SYLODIVLDOBIASEN
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVLDOEN : SYLODIVLDOEN
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYSTARTCHPREG : SYSTARTCHPREG
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : no_fast_startup


1 : fast_startup


End of enumeration elements list.

SYSTARTMMDREG : SYSTARTMMDREG
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : no_fast_startup


1 : fast_startup


End of enumeration elements list.


SYLOEN


address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYLOEN SYLOEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYLODIVRLOADCCLK2G4EN SYLODIVRLO12G4EN SYLODIVRLO22G4EN SYLODIVTLO0DBM2G4AUXEN SYLODIVTLO0DBM2G4EN SYLODIVTLO20DBM2G4AUXEN SYLODIVTLO20DBM2G4EN

SYLODIVRLOADCCLK2G4EN : SYLODIVRLOADCCLK2G4EN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVRLO12G4EN : SYLODIVRLO12G4EN
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVRLO22G4EN : SYLODIVRLO22G4EN
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO0DBM2G4AUXEN : SYLODIVTLO0DBM2G4AUXEN
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO0DBM2G4EN : SYLODIVTLO0DBM2G4EN
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO20DBM2G4AUXEN : SYLODIVTLO20DBM2G4AUXEN
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYLODIVTLO20DBM2G4EN : SYLODIVTLO20DBM2G4EN
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


SYMMDCTRL


address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYMMDCTRL SYMMDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYMMDENRSDIG SYMMDDIVRSDIG

SYMMDENRSDIG : SYMMDENRSDIG
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

SYMMDDIVRSDIG : SYMMDDIVRSDIG
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : Divideby1


1 : Divideby2


2 : Divideby4


3 : Divideby8


End of enumeration elements list.


DIGCLKRETIMECTRL

No Description
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIGCLKRETIMECTRL DIGCLKRETIMECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGCLKRETIMEENRETIME DIGCLKRETIMEDISRETIME DIGCLKRETIMERESETN DIGCLKRETIMELIMITH DIGCLKRETIMELIMITL

DIGCLKRETIMEENRETIME : DIGCLKRETIMEENRETIME
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

DIGCLKRETIMEDISRETIME : DIGCLKRETIMEDISRETIME
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : enable_retime


1 : disable_retime


End of enumeration elements list.

DIGCLKRETIMERESETN : DIGCLKRETIMERESETN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : operate


1 : reset


End of enumeration elements list.

DIGCLKRETIMELIMITH : DIGCLKRETIMELIMITH
bits : 4 - 6 (3 bit)
access : read-write

DIGCLKRETIMELIMITL : DIGCLKRETIMELIMITL
bits : 8 - 10 (3 bit)
access : read-write


DIGCLKRETIMESTATUS

No Description
address_offset : 0x160 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIGCLKRETIMESTATUS DIGCLKRETIMESTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIGCLKRETIMECLKSEL DIGCLKRETIMERESETNLO

DIGCLKRETIMECLKSEL : DIGCLKRETIMECLKSEL
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : use_raw_clk


1 : use_retimed_clk


End of enumeration elements list.

DIGCLKRETIMERESETNLO : DIGCLKRETIMERESETNLO
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : lo


1 : hi


End of enumeration elements list.


XORETIMECTRL

No Description
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XORETIMECTRL XORETIMECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XORETIMEENRETIME XORETIMEDISRETIME XORETIMERESETN XORETIMELIMITH XORETIMELIMITL

XORETIMEENRETIME : XORETIMEENRETIME
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

XORETIMEDISRETIME : XORETIMEDISRETIME
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : enable_retime


1 : disable_retime


End of enumeration elements list.

XORETIMERESETN : XORETIMERESETN
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : operate


1 : reset


End of enumeration elements list.

XORETIMELIMITH : XORETIMELIMITH
bits : 4 - 6 (3 bit)
access : read-write

XORETIMELIMITL : XORETIMELIMITL
bits : 8 - 10 (3 bit)
access : read-write


XORETIMESTATUS

No Description
address_offset : 0x168 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

XORETIMESTATUS XORETIMESTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XORETIMECLKSEL XORETIMERESETNLO

XORETIMECLKSEL : XORETIMECLKSEL
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : use_raw_clk


1 : use_retimed_clk


End of enumeration elements list.

XORETIMERESETNLO : XORETIMERESETNLO
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : lo


1 : hi


End of enumeration elements list.


XOSQBUFFILT


address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSQBUFFILT XOSQBUFFILT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XOSQBUFFILT

XOSQBUFFILT : XOSQBUFFILT
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : bypass


1 : filter_1


2 : filter_2


3 : filter_3


End of enumeration elements list.


ANTDIV

No Description
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANTDIV ANTDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN STATUS

EN : EN
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : OFF

All controls off

1 : PAENANT1

Control pa_en_ant1

2 : LNAMIXEN1

Control lnamix_en1

4 : LNAMIXRFPKDENRF1

Control lnamix_rfpkd_en_rf1

8 : SYLODIVRLO12G4EN

Control sy_lodiv_rlo1_2g4_en

16 : PAENANT2

Control pa_en_ant2

32 : LNAMIXEN2

Control lnamix_en2

64 : LNAMIXRFPKDENRF2

Control lnamix_rfpkd_en_rf2

128 : SYLODIVRLO22G4EN

Control sy_lodiv_rlo2_2g4_en

255 : ON

All controls on

End of enumeration elements list.

STATUS : STATUS
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : OFF

Both antenna disabled

1 : ANT1

Antenna 1 enabled

2 : ANT2

Antenna 2 enabled

3 : BOTH

Both antenna enabled

End of enumeration elements list.


FORCESTATE

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FORCESTATE FORCESTATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCESTATE

FORCESTATE : Force RAC state transition
bits : 0 - 3 (4 bit)
access : read-write


IF

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATECHANGE STIMCMPEV BUSERROR SEQ

STATECHANGE : Radio State Change
bits : 0 - 0 (1 bit)
access : read-write

STIMCMPEV : STIMER Compare Event
bits : 1 - 1 (1 bit)
access : read-write

BUSERROR : Bus Error
bits : 2 - 2 (1 bit)
access : read-write

SEQ : Sequencer Interrupt Flags
bits : 16 - 23 (8 bit)
access : read-write


IEN

No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATECHANGE STIMCMPEV BUSERROR SEQ

STATECHANGE : Radio State Change Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

STIMCMPEV : STIMER Compare Event Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

BUSERROR : Bus Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

SEQ : Sequencer Flags Interrupt Enable
bits : 16 - 23 (8 bit)
access : read-write


TESTCTRL

No Description
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTCTRL TESTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEN DEMODEN AUX2RFSENSE LOOPBACK2LNAINPUT LOOPBACK2LNAOUTPUT

MODEN : Modulator enable
bits : 0 - 0 (1 bit)
access : read-write

DEMODEN : Demodulator enable
bits : 1 - 1 (1 bit)
access : read-write

AUX2RFSENSE : Enable auxiliary synthesizer output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : X0

The auxiliary synthesizer is not connected to the RFSENSE input

1 : X1

The auxiliary synthesizer is connected to the RFSENSE input

End of enumeration elements list.

LOOPBACK2LNAINPUT : Enable RF loopback
bits : 3 - 3 (1 bit)
access : read-write

LOOPBACK2LNAOUTPUT : Enable RF loopback
bits : 4 - 4 (1 bit)
access : read-write


SEQSTATUS

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SEQSTATUS SEQSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPED BKPT WAITING WAITMODE DONE NEG POS ZERO CARRY ABORTEN

STOPPED : Sequencer Stopped
bits : 0 - 0 (1 bit)
access : read-only

BKPT : Breakpoint Enabled
bits : 1 - 1 (1 bit)
access : read-only

WAITING : Sequencer Waiting
bits : 2 - 2 (1 bit)
access : read-only

WAITMODE : Sequencer Waiting Mode
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : ANY

Sequencer is waiting for any of the events indicated SEQ_WAITMASK.

1 : ALL

Sequencer is waiting for all the events indicated SEQ_WAITMASK.

End of enumeration elements list.

DONE : Sequencer Done Signal
bits : 4 - 4 (1 bit)
access : read-only

NEG : Negative Flag
bits : 5 - 5 (1 bit)
access : read-only

POS : Positive Flag
bits : 6 - 6 (1 bit)
access : read-only

ZERO : Zero Flag
bits : 7 - 7 (1 bit)
access : read-only

CARRY : Carry Flag
bits : 8 - 8 (1 bit)
access : read-only

ABORTEN : Sequencer Program Execution Abort Enable
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

0 : X0

Sequencer Program Execution can not be aborted.

1 : X1

Sequencer Program Execution can be aborted.

End of enumeration elements list.


SEQCMD

No Description
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SEQCMD SEQCMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HALT STEP RESUME BKPTEN BKPTDIS ABORT ABORTENSET ABORTENCLEAR

HALT : Sequencer Halt
bits : 0 - 0 (1 bit)
access : write-only

STEP : Sequencer Step
bits : 1 - 1 (1 bit)
access : write-only

RESUME : Sequencer Resume
bits : 2 - 2 (1 bit)
access : write-only

BKPTEN : Breakpoint Enable
bits : 3 - 3 (1 bit)
access : write-only

BKPTDIS : Breakpoint Disable
bits : 4 - 4 (1 bit)
access : write-only

ABORT : Sequencer Execution Abort
bits : 5 - 5 (1 bit)
access : write-only

ABORTENSET : Set Sequencer Abort Enable
bits : 6 - 6 (1 bit)
access : write-only

ABORTENCLEAR : Clear Sequencer Abort Enable
bits : 7 - 7 (1 bit)
access : write-only


BREAKPOINT

No Description
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREAKPOINT BREAKPOINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BKPADDR

BKPADDR : Sequencer Breakpoint Address
bits : 0 - 31 (32 bit)
access : read-write


R0

No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R0 R0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0

R0 : Sequencer Register 0
bits : 0 - 31 (32 bit)
access : read-write


R1

No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R1 R1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1

R1 : Sequencer Register 1
bits : 0 - 31 (32 bit)
access : read-write


R2

No Description
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R2 R2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R2

R2 : Sequencer Register 2
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH0

No Description
address_offset : 0x3E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH0 SCRATCH0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH0

SCRATCH0 : SCRATCH0
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH1

No Description
address_offset : 0x3E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH1 SCRATCH1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH1

SCRATCH1 : SCRATCH1
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH2

No Description
address_offset : 0x3E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH2 SCRATCH2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH2

SCRATCH2 : SCRATCH2
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH3

No Description
address_offset : 0x3EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH3 SCRATCH3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH3

SCRATCH3 : SCRATCH3
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH4

No Description
address_offset : 0x3F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH4 SCRATCH4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH4

SCRATCH4 : SCRATCH4
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH5

No Description
address_offset : 0x3F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH5 SCRATCH5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH5

SCRATCH5 : SCRATCH5
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH6

No Description
address_offset : 0x3F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH6 SCRATCH6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH6

SCRATCH6 : SCRATCH6
bits : 0 - 31 (32 bit)
access : read-write


SCRATCH7

No Description
address_offset : 0x3FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH7 SCRATCH7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCRATCH7

SCRATCH7 : SCRATCH7
bits : 0 - 31 (32 bit)
access : read-write


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write


R3

No Description
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R3 R3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R3

R3 : Sequencer Register 3
bits : 0 - 31 (32 bit)
access : read-write


R4

No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R4 R4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R4

R4 : Sequencer Register 4
bits : 0 - 31 (32 bit)
access : read-write


R5

No Description
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R5 R5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R5

R5 : Sequencer Register 5
bits : 0 - 31 (32 bit)
access : read-write


R6

No Description
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R6 R6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R6

R6 : Sequencer Register 6
bits : 0 - 31 (32 bit)
access : read-write


R7

No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R7 R7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R7

R7 : Sequencer Register 7
bits : 0 - 31 (32 bit)
access : read-write


WAITMASK

No Description
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WAITMASK WAITMASK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCMP FRCRX FRCTX PRSEVENT DEMODRXREQCLR SYNTHRDY RAMPDONE FRCPAUSED ANTSWITCH

STCMP : STIMER Compare Event
bits : 0 - 0 (1 bit)
access : read-only

FRCRX : FRC RXWord
bits : 1 - 1 (1 bit)
access : read-only

FRCTX : FRC TXWord
bits : 2 - 2 (1 bit)
access : read-only

PRSEVENT : PRS Event
bits : 3 - 3 (1 bit)
access : read-only

DEMODRXREQCLR : Demodulator RX Request Clear
bits : 4 - 4 (1 bit)
access : read-only

SYNTHRDY : SYNTH Ready
bits : 5 - 5 (1 bit)
access : read-only

RAMPDONE : Ramp Done
bits : 6 - 6 (1 bit)
access : read-only

FRCPAUSED : FRC Paused
bits : 7 - 7 (1 bit)
access : read-only

ANTSWITCH : Active antenna has switched
bits : 8 - 8 (1 bit)
access : read-only


WAITSNSH

No Description
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WAITSNSH WAITSNSH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITSNSH

WAITSNSH : Wait Event Snapshot
bits : 0 - 9 (10 bit)
access : read-only


STIMER

No Description
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STIMER STIMER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMER

STIMER : STIMER Register
bits : 0 - 15 (16 bit)
access : read-only


STIMERCOMP

No Description
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STIMERCOMP STIMERCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMERCOMP

STIMERCOMP : STIMER Compare Register
bits : 0 - 15 (16 bit)
access : read-write


VECTADDR

No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VECTADDR VECTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTADDR

VECTADDR : Vector Table Address
bits : 0 - 31 (32 bit)
access : read-write


SEQCTRL

No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEQCTRL SEQCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPACT COMPINVALMODE STIMERDEBUGRUN CPUHALTREQEN SEQHALTUPONCPUHALTEN

COMPACT : STIMER Compare Action
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : WRAP

STIMER wraps when reaching STIMERCOMP

1 : CONTINUE

STIMER continues when reaching STIMERCOMP

End of enumeration elements list.

COMPINVALMODE : STIMER Comp Invalid Mode
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : NEVER

STIMERCOMP is always valid

1 : STATECHANGE

STIMERCOMP is invalidated when the RSM changes state

2 : COMPEVENT

STIMERCOMP is invalidated when an STIMER compare event occurs

3 : STATECOMP

STIMERCOMP is invalidated both when the RSM changes state and when a compare event occurs

End of enumeration elements list.

STIMERDEBUGRUN : STIMER Debug Run
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : X0

STIMER is not running when the Sequencer is halted.

1 : X1

STIMER is running when the Sequencer is halted.

End of enumeration elements list.

CPUHALTREQEN : CPU Halt Request Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : X0

Main CPU is not halted when the Sequencer is halted.

1 : X1

Main CPU is halted when the Sequencer is halted.

End of enumeration elements list.

SEQHALTUPONCPUHALTEN : Sequencer Halt Upon CPU Halt Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : X0

Sequencer is not halted when the main CPU is halted.

1 : X1

Sequencer is halted when the main CPU is halted.

End of enumeration elements list.


PRESC

No Description
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESC PRESC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STIMER

STIMER : STIMER Prescaler
bits : 0 - 6 (7 bit)
access : read-write


SR0

No Description
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR0 SR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR0

SR0 : Sequencer Storage Register 0
bits : 0 - 31 (32 bit)
access : read-write


SR1

No Description
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR1 SR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR1

SR1 : Sequencer Storage Register 1
bits : 0 - 31 (32 bit)
access : read-write


SR2

No Description
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR2 SR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR2

SR2 : Sequencer Storage Register 2
bits : 0 - 31 (32 bit)
access : read-write


SR3

No Description
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR3 SR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR3

SR3 : Sequencer Storage Register 3
bits : 0 - 31 (32 bit)
access : read-write


RXENSRCEN

No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXENSRCEN RXENSRCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRXEN CHANNELBUSYEN TIMDETEN PREDETEN FRAMEDETEN DEMODRXREQEN PRSRXEN

SWRXEN : SW RX Enable
bits : 0 - 7 (8 bit)
access : read-write

CHANNELBUSYEN : Channel Busy Enable
bits : 8 - 8 (1 bit)
access : read-write

TIMDETEN : Timing Detected Enable
bits : 9 - 9 (1 bit)
access : read-write

PREDETEN : Preamble Detected Enable
bits : 10 - 10 (1 bit)
access : read-write

FRAMEDETEN : Frame Detected Enable
bits : 11 - 11 (1 bit)
access : read-write

DEMODRXREQEN : DEMOD RX Request Enable
bits : 12 - 12 (1 bit)
access : read-write

PRSRXEN : PRS RX Enable
bits : 13 - 13 (1 bit)
access : read-write


SYNTHENCTRL

No Description
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNTHENCTRL SYNTHENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCOSTARTUP VCBUFEN LPFBWSEL

VCOSTARTUP : SYVCOFASTSTARTUP
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : fast_start_up_0


1 : fast_start_up_1


End of enumeration elements list.

VCBUFEN : SYLPFVCBUFEN
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

LPFBWSEL : LPF bandwidth register selection
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : LPFBWRX

Select LPFBWRX

1 : LPFBWTX

Select LPFBWTX

End of enumeration elements list.


SYNTHREGCTRL

No Description
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNTHREGCTRL SYNTHREGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMDLDOVREFTRIM CHPLDOVREFTRIM

MMDLDOVREFTRIM : SYTRIMMMDREGVREF
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0 : vref0p6000


1 : vref0p6125


2 : vref0p6250


3 : vref0p6375


4 : vref0p6500


5 : vref0p6625


6 : vref0p6750


7 : vref0p6875


End of enumeration elements list.

CHPLDOVREFTRIM : SYTRIMCHPREGVREF
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : vref0p6000


1 : vref0p6125


2 : vref0p6250


3 : vref0p6375


4 : vref0p6500


5 : vref0p6625


6 : vref0p6750


7 : vref0p6875


End of enumeration elements list.


VCOCTRL

No Description
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCOCTRL VCOCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VCOAMPLITUDE VCODETAMPLITUDE

VCOAMPLITUDE : SYVCOAMPLOPEN
bits : 0 - 3 (4 bit)
access : read-write

VCODETAMPLITUDE : SYVCOAMPLPKD
bits : 4 - 7 (4 bit)
access : read-write


SYNTHCTRL

No Description
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNTHCTRL SYNTHCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MMDPOWERBALANCEDISABLE

MMDPOWERBALANCEDISABLE : SYMMDPOWERBALANCEENB
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : EnablePowerbleed


1 : DisablePowerBleed


End of enumeration elements list.


STATUS2

No Description
address_offset : 0x9C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS2 STATUS2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREVSTATE1 PREVSTATE2 PREVSTATE3

PREVSTATE1 : Previous Radio State
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

End of enumeration elements list.

PREVSTATE2 : Previous Radio State 2
bits : 4 - 7 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

End of enumeration elements list.

PREVSTATE3 : Previous Radio State 3
bits : 8 - 11 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

End of enumeration elements list.


IFPGACTRL

No Description
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFPGACTRL IFPGACTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCCALON DCRSTEN DCESTIEN DCCALDEC0 DCCALDCGEAR

DCCALON : Enable/Disable DCCAL in DEMOD
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

DC ESTI DISABLED

1 : ENABLE

DC ESTI ENABLED

End of enumeration elements list.

DCRSTEN : DC Compensation Filter Reset Enable
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

DC Comp out of Reset

1 : ENABLE

DC Comp in Reset

End of enumeration elements list.

DCESTIEN : DCESTIEN Override for RAC
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

DCESTI Disabled in MODEM

1 : ENABLE

DCESTI Enabled in MODEM

End of enumeration elements list.

DCCALDEC0 : DEC0 Value for DCCAL
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

0 : DF3

Decimation Factor 0 = 3. Cutoff 0.050 * fHFXO.

1 : DF4WIDE

Decimation Factor 0 = 4. Cutoff 0.069 * fHFXO.

2 : DF4NARROW

Decimation Factor 0 = 4. Cutoff 0.037 * fHFXO.

3 : DF8WIDE

Decimation Factor 0 = 8. Cutoff 0.012 * fHFXO.

4 : DF8NARROW

Decimation Factor 0 = 8. Cutoff 0.005 * fHFXO.

End of enumeration elements list.

DCCALDCGEAR : DC COMP GEAR Value for DCCAL
bits : 25 - 27 (3 bit)
access : read-write


PAENCTRL

No Description
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PAENCTRL PAENCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARAMP

PARAMP : PA output level ramping
bits : 8 - 8 (1 bit)
access : read-write


APC

No Description
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APC APC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENAPCSW AMPCONTROLLIMITSW

ENAPCSW : software control bit for apc
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : DISABLE


1 : ENABLE


End of enumeration elements list.

AMPCONTROLLIMITSW : software amp_control top limit
bits : 24 - 31 (8 bit)
access : read-write


AUXADCTRIM


address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCTRIM AUXADCTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCCLKINVERT AUXADCLDOVREFTRIM AUXADCOUTPUTINVERT AUXADCRCTUNE AUXADCTRIMADCINPUTRES AUXADCTRIMCURRINPUTBUF AUXADCTRIMCURROPA1 AUXADCTRIMCURROPA2 AUXADCTRIMCURRREFBUF AUXADCTRIMCURRTSENSE AUXADCTRIMCURRVCMBUF AUXADCTRIMLDOHIGHCURRENT AUXADCTRIMREFP AUXADCTRIMVREFVCM AUXADCTSENSETRIMVBE2

AUXADCCLKINVERT : AUXADCCLKINVERT
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disable_Invert


1 : Enable_Invert


End of enumeration elements list.

AUXADCLDOVREFTRIM : AUXADCLDOVREFTRIM
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

0 : TRIM1p27


1 : TRIM1p3


2 : TRIM1p35


3 : TRIM1p4


End of enumeration elements list.

AUXADCOUTPUTINVERT : AUXADCOUTPUTINVERT
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCRCTUNE : AUXADCRCTUNE
bits : 4 - 8 (5 bit)
access : read-write

AUXADCTRIMADCINPUTRES : AUXADCTRIMADCINPUTRES
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : RES200k


1 : RES250k


2 : RES300k


3 : RES350k


End of enumeration elements list.

AUXADCTRIMCURRINPUTBUF : AUXADCTRIMCURRINPUTBUF
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURROPA1 : AUXADCTRIMCURROPA1
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURROPA2 : AUXADCTRIMCURROPA2
bits : 15 - 16 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURRREFBUF : AUXADCTRIMCURRREFBUF
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURRTSENSE : AUXADCTRIMCURRTSENSE
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMCURRVCMBUF : AUXADCTRIMCURRVCMBUF
bits : 21 - 22 (2 bit)
access : read-write

Enumeration:

0 : Typ_minus_40pct


1 : Typ_minus_20pct


2 : Typ


3 : Typ_plus_20pct


End of enumeration elements list.

AUXADCTRIMLDOHIGHCURRENT : AUXADCTRIMLDOHIGHCURRENT
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : LowCurrentMode


1 : HighCurrentMode


End of enumeration elements list.

AUXADCTRIMREFP : AUXADCTRIMREFP
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : REF1p05


1 : REF1p16


2 : REF1p2


3 : REF1p25


End of enumeration elements list.

AUXADCTRIMVREFVCM : AUXADCTRIMVREFVCM
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : Trim0p6


1 : Trim0p65


2 : Trim0p7


3 : Trim0p75


End of enumeration elements list.

AUXADCTSENSETRIMVBE2 : AUXADCTSENSETRIMVBE2
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

0 : VBE_16uA


1 : VBE_32uA


End of enumeration elements list.


AUXADCEN


address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCEN AUXADCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCENAUXADC AUXADCENINPUTBUFFER AUXADCENLDO AUXADCENOUTPUTDRV AUXADCENPMON AUXADCENRESONDIAGA AUXADCENTSENSE AUXADCENTSENSECAL AUXADCINPUTBUFFERBYPASS

AUXADCENAUXADC : AUXADCENAUXADC
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENINPUTBUFFER : AUXADCENINPUTBUFFER
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENLDO : AUXADCENLDO
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENOUTPUTDRV : AUXADCENOUTPUTDRV
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENPMON : AUXADCENPMON
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENRESONDIAGA : AUXADCENRESONDIAGA
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENTSENSE : AUXADCENTSENSE
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCENTSENSECAL : AUXADCENTSENSECAL
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : Disabled


1 : Enabled


End of enumeration elements list.

AUXADCINPUTBUFFERBYPASS : AUXADCINPUTBUFFERBYPASS
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : Not_Bypassed


1 : Bypassed


End of enumeration elements list.


AUXADCCTRL0

No Description
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCCTRL0 AUXADCCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYCLES MUXSEL CLRCOUNTER CLRFILTER INPUTRESSEL

CYCLES : Cycle number to run
bits : 0 - 9 (10 bit)
access : read-write

MUXSEL : Select accumulator
bits : 10 - 11 (2 bit)
access : read-write

CLRCOUNTER : Clear counter
bits : 12 - 12 (1 bit)
access : read-write

CLRFILTER : Clear accumulators
bits : 13 - 13 (1 bit)
access : read-write

INPUTRESSEL : Select input resource
bits : 14 - 17 (4 bit)
access : read-write


AUXADCCTRL1


address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXADCCTRL1 AUXADCCTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCINPUTRESSEL AUXADCINPUTSELECT AUXADCPMONSELECT AUXADCTSENSESELCURR AUXADCRESET AUXADCTSENSESELVBE

AUXADCINPUTRESSEL : AUXADCINPUTRESSEL
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : RES640kOhm


1 : RES320kOhm


2 : RES160kOhm


3 : RES80kOhm


4 : RES40kOhm


5 : RES20kOhm


6 : RES10kOhm


7 : RES5kOhm


8 : RES2p5kOhm


9 : RES1p25kOhm


10 : RES0p6kOhm


11 : RES_switch


End of enumeration elements list.

AUXADCINPUTSELECT : AUXADCINPUTSELECT
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0 : SEL0


1 : SEL1


2 : SEL2


3 : SEL3


4 : SEL4


5 : SEL5


6 : SEL6


7 : SEL7


8 : SEL8


9 : SEL9


End of enumeration elements list.

AUXADCPMONSELECT : AUXADCPMONSELECT
bits : 8 - 11 (4 bit)
access : read-write

AUXADCTSENSESELCURR : AUXADCTSENSESELCURR
bits : 16 - 20 (5 bit)
access : read-write

AUXADCRESET : AUXADCRESET
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : Reset_Enabled


1 : Reset_Disabled


End of enumeration elements list.

AUXADCTSENSESELVBE : AUXADCTSENSESELVBE
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : VBE1


1 : VBE2


End of enumeration elements list.


AUXADCOUT

No Description
address_offset : 0xBC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AUXADCOUT AUXADCOUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXADCOUT

AUXADCOUT : AUXADC output
bits : 0 - 27 (28 bit)
access : read-only


STATUS

No Description
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXMASK FORCESTATEACTIVE TXAFTERFRAMEPEND TXAFTERFRAMEACTIVE STATE TXENS RXENS

RXMASK : Receive Enable Mask
bits : 0 - 15 (16 bit)
access : read-only

FORCESTATEACTIVE : FSM state force active
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

0 : X0

No special state transition is currently in progress

1 : X1

A forced state transition is currently in progress

End of enumeration elements list.

TXAFTERFRAMEPEND : TX After Frame Pending
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

0 : X0

A transmit after frame operation is currently not pending.

1 : X1

A transmit after frame operation is currently pending.

End of enumeration elements list.

TXAFTERFRAMEACTIVE : TX After Frame Active
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

0 : X0

The currently ongoing TX was not initiated by a TXAFTERFRAME command.

1 : X1

The currently ongoing TX was initiated by a TXAFTERFRAME command.

End of enumeration elements list.

STATE : Radio State
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

0 : OFF

Radio is off

1 : RXWARM

Radio is enabling receiver

2 : RXSEARCH

Radio is listening for incoming frames

3 : RXFRAME

Radio is receiving a frame

4 : RXPD

Radio is powering down receiver and going to OFF state

5 : RX2RX

Radio remains in receive mode after frame reception is completed

6 : RXOVERFLOW

Received data was lost due to full receive buffer

7 : RX2TX

Radio is disabling receiver and enabling transmitter

8 : TXWARM

Radio is enabling transmitter

9 : TX

Radio is transmitting data

10 : TXPD

Radio is powering down transmitter and going to OFF state

11 : TX2RX

Radio is disabling transmitter and enabling reception

12 : TX2TX

Radio is preparing for a transmission after the previous transmission was ended

13 : SHUTDOWN

Radio is powering down receiver and going to OFF state

End of enumeration elements list.

TXENS : TXEN Status
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : X0

TXEN is not set.

1 : X1

TXEN is set.

End of enumeration elements list.

RXENS : RXEN Status
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : X0

RXEN is not set.

1 : X1

RXEN is set.

End of enumeration elements list.


CLKMULTEN0


address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKMULTEN0 CLKMULTEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTBWCAL CLKMULTDISICO CLKMULTENBBDET CLKMULTENBBXLDET CLKMULTENBBXMDET CLKMULTENCFDET CLKMULTENDITHER CLKMULTENDRVADC CLKMULTENDRVDIFF CLKMULTENDRVRX2P4G CLKMULTENFBDIV CLKMULTENREFDIV CLKMULTENREG1 CLKMULTENREG2 CLKMULTENROTDET CLKMULTFREQCAL CLKMULTREG1ADJV CLKMULTREG2ADJI CLKMULTREG2ADJV

CLKMULTBWCAL : CLKMULTBWCAL
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : bw_1lsb


1 : bw_2lsb


2 : bw_3lsb


3 : bw_4lsb


End of enumeration elements list.

CLKMULTDISICO : CLKMULTDISICO
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : enable


1 : disable


End of enumeration elements list.

CLKMULTENBBDET : CLKMULTENBBDET
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENBBXLDET : CLKMULTENBBXLDET
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENBBXMDET : CLKMULTENBBXMDET
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENCFDET : CLKMULTENCFDET
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDITHER : CLKMULTENDITHER
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDRVADC : CLKMULTENDRVADC
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENDRVDIFF : CLKMULTENDRVDIFF
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : Single_ended


1 : Differential


End of enumeration elements list.

CLKMULTENDRVRX2P4G : CLKMULTENDRVRX2P4G
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENFBDIV : CLKMULTENFBDIV
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREFDIV : CLKMULTENREFDIV
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREG1 : CLKMULTENREG1
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENREG2 : CLKMULTENREG2
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTENROTDET : CLKMULTENROTDET
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTFREQCAL : CLKMULTFREQCAL
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0 : pedes_14uA


1 : pedes_22uA


2 : pedes_30uA


3 : pedes_38uA


End of enumeration elements list.

CLKMULTREG1ADJV : CLKMULTREG1ADJV
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : v1p28


1 : v1p32


2 : v1p33


3 : v1p38


End of enumeration elements list.

CLKMULTREG2ADJI : CLKMULTREG2ADJI
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

0 : I_200uA


1 : I_480uA


2 : I_760uA


3 : I_1040uA


End of enumeration elements list.

CLKMULTREG2ADJV : CLKMULTREG2ADJV
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : v1p03


1 : v1p09


2 : v1p10


3 : v1p16


End of enumeration elements list.


CLKMULTEN1


address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKMULTEN1 CLKMULTEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTINNIBBLE CLKMULTLDCNIB CLKMULTLDFNIB CLKMULTLDMNIB CLKMULTRDNIBBLE

CLKMULTINNIBBLE : CLKMULTINNIBBLE
bits : 0 - 3 (4 bit)
access : read-write

CLKMULTLDCNIB : CLKMULTLDCNIB
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTLDFNIB : CLKMULTLDFNIB
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTLDMNIB : CLKMULTLDMNIB
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

CLKMULTRDNIBBLE : CLKMULTRDNIBBLE
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : quarter_nibble


1 : fine_nibble


2 : moderate_nibble


3 : coarse_nibble


End of enumeration elements list.


CLKMULTCTRL


address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKMULTCTRL CLKMULTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTDIVN CLKMULTDIVR CLKMULTDIVX CLKMULTENRESYNC CLKMULTVALID

CLKMULTDIVN : CLKMULTDIVN
bits : 0 - 6 (7 bit)
access : read-write

CLKMULTDIVR : CLKMULTDIVR
bits : 7 - 9 (3 bit)
access : read-write

CLKMULTDIVX : CLKMULTDIVX
bits : 10 - 12 (3 bit)
access : read-write

Enumeration:

0 : div_1


1 : div_2


2 : div_4


3 : div_6


4 : div_8


5 : div10


6 : div12


7 : div14


End of enumeration elements list.

CLKMULTENRESYNC : CLKMULTENRESYNC
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : disable_sync


1 : enable_sync


End of enumeration elements list.

CLKMULTVALID : CLKMULTVALID
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : invalid


1 : valid


End of enumeration elements list.


CLKMULTSTATUS


address_offset : 0xCC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CLKMULTSTATUS CLKMULTSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKMULTOUTNIBBLE CLKMULTACKVALID

CLKMULTOUTNIBBLE : CLKMULTOUTNIBBLE
bits : 0 - 3 (4 bit)
access : read-only

CLKMULTACKVALID : CLKMULTACKVALID
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : invalid


1 : valid


End of enumeration elements list.


IFADCTRIM


address_offset : 0xD4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFADCTRIM IFADCTRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCCLKSEL IFADCENHALFMODE IFADCLDOSERIESAMPLVL IFADCLDOSHUNTAMPLVL IFADCLDOSHUNTCURLP IFADCLDOSHUNTCURLVL IFADCOTAST1CURRENT IFADCOTAST2CURRENT IFADCREFBUFAMPLVL IFADCREFBUFCURLVL IFADCSIDETONEAMP IFADCSIDETONEFREQ IFADCTUNEZERO IFADCVCMLVL

IFADCCLKSEL : IFADCCLKSEL
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : clk_2p4g


1 : clk_subg


End of enumeration elements list.

IFADCENHALFMODE : IFADCENHALFMODE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : full_speed_mode


1 : half_speed_mode


End of enumeration elements list.

IFADCLDOSERIESAMPLVL : IFADCLDOSERIESAMPLVL
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0 : v1p20


1 : v1p24


2 : v1p28


3 : v1p32


4 : v1p35


5 : v1p39


6 : v1p42


7 : v1p46


End of enumeration elements list.

IFADCLDOSHUNTAMPLVL : IFADCLDOSHUNTAMPLVL
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : v1p20


1 : v1p24


2 : v1p28


3 : v1p32


4 : v1p35


5 : v1p39


6 : v1p42


7 : v1p46


End of enumeration elements list.

IFADCLDOSHUNTCURLP : IFADCLDOSHUNTCURLP
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : low_power_disabled


1 : low_power_enabled


End of enumeration elements list.

IFADCLDOSHUNTCURLVL : IFADCLDOSHUNTCURLVL
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : current_180uA


1 : current_190uA


2 : current_200uA


3 : current_210uA


End of enumeration elements list.

IFADCOTAST1CURRENT : IFADCOTAST1CURRENT
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : negative_20p


1 : negative_11p


2 : nominal


3 : positive_15p


End of enumeration elements list.

IFADCOTAST2CURRENT : IFADCOTAST2CURRENT
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

0 : negative_20p


1 : negative_11p


2 : nominal


3 : positive_15p


End of enumeration elements list.

IFADCREFBUFAMPLVL : IFADCREFBUFAMPLVL
bits : 15 - 17 (3 bit)
access : read-write

Enumeration:

0 : v0p88


1 : v0p91


2 : v0p94


3 : v0p97


4 : v1p00


5 : v1p03


6 : v1p06


7 : v1p09


End of enumeration elements list.

IFADCREFBUFCURLVL : IFADCREFBUFCURLVL
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0 : current_65uA


1 : current_75uA


2 : current_85uA


3 : current_95uA


End of enumeration elements list.

IFADCSIDETONEAMP : IFADCSIDETONEAMP
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

0 : diff_pk_10mV


1 : diff_pk_20mV


2 : diff_pk_50mV


3 : diff_pk_100mV


End of enumeration elements list.

IFADCSIDETONEFREQ : IFADCSIDETONEFREQ
bits : 22 - 24 (3 bit)
access : read-write

Enumeration:

0 : na0


1 : div_128


2 : div_64


3 : div_32


4 : div_16


5 : div_8


6 : div_4


7 : na7


End of enumeration elements list.

IFADCTUNEZERO : IFADCTUNEZERO
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : nominal_zero


1 : half_freq_zero


End of enumeration elements list.

IFADCVCMLVL : IFADCVCMLVL
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : ratio_0p48


1 : ratio_0p49


2 : ratio_0p5


3 : ratio_0p52


End of enumeration elements list.


IFADCCAL


address_offset : 0xD8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFADCCAL IFADCCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCENRCCAL IFADCTUNERCCALMODE IFADCTUNERC

IFADCENRCCAL : IFADCENRCCAL
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : rccal_disable


1 : rccal_enable


End of enumeration elements list.

IFADCTUNERCCALMODE : IFADCTUNERCCALMODE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : SYmode


1 : ADCmode


End of enumeration elements list.

IFADCTUNERC : IFADCTUNERC
bits : 8 - 12 (5 bit)
access : read-write


IFADCSTATUS


address_offset : 0xDC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IFADCSTATUS IFADCSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFADCRCCALOUT

IFADCRCCALOUT : IFADCRCCALOUT
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : lo


1 : hi


End of enumeration elements list.


LNAMIXTRIM0


address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM0 LNAMIXTRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXCURCTRL LNAMIXHIGHCUR LNAMIXLOWCUR LNAMIXRFPKDBWSEL LNAMIXRFPKDCALCM LNAMIXRFPKDCALDM LNAMIXTRIMVREG

LNAMIXCURCTRL : LNAMIXCURCTRL
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXHIGHCUR : LNAMIXHIGHCUR
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0 : current_470uA


1 : current_530uA


2 : unused


3 : current_590uA


End of enumeration elements list.

LNAMIXLOWCUR : LNAMIXLOWCUR
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : current_nom


1 : unused


2 : current_80percent


3 : current_60percent


End of enumeration elements list.

LNAMIXRFPKDBWSEL : LNAMIXRFPKDBWSEL
bits : 10 - 11 (2 bit)
access : read-write

LNAMIXRFPKDCALCM : LNAMIXRFPKDCALCM
bits : 12 - 17 (6 bit)
access : read-write

LNAMIXRFPKDCALDM : LNAMIXRFPKDCALDM
bits : 18 - 22 (5 bit)
access : read-write

LNAMIXTRIMVREG : LNAMIXTRIMVREG
bits : 23 - 26 (4 bit)
access : read-write


LNAMIXTRIM1


address_offset : 0xE8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM1 LNAMIXTRIM1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXIBIAS1ADJ LNAMIXLNA1CAPSEL LNAMIXMXRBIAS1 LNAMIXNCAS1ADJ LNAMIXPCAS1ADJ LNAMIXVOUT1ADJ

LNAMIXIBIAS1ADJ : LNAMIXIBIAS1ADJ
bits : 0 - 3 (4 bit)
access : read-write

LNAMIXLNA1CAPSEL : LNAMIXLNA1CAPSEL
bits : 4 - 6 (3 bit)
access : read-write

LNAMIXMXRBIAS1 : LNAMIXMXRBIAS1
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : bias_1V


1 : unused


2 : bias_900m


3 : bias_800m


End of enumeration elements list.

LNAMIXNCAS1ADJ : LNAMIXNCAS1ADJ
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : ncas_1V


1 : unused


2 : ncas_950m


3 : ncas_900m


End of enumeration elements list.

LNAMIXPCAS1ADJ : LNAMIXPCAS1ADJ
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : pcas_250m


1 : unused


2 : pcas_300m


3 : pcas_350m


End of enumeration elements list.

LNAMIXVOUT1ADJ : LNAMIXVOUT1ADJ
bits : 13 - 16 (4 bit)
access : read-write


LNAMIXTRIM2

No Description
address_offset : 0xEC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXTRIM2 LNAMIXTRIM2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXIBIAS2ADJ LNAMIXLNA2CAPSEL LNAMIXMXRBIAS2 LNAMIXNCAS2ADJ LNAMIXPCAS2ADJ LNAMIXVOUT2ADJ

LNAMIXIBIAS2ADJ : LNAMIXIBIAS2ADJ
bits : 0 - 3 (4 bit)
access : read-write

LNAMIXLNA2CAPSEL : LNAMIXLNA2CAPSEL
bits : 4 - 6 (3 bit)
access : read-write

LNAMIXMXRBIAS2 : LNAMIXMXRBIAS2
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : bias_1V


1 : unused


2 : bias_900m


3 : bias_800m


End of enumeration elements list.

LNAMIXNCAS2ADJ : LNAMIXNCAS2ADJ
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : ncas_1V


1 : unused


2 : ncas_950m


3 : ncas_900m


End of enumeration elements list.

LNAMIXPCAS2ADJ : LNAMIXPCAS2ADJ
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0 : pcas_250m


1 : unused


2 : pcas_300m


3 : pcas_350m


End of enumeration elements list.

LNAMIXVOUT2ADJ : LNAMIXVOUT2ADJ
bits : 13 - 16 (4 bit)
access : read-write


LNAMIXCAL


address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXCAL LNAMIXCAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXCALEN LNAMIXCALVMODE LNAMIXENIRCAL1 LNAMIXENIRCAL2 LNAMIXIRCAL1AMP LNAMIXIRCAL2AMP

LNAMIXCALEN : LNAMIXCALEN
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : cal_disable


1 : cal_enable


End of enumeration elements list.

LNAMIXCALVMODE : LNAMIXCALVMODE
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : current_mode


1 : voltage_mode


End of enumeration elements list.

LNAMIXENIRCAL1 : LNAMIXENIRCAL1
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXENIRCAL2 : LNAMIXENIRCAL2
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

LNAMIXIRCAL1AMP : LNAMIXIRCAL1AMP
bits : 4 - 6 (3 bit)
access : read-write

LNAMIXIRCAL2AMP : LNAMIXIRCAL2AMP
bits : 7 - 9 (3 bit)
access : read-write


LNAMIXEN


address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXEN LNAMIXEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXENLDO

LNAMIXENLDO : LNAMIXENLDO
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.


PRECTRL


address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRECTRL PRECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREBYPFORCE PREREGTRIM PREVREFTRIM

PREBYPFORCE : PREBYPFORCE
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : not_forced


1 : forced


End of enumeration elements list.

PREREGTRIM : PREREGTRIM
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

0 : v1p61


1 : v1p68


2 : v1p74


3 : v1p80


4 : v1p86


5 : v1p91


6 : v1p96


7 : v2p00


End of enumeration elements list.

PREVREFTRIM : PREVREFTRIM
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : v0p675


1 : v0p688


2 : v0p700


3 : v0p713


End of enumeration elements list.


PATRIM0


address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PATRIM0 PATRIM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PATRIMDRVREGIBCORE0DBM PATRIMDRVREGIBNDIO0DBM PATRIMDRVREGPSR0DBM PATRIMDRVSLICE0DBM PATRIMFB0DBM PATRIMPABIASN0DBM PATRIMPABIASP0DBM PATRIMPASLICE0DBM PATRIMVREF0DBM

PATRIMDRVREGIBCORE0DBM : PATRIMDRVREGIBCORE0DBM
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : i_4u


1 : i_5u


2 : i_6u


3 : i_7u


End of enumeration elements list.

PATRIMDRVREGIBNDIO0DBM : PATRIMDRVREGIBNDIO0DBM
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

0 : vreg_1p09


1 : vreg_1p13


2 : vreg_1p16


3 : vreg_1p20


4 : vreg_1p23


5 : vreg_1p25


6 : vreg_1p28


7 : vreg_1p31


8 : vreg_1p33


9 : vreg_1p36


10 : NA_10


11 : NA_11


12 : NA_12


13 : NA_13


14 : NA_14


15 : NA_15


End of enumeration elements list.

PATRIMDRVREGPSR0DBM : PATRIMDRVREGPSR0DBM
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : disable


1 : enable


End of enumeration elements list.

PATRIMDRVSLICE0DBM : PATRIMDRVSLICE0DBM
bits : 7 - 8 (2 bit)
access : read-write

Enumeration:

0 : on_0_slice


1 : on_1_slice


2 : on_2_slice


3 : on_3_slice


End of enumeration elements list.

PATRIMFB0DBM : PATRIMFB0DBM
bits : 9 - 12 (4 bit)
access : read-write

Enumeration:

0 : vo_vi_0p475


1 : vo_vi_0p500


2 : vo_vi_0p525


3 : vo_vi_0p550


4 : vo_vi_0p575


5 : vo_vi_0p600


6 : vo_vi_0p625


7 : vo_vi_0p650


8 : vo_vi_0p675


9 : vo_vi_0p700


10 : vo_vi_0p725


11 : vo_vi_0p750


12 : vo_vi_0p775


13 : vo_vi_0p80


14 : vo_vi_0p825


15 : vo_vi_0p85


End of enumeration elements list.

PATRIMPABIASN0DBM : PATRIMPABIASN0DBM
bits : 13 - 16 (4 bit)
access : read-write

Enumeration:

0 : v_450m


1 : v_462p5m


2 : v_475m


3 : v_487p5m


4 : v_500m


5 : v_512p5m


6 : v_525m


7 : v_537p5m


8 : v_550m


9 : v_562p5m


10 : v_575m


11 : v_587p5m


12 : v_600m


13 : v_612p5m


14 : v_625m


15 : v_637p5m


End of enumeration elements list.

PATRIMPABIASP0DBM : PATRIMPABIASP0DBM
bits : 17 - 20 (4 bit)
access : read-write

Enumeration:

0 : v_450m


1 : v_462p5m


2 : v_475m


3 : v_487p5m


4 : v_500m


5 : v_512p5m


6 : v_525m


7 : v_537p5m


8 : v_550m


9 : v_562p5m


10 : v_575m


11 : v_587p5m


12 : v_600m


13 : v_612p5m


14 : v_625m


15 : v_637p5m


End of enumeration elements list.

PATRIMPASLICE0DBM : PATRIMPASLICE0DBM
bits : 21 - 26 (6 bit)
access : read-write

Enumeration:

0 : on_slice_0


63 : on_slice_63


End of enumeration elements list.

PATRIMVREF0DBM : PATRIMVREF0DBM
bits : 27 - 29 (3 bit)
access : read-write

Enumeration:

0 : v_900m


1 : v_912p5m


2 : v_925m


3 : v_937p5m


4 : v_950m


5 : v_962p5m


6 : v_975m


7 : v_987p5m


End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.