Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP version ID
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATABITS : Data-Bit Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
1 : SEVEN
Each frame contains 7 data bits
2 : EIGHT
Each frame contains 8 data bits
3 : NINE
Each frame contains 9 data bits
End of enumeration elements list.
PARITY : Parity-Bit Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : NONE
Parity bits are not used
2 : EVEN
Even parity are used. Parity bits are automatically generated and checked by hardware.
3 : ODD
Odd parity is used. Parity bits are automatically generated and checked by hardware.
End of enumeration elements list.
STOPBITS : Stop-Bit Mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : HALF
The transmitter generates a half stop bit. Stop-bits are not verified by receiver
1 : ONE
One stop bit is generated and verified
2 : ONEANDAHALF
The transmitter generates one and a half stop bit. The receiver verifies the first stop bit
3 : TWO
The transmitter generates two stop bits. The receiver checks the first stop-bit only
End of enumeration elements list.
No Description
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRHFEN : Enable IrDA Module
bits : 0 - 0 (1 bit)
access : read-write
IRHFPW : IrDA TX Pulse Width
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : ONE
IrDA pulse width is 1/16 for OVS=0 and 1/8 for OVS=1
1 : TWO
IrDA pulse width is 2/16 for OVS=0 and 2/8 for OVS=1
2 : THREE
IrDA pulse width is 3/16 for OVS=0 and 3/8 for OVS=1
3 : FOUR
IrDA pulse width is 4/16 for OVS=0 and 4/8 for OVS=1
End of enumeration elements list.
IRHFFILT : IrDA RX Filter
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
No filter enabled
1 : ENABLE
Filter enabled. IrDA pulse must be high for at least 4 consecutive clock cycles to be detected
End of enumeration elements list.
No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRLFEN : Pulse Generator/Extender Enable
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDELAY : TX Delay Transmission
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : NONE
Frames are transmitted immediately.
1 : SINGLE
Transmission of new frames is delayed by a single bit period.
2 : DOUBLE
Transmission of new frames is delayed by a two bit periods.
3 : TRIPPLE
Transmission of new frames is delayed by a three bit periods.
End of enumeration elements list.
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTFRAME : Start Frame
bits : 0 - 8 (9 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIGFRAME : Signal Frame Value
bits : 0 - 8 (9 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV : Fractional Clock Divider
bits : 3 - 22 (20 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receive Trigger Enable
bits : 0 - 0 (1 bit)
access : read-write
TXTEN : Transmit Trigger Enable
bits : 1 - 1 (1 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXEN : Receiver Enable
bits : 0 - 0 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 1 - 1 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 2 - 2 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 3 - 3 (1 bit)
access : write-only
RXBLOCKEN : Receiver Block Enable
bits : 4 - 4 (1 bit)
access : write-only
RXBLOCKDIS : Receiver Block Disable
bits : 5 - 5 (1 bit)
access : write-only
TXTRIEN : Transmitter Tristate Enable
bits : 6 - 6 (1 bit)
access : write-only
TXTRIDIS : Transmitter Tristate Disable
bits : 7 - 7 (1 bit)
access : write-only
CLEARTX : Clear TX FIFO
bits : 8 - 8 (1 bit)
access : write-only
No Description
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : RX Data
bits : 0 - 8 (9 bit)
access : read-only
PERR : Parity Error
bits : 9 - 9 (1 bit)
access : read-only
FERR : Framing Error
bits : 10 - 10 (1 bit)
access : read-only
No Description
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATAP : RX Data Peek
bits : 0 - 8 (9 bit)
access : read-only
PERRP : Parity Error Peek
bits : 9 - 9 (1 bit)
access : read-only
FERRP : Framing Error Peek
bits : 10 - 10 (1 bit)
access : read-only
No Description
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : TX Data
bits : 0 - 8 (9 bit)
access : write-only
UBRXAT : Unblock RX After Transmission
bits : 9 - 9 (1 bit)
access : write-only
TXTRIAT : Set TXTRI After Transmisssion
bits : 10 - 10 (1 bit)
access : write-only
TXBREAK : Transit Data as Break
bits : 11 - 11 (1 bit)
access : write-only
TXDISAT : Clear TXEN After Transmission
bits : 12 - 12 (1 bit)
access : write-only
RXENAT : Enable RXEN After Transmission
bits : 13 - 13 (1 bit)
access : write-only
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Module enable
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXENS : Receiver Enable Status
bits : 0 - 0 (1 bit)
access : read-only
TXENS : Transmitter Enable Status
bits : 1 - 1 (1 bit)
access : read-only
RXBLOCK : Block Incoming Data
bits : 3 - 3 (1 bit)
access : read-only
TXTRI : Transmitter Tristated
bits : 4 - 4 (1 bit)
access : read-only
TXC : TX Complete
bits : 5 - 5 (1 bit)
access : read-only
TXFL : TX FIFO Level
bits : 6 - 6 (1 bit)
access : read-only
RXFL : RX FIFO Level
bits : 7 - 7 (1 bit)
access : read-only
RXFULL : RX FIFO Full
bits : 8 - 8 (1 bit)
access : read-only
RXIDLE : RX Idle
bits : 12 - 12 (1 bit)
access : read-only
TXIDLE : TX Idle
bits : 13 - 13 (1 bit)
access : read-only
TXFCNT : Valid entries in TX FIFO
bits : 16 - 18 (3 bit)
access : read-only
CLEARTXBUSY : TX FIFO Clear Busy
bits : 19 - 19 (1 bit)
access : read-only
AUTOBAUDDONE : Auto Baud Rate Detection Completed
bits : 24 - 24 (1 bit)
access : read-only
No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCIF : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
TXC : TX Complete Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
TXFLIF : TX FIFO Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
TXFL : TX FIFO Level Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
RXFLIF : RX FIFO Level Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
RXFL : RX FIFO Level Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
RXFULLIF : RX FIFO Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
RXFULL : RX FIFO Full Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
RXOFIF : RX FIFO Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
RXOF : RX FIFO Overflow Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
RXUFIF : RX FIFO Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
RXUF : RX FIFO Underflow Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
TXOFIF : TX FIFO Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
TXOF : TX FIFO Overflow Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write
PERRIF : Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
PERR : Parity Error Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
FERRIF : Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
FERR : Framing Error Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
MPAFIF : Multi-Processor Address Frame Interrupt
bits : 10 - 10 (1 bit)
access : read-write
MPAF : Multi-Processor Address Frame Interrupt
bits : 10 - 10 (1 bit)
access : read-write
CCFIF : Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write
CCF : Collision Check Fail Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write
TXIDLEIF : TX Idle Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write
TXIDLE : TX Idle Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write
STARTFIF : Start Frame Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write
STARTF : Start Frame Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write
SIGFIF : Signal Frame Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-write
SIGF : Signal Frame Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-write
AUTOBAUDDONEIF : Auto Baud Complete Interrupt Flag
bits : 24 - 24 (1 bit)
access : read-write
AUTOBAUDDONE : Auto Baud Complete Interrupt Flag
bits : 24 - 24 (1 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCIEN : TX Complete IEN
bits : 0 - 0 (1 bit)
access : read-write
TXC : TX Complete IEN
bits : 0 - 0 (1 bit)
access : read-write
TXFLIEN : TX FIFO Level IEN
bits : 1 - 1 (1 bit)
access : read-write
TXFL : TX FIFO Level IEN
bits : 1 - 1 (1 bit)
access : read-write
RXFLIEN : RX FIFO Level IEN
bits : 2 - 2 (1 bit)
access : read-write
RXFL : RX FIFO Level IEN
bits : 2 - 2 (1 bit)
access : read-write
RXFULLIEN : RX FIFO Full IEN
bits : 3 - 3 (1 bit)
access : read-write
RXFULL : RX FIFO Full IEN
bits : 3 - 3 (1 bit)
access : read-write
RXOFIEN : RX FIFO Overflow IEN
bits : 4 - 4 (1 bit)
access : read-write
RXOF : RX FIFO Overflow IEN
bits : 4 - 4 (1 bit)
access : read-write
RXUFIEN : RX FIFO Underflow IEN
bits : 5 - 5 (1 bit)
access : read-write
RXUF : RX FIFO Underflow IEN
bits : 5 - 5 (1 bit)
access : read-write
TXOFIEN : TX FIFO Overflow IEN
bits : 6 - 6 (1 bit)
access : read-write
TXOF : TX FIFO Overflow IEN
bits : 6 - 6 (1 bit)
access : read-write
PERRIEN : Parity Error IEN
bits : 8 - 8 (1 bit)
access : read-write
PERR : Parity Error IEN
bits : 8 - 8 (1 bit)
access : read-write
FERRIEN : Framing Error IEN
bits : 9 - 9 (1 bit)
access : read-write
FERR : Framing Error IEN
bits : 9 - 9 (1 bit)
access : read-write
MPAFIEN : Multi-Processor Addr Frame IEN
bits : 10 - 10 (1 bit)
access : read-write
MPAF : Multi-Processor Addr Frame IEN
bits : 10 - 10 (1 bit)
access : read-write
CCFIEN : Collision Check Fail IEN
bits : 12 - 12 (1 bit)
access : read-write
CCF : Collision Check Fail IEN
bits : 12 - 12 (1 bit)
access : read-write
TXIDLEIEN : TX IDLE IEN
bits : 13 - 13 (1 bit)
access : read-write
TXIDLE : TX IDLE IEN
bits : 13 - 13 (1 bit)
access : read-write
STARTFIEN : Start Frame IEN
bits : 18 - 18 (1 bit)
access : read-write
STARTF : Start Frame IEN
bits : 18 - 18 (1 bit)
access : read-write
SIGFIEN : Signal Frame IEN
bits : 19 - 19 (1 bit)
access : read-write
SIGF : Signal Frame IEN
bits : 19 - 19 (1 bit)
access : read-write
AUTOBAUDDONEIEN : Auto Baud Complete IEN
bits : 24 - 24 (1 bit)
access : read-write
AUTOBAUDDONE : Auto Baud Complete IEN
bits : 24 - 24 (1 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DIV : SYNCBUSY for DIV in CLKDIV
bits : 0 - 0 (1 bit)
access : read-only
RXTEN : SYNCBUSY for RXTEN in TRIGCTRL
bits : 1 - 1 (1 bit)
access : read-only
TXTEN : SYNCBUSY for TXTEN in TRIGCTRL
bits : 2 - 2 (1 bit)
access : read-only
RXEN : SYNCBUSY for RXEN in CMD
bits : 3 - 3 (1 bit)
access : read-only
RXDIS : SYNCBUSY for RXDIS in CMD
bits : 4 - 4 (1 bit)
access : read-only
TXEN : SYNCBUSY for TXEN in CMD
bits : 5 - 5 (1 bit)
access : read-only
TXDIS : SYNCBUSY for TXDIS in CMD
bits : 6 - 6 (1 bit)
access : read-only
RXBLOCKEN : SYNCBUSY for RXBLOCKEN in CMD
bits : 7 - 7 (1 bit)
access : read-only
RXBLOCKDIS : SYNCBUSY for RXBLOCKDIS in CMD
bits : 8 - 8 (1 bit)
access : read-only
TXTRIEN : SYNCBUSY for TXTRIEN in CMD
bits : 9 - 9 (1 bit)
access : read-only
TXTRIDIS : SYNCBUSY in TXTRIDIS in CMD
bits : 10 - 10 (1 bit)
access : read-only
No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOOPBK : Loopback Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The receiver is connected to and receives data from UARTn_RX
1 : ENABLE
The receiver is connected to and receives data from UARTn_TX
End of enumeration elements list.
CCEN : Collision Check Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Collision check is disabled
1 : ENABLE
Collision check is enabled. The receiver must be enabled for the check to be performed
End of enumeration elements list.
MPM : Multi-Processor Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The 9th bit of incoming frames has no special function
1 : ENABLE
An incoming frame with the 9th bit equal to MPAB will be loaded into the RX FIFO regardless of RXBLOCK and will result in the MPAB interrupt flag being set
End of enumeration elements list.
MPAB : Multi-Processor Address-Bit
bits : 4 - 4 (1 bit)
access : read-write
OVS : Oversampling
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
0 : X16
16X oversampling
1 : X8
8X oversampling
2 : X6
6X oversampling
3 : X4
4X oversampling
4 : DISABLE
Disable oversampling (for LF operation)
End of enumeration elements list.
MSBF : Most Significant Bit First
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Data is sent with the least significant bit first
1 : ENABLE
Data is sent with the most significant bit first
End of enumeration elements list.
RXINV : Receiver Input Invert
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Input is passed directly to the receiver
1 : ENABLE
Input is inverted before it is passed to the receiver
End of enumeration elements list.
TXINV : Transmitter output Invert
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Output from the transmitter is passed unchanged to UARTn_TX
1 : ENABLE
Output from the transmitter is inverted before it is passed to UARTn_TX
End of enumeration elements list.
AUTOTRI : Automatic TX Tristate
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The output on UARTn_TX when the transmitter is idle is defined by TXINV
1 : ENABLE
UARTn_TX is tristated whenever the transmitter is idle
End of enumeration elements list.
SKIPPERRF : Skip Parity Error Frames
bits : 20 - 20 (1 bit)
access : read-write
ERRSDMA : Halt DMA Read On Error
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Framing and parity errors have no effect on DMA requests from the UART
1 : ENABLE
DMA requests from the UART are blocked while the PERR or FERR interrupt flags are set
End of enumeration elements list.
ERRSRX : Disable RX On Error
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Framing and parity errors have no effect on receiver
1 : ENABLE
Framing and parity errors disable the receiver
End of enumeration elements list.
ERRSTX : Disable TX On Error
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Received framing and parity errors have no effect on transmitter
1 : ENABLE
Received framing and parity errors disable the transmitter
End of enumeration elements list.
MVDIS : Majority Vote Disable
bits : 30 - 30 (1 bit)
access : read-write
AUTOBAUDEN : AUTOBAUD detection enable
bits : 31 - 31 (1 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGHALT : Debug halt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Continue normal UART operation even if core is halted
1 : ENABLE
If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping.
End of enumeration elements list.
CTSINV : Clear-to-send Invert Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The CTS pin is active low
1 : ENABLE
The CTS pin is active high
End of enumeration elements list.
CTSEN : Clear-to-send Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Ignore CTS
1 : ENABLE
Stop transmitting when CTS is inactive
End of enumeration elements list.
RTSINV : Request-to-send Invert Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The RTS pin is active low
1 : ENABLE
The RTS pin is active high
End of enumeration elements list.
TXDMAWU : Transmitter DMA Wakeup
bits : 9 - 9 (1 bit)
access : read-write
RXDMAWU : Receiver DMA Wakeup
bits : 10 - 10 (1 bit)
access : read-write
SFUBRX : Start Frame Unblock Receiver
bits : 11 - 11 (1 bit)
access : read-write
RXPRSEN : PRS RX Enable
bits : 15 - 15 (1 bit)
access : read-write
TXFIW : TX FIFO Interrupt Watermark
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : ONEFRAME
TXFL status flag and IF are set when the TX FIFO has space for at least one more frame.
1 : TWOFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least two more frames.
2 : THREEFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least three more frames.
3 : FOURFRAMES
TXFL status flag and IF are set when the TX FIFO has space for at least four more frames.
End of enumeration elements list.
RXFIW : RX FIFO Interrupt Watermark
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0 : ONEFRAME
RXFL status flag and IF are set when the RX FIFO has at least one frame in it.
1 : TWOFRAMES
RXFL status flag and IF are set when the RX FIFO has at least two frames in it.
2 : THREEFRAMES
RXFL status flag and IF are set when the RX FIFO has at least three frames in it.
3 : FOURFRAMES
RXFL status flag and IF are set when the RX FIFO has four frames in it.
End of enumeration elements list.
RTSRXFW : Request-to-send RX FIFO Watermark
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : ONEFRAME
RTS is set if there is space for at least one more frame in the RX FIFO.
1 : TWOFRAMES
RTS is set if there is space for at least two more frames in the RX FIFO.
2 : THREEFRAMES
RTS is set if there is space for at least three more frames in the RX FIFO.
3 : FOURFRAMES
RTS is set if there is space for four more frames in the RX FIFO.
End of enumeration elements list.
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