\n

I2C1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CLKDIV

SADDR

SADDRMASK

RXDATA

RXDOUBLE

RXDATAP

RXDOUBLEP

TXDATA

TXDOUBLE

IF

IFS

IFC

CMD

IEN

ROUTEPEN

ROUTELOC0

STATE

STATUS


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SLAVE AUTOACK AUTOSE AUTOSN ARBDIS GCAMEN TXBIL CLHR BITO GIBITO CLTO

EN : I2C Enable
bits : 0 - 0 (1 bit)
access : read-write

SLAVE : Addressable as Slave
bits : 1 - 1 (1 bit)
access : read-write

AUTOACK : Automatic Acknowledge
bits : 2 - 2 (1 bit)
access : read-write

AUTOSE : Automatic STOP When Empty
bits : 3 - 3 (1 bit)
access : read-write

AUTOSN : Automatic STOP on NACK
bits : 4 - 4 (1 bit)
access : read-write

ARBDIS : Arbitration Disable
bits : 5 - 5 (1 bit)
access : read-write

GCAMEN : General Call Address Match Enable
bits : 6 - 6 (1 bit)
access : read-write

TXBIL : TX Buffer Interrupt Level
bits : 7 - 7 (1 bit)
access : read-write

CLHR : Clock Low High Ratio
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x00000000 : STANDARD

The ratio between low period and high period counters (Nlow:Nhigh) is 4:4

0x00000001 : ASYMMETRIC

The ratio between low period and high period counters (Nlow:Nhigh) is 6:3

0x00000002 : FAST

The ratio between low period and high period counters (Nlow:Nhigh) is 11:6

End of enumeration elements list.

BITO : Bus Idle Timeout
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Timeout disabled

0x00000001 : 40PCC

Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

0x00000002 : 80PCC

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

0x00000003 : 160PCC

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

End of enumeration elements list.

GIBITO : Go Idle on Bus Idle Timeout
bits : 15 - 15 (1 bit)
access : read-write

CLTO : Clock Low Timeout
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x00000000 : OFF

Timeout disabled

0x00000001 : 40PCC

Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

0x00000002 : 80PCC

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

0x00000003 : 160PCC

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

0x00000004 : 320PCC

Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout.

0x00000005 : 1024PCC

Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout.

End of enumeration elements list.


CLKDIV

Clock Division Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock Divider
bits : 0 - 8 (9 bit)
access : read-write


SADDR

Slave Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR SADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Slave Address
bits : 1 - 7 (7 bit)
access : read-write


SADDRMASK

Slave Address Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDRMASK SADDRMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Slave Address Mask
bits : 1 - 7 (7 bit)
access : read-write


RXDATA

Receive Buffer Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATA RXDATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLE

Receive Buffer Double Data Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLE RXDOUBLE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA0 RXDATA1

RXDATA0 : RX Data 0
bits : 0 - 7 (8 bit)
access : read-only

RXDATA1 : RX Data 1
bits : 8 - 15 (8 bit)
access : read-only


RXDATAP

Receive Buffer Data Peek Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDATAP RXDATAP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP

RXDATAP : RX Data Peek
bits : 0 - 7 (8 bit)
access : read-only


RXDOUBLEP

Receive Buffer Double Data Peek Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXDOUBLEP RXDOUBLEP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP0 RXDATAP1

RXDATAP0 : RX Data 0 Peek
bits : 0 - 7 (8 bit)
access : read-only

RXDATAP1 : RX Data 1 Peek
bits : 8 - 15 (8 bit)
access : read-only


TXDATA

Transmit Buffer Data Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDATA TXDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7 (8 bit)
access : read-write


TXDOUBLE

Transmit Buffer Double Data Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDOUBLE TXDOUBLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA0 TXDATA1

TXDATA0 : TX Data
bits : 0 - 7 (8 bit)
access : read-write

TXDATA1 : TX Data
bits : 8 - 15 (8 bit)
access : read-write


IF

Interrupt Flag Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC TXBL RXDATAV ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP RXFULL CLERR

START : START Condition Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

RSTART : Repeated START Condition Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only

ADDR : Address Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-only

TXC : Transfer Completed Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-only

TXBL : Transmit Buffer Level Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-only

RXDATAV : Receive Data Valid Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-only

ACK : Acknowledge Received Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-only

NACK : Not Acknowledge Received Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-only

MSTOP : Master STOP Condition Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-only

ARBLOST : Arbitration Lost Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-only

BUSERR : Bus Error Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-only

BUSHOLD : Bus Held Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-only

TXOF : Transmit Buffer Overflow Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-only

RXUF : Receive Buffer Underflow Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-only

BITO : Bus Idle Timeout Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-only

CLTO : Clock Low Timeout Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-only

SSTOP : Slave STOP Condition Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-only

RXFULL : Receive Buffer Full Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-only

CLERR : Clock Low Error Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP RXFULL CLERR

START : Set START Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

RSTART : Set RSTART Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

ADDR : Set ADDR Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

TXC : Set TXC Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

ACK : Set ACK Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

NACK : Set NACK Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

MSTOP : Set MSTOP Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

ARBLOST : Set ARBLOST Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

BUSERR : Set BUSERR Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

BUSHOLD : Set BUSHOLD Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

TXOF : Set TXOF Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only

RXUF : Set RXUF Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only

BITO : Set BITO Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

CLTO : Set CLTO Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

SSTOP : Set SSTOP Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

RXFULL : Set RXFULL Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

CLERR : Set CLERR Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP RXFULL CLERR

START : Clear START Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

RSTART : Clear RSTART Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

ADDR : Clear ADDR Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

TXC : Clear TXC Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

ACK : Clear ACK Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

NACK : Clear NACK Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

MSTOP : Clear MSTOP Interrupt Flag
bits : 8 - 8 (1 bit)
access : write-only

ARBLOST : Clear ARBLOST Interrupt Flag
bits : 9 - 9 (1 bit)
access : write-only

BUSERR : Clear BUSERR Interrupt Flag
bits : 10 - 10 (1 bit)
access : write-only

BUSHOLD : Clear BUSHOLD Interrupt Flag
bits : 11 - 11 (1 bit)
access : write-only

TXOF : Clear TXOF Interrupt Flag
bits : 12 - 12 (1 bit)
access : write-only

RXUF : Clear RXUF Interrupt Flag
bits : 13 - 13 (1 bit)
access : write-only

BITO : Clear BITO Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

CLTO : Clear CLTO Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

SSTOP : Clear SSTOP Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

RXFULL : Clear RXFULL Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

CLERR : Clear CLERR Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP ACK NACK CONT ABORT CLEARTX CLEARPC

START : Send Start Condition
bits : 0 - 0 (1 bit)
access : write-only

STOP : Send Stop Condition
bits : 1 - 1 (1 bit)
access : write-only

ACK : Send ACK
bits : 2 - 2 (1 bit)
access : write-only

NACK : Send NACK
bits : 3 - 3 (1 bit)
access : write-only

CONT : Continue Transmission
bits : 4 - 4 (1 bit)
access : write-only

ABORT : Abort Transmission
bits : 5 - 5 (1 bit)
access : write-only

CLEARTX : Clear TX
bits : 6 - 6 (1 bit)
access : write-only

CLEARPC : Clear Pending Commands
bits : 7 - 7 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC TXBL RXDATAV ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP RXFULL CLERR

START : START Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

RSTART : RSTART Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

ADDR : ADDR Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

TXC : TXC Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

TXBL : TXBL Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

RXDATAV : RXDATAV Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

ACK : ACK Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

NACK : NACK Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

MSTOP : MSTOP Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

ARBLOST : ARBLOST Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

BUSERR : BUSERR Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

BUSHOLD : BUSHOLD Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

TXOF : TXOF Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

RXUF : RXUF Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write

BITO : BITO Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

CLTO : CLTO Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write

SSTOP : SSTOP Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

RXFULL : RXFULL Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

CLERR : CLERR Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write


ROUTEPEN

I/O Routing Pin Enable Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTEPEN ROUTEPEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDAPEN SCLPEN

SDAPEN : SDA Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

SCLPEN : SCL Pin Enable
bits : 1 - 1 (1 bit)
access : read-write


ROUTELOC0

I/O Routing Location Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTELOC0 ROUTELOC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDALOC SCLLOC

SDALOC : I/O Location
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

0x00000007 : LOC7

Location 7

0x00000008 : LOC8

Location 8

0x00000009 : LOC9

Location 9

0x0000000A : LOC10

Location 10

0x0000000B : LOC11

Location 11

0x0000000C : LOC12

Location 12

0x0000000D : LOC13

Location 13

0x0000000E : LOC14

Location 14

0x0000000F : LOC15

Location 15

0x00000010 : LOC16

Location 16

0x00000011 : LOC17

Location 17

0x00000012 : LOC18

Location 18

0x00000013 : LOC19

Location 19

0x00000014 : LOC20

Location 20

0x00000015 : LOC21

Location 21

0x00000016 : LOC22

Location 22

0x00000017 : LOC23

Location 23

0x00000018 : LOC24

Location 24

0x00000019 : LOC25

Location 25

0x0000001A : LOC26

Location 26

0x0000001B : LOC27

Location 27

0x0000001C : LOC28

Location 28

0x0000001D : LOC29

Location 29

0x0000001E : LOC30

Location 30

0x0000001F : LOC31

Location 31

End of enumeration elements list.

SCLLOC : I/O Location
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

0x00000007 : LOC7

Location 7

0x00000008 : LOC8

Location 8

0x00000009 : LOC9

Location 9

0x0000000A : LOC10

Location 10

0x0000000B : LOC11

Location 11

0x0000000C : LOC12

Location 12

0x0000000D : LOC13

Location 13

0x0000000E : LOC14

Location 14

0x0000000F : LOC15

Location 15

0x00000010 : LOC16

Location 16

0x00000011 : LOC17

Location 17

0x00000012 : LOC18

Location 18

0x00000013 : LOC19

Location 19

0x00000014 : LOC20

Location 20

0x00000015 : LOC21

Location 21

0x00000016 : LOC22

Location 22

0x00000017 : LOC23

Location 23

0x00000018 : LOC24

Location 24

0x00000019 : LOC25

Location 25

0x0000001A : LOC26

Location 26

0x0000001B : LOC27

Location 27

0x0000001C : LOC28

Location 28

0x0000001D : LOC29

Location 29

0x0000001E : LOC30

Location 30

0x0000001F : LOC31

Location 31

End of enumeration elements list.


STATE

State Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATE STATE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY MASTER TRANSMITTER NACKED BUSHOLD STATE

BUSY : Bus Busy
bits : 0 - 0 (1 bit)
access : read-only

MASTER : Master
bits : 1 - 1 (1 bit)
access : read-only

TRANSMITTER : Transmitter
bits : 2 - 2 (1 bit)
access : read-only

NACKED : Nack Received
bits : 3 - 3 (1 bit)
access : read-only

BUSHOLD : Bus Held
bits : 4 - 4 (1 bit)
access : read-only

STATE : Transmission State
bits : 5 - 7 (3 bit)
access : read-only

Enumeration:

0x00000000 : IDLE

No transmission is being performed.

0x00000001 : WAIT

Waiting for idle. Will send a start condition as soon as the bus is idle.

0x00000002 : START

Start transmitted or received

0x00000003 : ADDR

Address transmitted or received

0x00000004 : ADDRACK

Address ack/nack transmitted or received

0x00000005 : DATA

Data transmitted or received

0x00000006 : DATAACK

Data ack/nack transmitted or received

End of enumeration elements list.


STATUS

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTART PSTOP PACK PNACK PCONT PABORT TXC TXBL RXDATAV RXFULL

PSTART : Pending START
bits : 0 - 0 (1 bit)
access : read-only

PSTOP : Pending STOP
bits : 1 - 1 (1 bit)
access : read-only

PACK : Pending ACK
bits : 2 - 2 (1 bit)
access : read-only

PNACK : Pending NACK
bits : 3 - 3 (1 bit)
access : read-only

PCONT : Pending Continue
bits : 4 - 4 (1 bit)
access : read-only

PABORT : Pending Abort
bits : 5 - 5 (1 bit)
access : read-only

TXC : TX Complete
bits : 6 - 6 (1 bit)
access : read-only

TXBL : TX Buffer Level
bits : 7 - 7 (1 bit)
access : read-only

RXDATAV : RX Data Valid
bits : 8 - 8 (1 bit)
access : read-only

RXFULL : RX FIFO Full
bits : 9 - 9 (1 bit)
access : read-only



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