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RFSENSE_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EN

THDSEL

IF

IEN

CALCFG

RFEN

MODESEL

CMPCONF

TRIMPTAT

TRIMBG

EM4WUEN

TRIMDAC

SPARE

SWCTRL

DIAGCTRL

STATUS

CFG

SYNCWORD


EN

Block enables
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : RFSENSE Enable
bits : 0 - 0 (1 bit)
access : read-write


THDSEL

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

THDSEL THDSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 THDSEL

THDSEL : Threshold Select
bits : 0 - 7 (8 bit)
access : read-write


IF

No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFSENSEIF RFSENSE SEQIF SEQ

RFSENSEIF : RFSENSE Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

RFSENSE : RFSENSE Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

SEQIF : Sequencer Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

SEQ : Sequencer Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFSENSEIEN RFSENSE SEQIEN SEQ

RFSENSEIEN : RFSENSE Interrrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

RFSENSE : RFSENSE Interrrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

SEQIEN : Sequencer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

SEQ : Sequencer Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write


CALCFG

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALCFG CALCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPERIOD DISCMCAL DISPTATCAL ENCALPUP PTATCALSTEPS CMCALSTEPS CALSTEPCLKS PTATCALMODE

CALPERIOD : Calibration Period
bits : 0 - 7 (8 bit)
access : read-write

DISCMCAL : Disable Common Mode Calibration
bits : 12 - 12 (1 bit)
access : read-write

DISPTATCAL : Disable PTAT Calibration
bits : 13 - 13 (1 bit)
access : read-write

ENCALPUP : Enable Calibration at Power Up
bits : 14 - 14 (1 bit)
access : read-write

PTATCALSTEPS : PTAT Calibration Steps
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : STEPS2


1 : STEPS4


2 : STEPS6


3 : STEPS8


End of enumeration elements list.

CMCALSTEPS : CM Calibration Steps
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0 : STEPS2


1 : STEPS4


2 : STEPS6


3 : STEPS8


End of enumeration elements list.

CALSTEPCLKS : Clocks per calibration step settling
bits : 24 - 25 (2 bit)
access : read-write

PTATCALMODE : PTAT Calibration mode
bits : 28 - 28 (1 bit)
access : read-write


RFEN

No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RFEN RFEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBG BGSTART PTATISO PTATSTART SUPFLTN DCEN RESETN

ENBG : Enable Bandgap
bits : 0 - 0 (1 bit)
access : read-write

BGSTART : Bandgap Startup Signal
bits : 1 - 1 (1 bit)
access : read-write

PTATISO : Isolate PTAT core
bits : 2 - 2 (1 bit)
access : read-write

PTATSTART : PTAT Startup signal
bits : 3 - 3 (1 bit)
access : read-write

SUPFLTN : Disable supply filtering
bits : 4 - 4 (1 bit)
access : read-write

DCEN : DC Bias Enable
bits : 5 - 5 (1 bit)
access : read-write

RESETN : Reset RFSENSE data flop
bits : 6 - 6 (1 bit)
access : read-write


MODESEL

No Description
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODESEL MODESEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODESEL

MODESEL : Mode Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NORMAL_OP

Normal operation

1 : CM_CAL

Common-mode calibration

2 : REF_CAL

Bandgap Reference calibration

3 : NORMAL_OP2

Normal operation mode-2

4 : DM_A_CAL

Differntial A calibration

5 : DM_B_CAL

Differential B calibration

6 : DM_A_CAL2

Differential A mode-2 calibration

7 : DM_B_CAL2

Differential B mode-2 calibration

End of enumeration elements list.


CMPCONF

No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPCONF CMPCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHP HYS PLSN

CHP : Invert Comparator IO
bits : 0 - 0 (1 bit)
access : read-write

HYS : Enable Hysteresis
bits : 1 - 1 (1 bit)
access : read-write

PLSN : Disable Comparator reset pulse
bits : 2 - 2 (1 bit)
access : read-write


TRIMPTAT

IPTAT Calbiration trim values
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIMPTAT TRIMPTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMRES TRIMCURR

TRIMRES : PTAT reference resistor trim
bits : 0 - 5 (6 bit)
access : read-write

TRIMCURR : PTAT current trim
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : m80pct

Reduce PTAT current by 80%

1 : m60pct

Reduce PTAT current by 60%

2 : m40pct

Reduce PTAT current by 40%

3 : m20pct

Reduce PTAT current by 20%

4 : default

Default PTAT current

5 : p20pct

Increase PTAT current by 20%

6 : p40pct

Increase PTAT current by 40%

7 : p60pct

Increase PTAT current by 60%

End of enumeration elements list.


TRIMBG

BandGap Calibration trim values
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIMBG TRIMBG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMREF TRIMTC

TRIMREF : Reference Trim
bits : 0 - 3 (4 bit)
access : read-write

TRIMTC : TempCo Trim
bits : 4 - 7 (4 bit)
access : read-write


EM4WUEN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM4WUEN EM4WUEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4WUEN

EM4WUEN : EM4 WakeUp Enable
bits : 0 - 0 (1 bit)
access : read-write


TRIMDAC

RFSENSE DAC trim values
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIMDAC TRIMDAC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIMCM CMPOSCAL TRIMDM INVDM

TRIMCM : Trim Common Mode
bits : 0 - 7 (8 bit)
access : read-write

CMPOSCAL : Comparator Offset Calibration value
bits : 8 - 15 (8 bit)
access : read-write

TRIMDM : Trim Differential Mode
bits : 16 - 24 (9 bit)
access : read-write

INVDM : Invert Differential offset polarity
bits : 25 - 25 (1 bit)
access : read-write


SPARE

No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPARE SPARE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE DIGSPARE

SPARE : Spare register
bits : 0 - 0 (1 bit)
access : read-write

DIGSPARE : Digital Spare registers
bits : 4 - 7 (4 bit)
access : read-write


SWCTRL

Enable Software Control of the FSM signals
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWCTRL SWCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWCTRL ANACLKINV

SWCTRL : New BitField
bits : 0 - 3 (4 bit)
access : read-write

ANACLKINV : Invert Analog clock
bits : 4 - 4 (1 bit)
access : read-write


DIAGCTRL

No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIAGCTRL DIAGCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIAGABYPN DIAGACHP

DIAGABYPN : Diag buffer bypass
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : ENBYPASS

Enable DIAGA buffer bypass

1 : DISBYPASS

Disable DIAGA buffer bypass

End of enumeration elements list.

DIAGACHP : Diag buffer chop
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

Disable DIAGA buffer chop

1 : ENABLE

Enable DIAGA buffer chop

End of enumeration elements list.


STATUS

No Description
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFSENSEDATA FIRSTTRIPDONE PREAMBLEDET SYNCDET CALRUNNING CALTRIMRES CALTRIMCURR CALTRIMCM

RFSENSEDATA : RFSENSE data input from analog
bits : 0 - 0 (1 bit)
access : read-only

FIRSTTRIPDONE : First RFSENSE trip done
bits : 1 - 1 (1 bit)
access : read-only

PREAMBLEDET : Preamble Detected
bits : 2 - 2 (1 bit)
access : read-only

SYNCDET : Syncword Detected
bits : 3 - 3 (1 bit)
access : read-only

CALRUNNING : Calibration Running
bits : 4 - 4 (1 bit)
access : read-only

CALTRIMRES : Calibration Resistor Trim value
bits : 8 - 13 (6 bit)
access : read-only

CALTRIMCURR : Calibration Current Trim value
bits : 16 - 18 (3 bit)
access : read-only

CALTRIMCM : Calibration Common mode Trim value
bits : 20 - 27 (8 bit)
access : read-only


CFG

Configures RFSENSE digital logic behavior
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLELEN SYNCWORDLEN ENERGYDUR LEGACYMODE

PREAMBLELEN : Number of Preamble bits
bits : 0 - 0 (1 bit)
access : read-write

SYNCWORDLEN : Synword Length
bits : 2 - 3 (2 bit)
access : read-write

ENERGYDUR : RFSENSE Energy Duration
bits : 23 - 25 (3 bit)
access : read-write

Enumeration:

0 : dur1ms

1ms duration

1 : dur2ms

2ms duration

2 : dur4ms

4ms duration

3 : dur8ms

8ms duration

4 : dur16ms

16ms duration

5 : dur32ms

32ms duration

6 : dur64ms

64ms duration

7 : dur128ms

128ms duration

End of enumeration elements list.

LEGACYMODE : RFSENSE Legacy Mode
bits : 26 - 26 (1 bit)
access : read-write


SYNCWORD

No Description
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCWORD SYNCWORD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCWORD

SYNCWORD : Sync Word
bits : 0 - 31 (32 bit)
access : read-write



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