\n

CRYOTIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

IF

IFS

IFC

IEN

PERIODSEL

CNT

EM4WUEN


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN DEBUGRUN OSCSEL PRESC

EN : Enable CRYOTIMER
bits : 0 - 0 (1 bit)
access : read-write

DEBUGRUN : Debug Mode Run Enable
bits : 1 - 1 (1 bit)
access : read-write

OSCSEL : Select Low Frequency Oscillator
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLED

Output is driven low

0x00000001 : LFRCO

Select Low Frequency RC Oscillator

0x00000002 : LFXO

Select Low Frequency Crystal Oscillator

0x00000003 : ULFRCO

Select Ultra Low Frequency RC Oscillator

End of enumeration elements list.

PRESC : Prescaler Setting
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0x00000000 : DIV1

LF Oscillator frequency undivided

0x00000001 : DIV2

LF Oscillator frequency divided by 2

0x00000002 : DIV4

LF Oscillator frequency divided by 4

0x00000003 : DIV8

LF Oscillator frequency divided by 8

0x00000004 : DIV16

LF Oscillator frequency divided by 16

0x00000005 : DIV32

LF Oscillator frequency divided by 32

0x00000006 : DIV64

LF Oscillator frequency divided by 64

0x00000007 : DIV128

LF Oscillator frequency divided by 128

End of enumeration elements list.


IF

Interrupt Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : Wakeup Event/Interrupt
bits : 0 - 0 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : Set PERIOD Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : Clear PERIOD Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD : PERIOD Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write


PERIODSEL

Interrupt Duration
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIODSEL PERIODSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIODSEL

PERIODSEL : Interrupts/Wakeup Events Period Setting
bits : 0 - 5 (6 bit)
access : read-write


CNT

Counter Value
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value
bits : 0 - 31 (32 bit)
access : read-only


EM4WUEN

Wake Up Enable
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM4WUEN EM4WUEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4WU

EM4WU : EM4 Wake-up Enable
bits : 0 - 0 (1 bit)
access : read-write



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