\n

EMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CMD

BIASCONF

EM4CTRL

TESTLOCK

BIASTESTCTRL

TEMPLIMITS

TEMP

IF

IFS

IFC

IEN

PWRLOCK

PWRCFG

PWRCTRL

STATUS

DCDCCTRL

DCDCMISCCTRL

DCDCZDETCTRL

DCDCCLIMCTRL

DCDCLNCOMPCTRL

DCDCLNVCTRL

DCDCTIMING

DCDCLPVCTRL

DCDCLPCTRL

DCDCLNFREQCTRL

DCDCSYNC

LOCK

VMONAVDDCTRL

VMONALTAVDDCTRL

VMONDVDDCTRL

VMONIO0CTRL

RAM0CTRL


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM2BLOCK

EM2BLOCK : Energy Mode 2 Block
bits : 1 - 1 (1 bit)
access : read-write


CMD

Command Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4UNLATCH

EM4UNLATCH : EM4 Unlatch
bits : 0 - 0 (1 bit)
access : write-only


BIASCONF

Configurations Related to the Bias
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIASCONF BIASCONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NADUTYEM01 LPEM01 GMCEM23 UADUTYEM23 NADUTYEM23 LPEM23

NADUTYEM01 : NA DUTY in EM01
bits : 2 - 2 (1 bit)
access : read-write

LPEM01 : LP in EM01
bits : 3 - 3 (1 bit)
access : read-write

GMCEM23 : GMC in EM234
bits : 4 - 4 (1 bit)
access : read-write

UADUTYEM23 : UADUTY in EM234
bits : 5 - 5 (1 bit)
access : read-write

NADUTYEM23 : NA DUTY in EM234
bits : 6 - 6 (1 bit)
access : read-write

LPEM23 : LP in EM234
bits : 7 - 7 (1 bit)
access : read-write


EM4CTRL

EM4 Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EM4CTRL EM4CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EM4STATE RETAINLFRCO RETAINLFXO RETAINULFRCO EM4IORETMODE EM4ENTRY

EM4STATE : Energy Mode 4 State
bits : 0 - 0 (1 bit)
access : read-write

RETAINLFRCO : LFRCO Retain During EM4
bits : 1 - 1 (1 bit)
access : read-write

RETAINLFXO : LFXO Retain During EM4
bits : 2 - 2 (1 bit)
access : read-write

RETAINULFRCO : ULFRCO Retain During EM4S
bits : 3 - 3 (1 bit)
access : read-write

EM4IORETMODE : EM4 IO Retention Disable
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

No Retention: Pads enter reset state when entering EM4

0x00000001 : EM4EXIT

Retention through EM4: Pads enter reset state when exiting EM4

0x00000002 : SWUNLATCH

Retention through EM4 and Wakeup: software writes UNLATCH register to remove retention

End of enumeration elements list.

EM4ENTRY : Energy Mode 4 Entry
bits : 16 - 17 (2 bit)
access : write-only


TESTLOCK

Test Lock Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTLOCK TESTLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


BIASTESTCTRL

Test Control Register for Regulator and BIAS
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BIASTESTCTRL BIASTESTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIAS_RIP_RESET

BIAS_RIP_RESET : Reset Bias Ripple Counter
bits : 3 - 3 (1 bit)
access : read-write


TEMPLIMITS

Temperature Limits for Interrupt Generation
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEMPLIMITS TEMPLIMITS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMPLOW TEMPHIGH EM4WUEN

TEMPLOW : Temperature Low Limit
bits : 0 - 7 (8 bit)
access : read-write

TEMPHIGH : Temperature High Limit
bits : 8 - 15 (8 bit)
access : read-write

EM4WUEN : Enable EM4 Wakeup Due to Low/high Temperature
bits : 16 - 16 (1 bit)
access : read-write


TEMP

Value of Last Temperature Measurement
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TEMP TEMP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMP

TEMP : Temperature Measurement
bits : 0 - 7 (8 bit)
access : read-only


IF

Interrupt Flag Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMONAVDDFALL VMONAVDDRISE VMONALTAVDDFALL VMONALTAVDDRISE VMONDVDDFALL VMONDVDDRISE VMONIO0FALL VMONIO0RISE VMONFVDDFALL VMONFVDDRISE PFETOVERCURRENTLIMIT NFETOVERCURRENTLIMIT DCDCLPRUNNING DCDCLNRUNNING DCDCINBYPASS EM23WAKEUP TEMP TEMPLOW TEMPHIGH

VMONAVDDFALL : VMON AVDD Channel Fall
bits : 0 - 0 (1 bit)
access : read-only

VMONAVDDRISE : VMON AVDD Channel Rise
bits : 1 - 1 (1 bit)
access : read-only

VMONALTAVDDFALL : Alternate VMON AVDD Channel Fall
bits : 2 - 2 (1 bit)
access : read-only

VMONALTAVDDRISE : Alternate VMON AVDD Channel Rise
bits : 3 - 3 (1 bit)
access : read-only

VMONDVDDFALL : VMON DVDD Channel Fall
bits : 4 - 4 (1 bit)
access : read-only

VMONDVDDRISE : VMON DVDD Channel Rise
bits : 5 - 5 (1 bit)
access : read-only

VMONIO0FALL : VMON IOVDD0 Channel Fall
bits : 6 - 6 (1 bit)
access : read-only

VMONIO0RISE : VMON IOVDD0 Channel Rise
bits : 7 - 7 (1 bit)
access : read-only

VMONFVDDFALL : VMON VDDFLASH Channel Fall
bits : 14 - 14 (1 bit)
access : read-only

VMONFVDDRISE : VMON VDDFLASH Channel Rise
bits : 15 - 15 (1 bit)
access : read-only

PFETOVERCURRENTLIMIT : PFET Current Limit Hit
bits : 16 - 16 (1 bit)
access : read-only

NFETOVERCURRENTLIMIT : NFET Current Limit Hit
bits : 17 - 17 (1 bit)
access : read-only

DCDCLPRUNNING : LP Mode is Running
bits : 18 - 18 (1 bit)
access : read-only

DCDCLNRUNNING : LN Mode is Running
bits : 19 - 19 (1 bit)
access : read-only

DCDCINBYPASS : DCDC is in Bypass
bits : 20 - 20 (1 bit)
access : read-only

EM23WAKEUP : Wakeup IRQ From EM2 and EM3
bits : 24 - 24 (1 bit)
access : read-only

TEMP : New Temperature Measurement Valid
bits : 29 - 29 (1 bit)
access : read-only

TEMPLOW : Temperature Low Limit Reached
bits : 30 - 30 (1 bit)
access : read-only

TEMPHIGH : Temperature High Limit Reached
bits : 31 - 31 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMONAVDDFALL VMONAVDDRISE VMONALTAVDDFALL VMONALTAVDDRISE VMONDVDDFALL VMONDVDDRISE VMONIO0FALL VMONIO0RISE VMONFVDDFALL VMONFVDDRISE PFETOVERCURRENTLIMIT NFETOVERCURRENTLIMIT DCDCLPRUNNING DCDCLNRUNNING DCDCINBYPASS EM23WAKEUP TEMP TEMPLOW TEMPHIGH

VMONAVDDFALL : Set VMONAVDDFALL Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

VMONAVDDRISE : Set VMONAVDDRISE Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

VMONALTAVDDFALL : Set VMONALTAVDDFALL Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

VMONALTAVDDRISE : Set VMONALTAVDDRISE Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

VMONDVDDFALL : Set VMONDVDDFALL Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

VMONDVDDRISE : Set VMONDVDDRISE Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

VMONIO0FALL : Set VMONIO0FALL Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

VMONIO0RISE : Set VMONIO0RISE Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

VMONFVDDFALL : Set VMONFVDDFALL Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

VMONFVDDRISE : Set VMONFVDDRISE Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

PFETOVERCURRENTLIMIT : Set PFETOVERCURRENTLIMIT Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

NFETOVERCURRENTLIMIT : Set NFETOVERCURRENTLIMIT Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

DCDCLPRUNNING : Set DCDCLPRUNNING Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only

DCDCLNRUNNING : Set DCDCLNRUNNING Interrupt Flag
bits : 19 - 19 (1 bit)
access : write-only

DCDCINBYPASS : Set DCDCINBYPASS Interrupt Flag
bits : 20 - 20 (1 bit)
access : write-only

EM23WAKEUP : Set EM23WAKEUP Interrupt Flag
bits : 24 - 24 (1 bit)
access : write-only

TEMP : Set TEMP Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only

TEMPLOW : Set TEMPLOW Interrupt Flag
bits : 30 - 30 (1 bit)
access : write-only

TEMPHIGH : Set TEMPHIGH Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMONAVDDFALL VMONAVDDRISE VMONALTAVDDFALL VMONALTAVDDRISE VMONDVDDFALL VMONDVDDRISE VMONIO0FALL VMONIO0RISE VMONFVDDFALL VMONFVDDRISE PFETOVERCURRENTLIMIT NFETOVERCURRENTLIMIT DCDCLPRUNNING DCDCLNRUNNING DCDCINBYPASS EM23WAKEUP TEMP TEMPLOW TEMPHIGH

VMONAVDDFALL : Clear VMONAVDDFALL Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

VMONAVDDRISE : Clear VMONAVDDRISE Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only

VMONALTAVDDFALL : Clear VMONALTAVDDFALL Interrupt Flag
bits : 2 - 2 (1 bit)
access : write-only

VMONALTAVDDRISE : Clear VMONALTAVDDRISE Interrupt Flag
bits : 3 - 3 (1 bit)
access : write-only

VMONDVDDFALL : Clear VMONDVDDFALL Interrupt Flag
bits : 4 - 4 (1 bit)
access : write-only

VMONDVDDRISE : Clear VMONDVDDRISE Interrupt Flag
bits : 5 - 5 (1 bit)
access : write-only

VMONIO0FALL : Clear VMONIO0FALL Interrupt Flag
bits : 6 - 6 (1 bit)
access : write-only

VMONIO0RISE : Clear VMONIO0RISE Interrupt Flag
bits : 7 - 7 (1 bit)
access : write-only

VMONFVDDFALL : Clear VMONFVDDFALL Interrupt Flag
bits : 14 - 14 (1 bit)
access : write-only

VMONFVDDRISE : Clear VMONFVDDRISE Interrupt Flag
bits : 15 - 15 (1 bit)
access : write-only

PFETOVERCURRENTLIMIT : Clear PFETOVERCURRENTLIMIT Interrupt Flag
bits : 16 - 16 (1 bit)
access : write-only

NFETOVERCURRENTLIMIT : Clear NFETOVERCURRENTLIMIT Interrupt Flag
bits : 17 - 17 (1 bit)
access : write-only

DCDCLPRUNNING : Clear DCDCLPRUNNING Interrupt Flag
bits : 18 - 18 (1 bit)
access : write-only

DCDCLNRUNNING : Clear DCDCLNRUNNING Interrupt Flag
bits : 19 - 19 (1 bit)
access : write-only

DCDCINBYPASS : Clear DCDCINBYPASS Interrupt Flag
bits : 20 - 20 (1 bit)
access : write-only

EM23WAKEUP : Clear EM23WAKEUP Interrupt Flag
bits : 24 - 24 (1 bit)
access : write-only

TEMP : Clear TEMP Interrupt Flag
bits : 29 - 29 (1 bit)
access : write-only

TEMPLOW : Clear TEMPLOW Interrupt Flag
bits : 30 - 30 (1 bit)
access : write-only

TEMPHIGH : Clear TEMPHIGH Interrupt Flag
bits : 31 - 31 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMONAVDDFALL VMONAVDDRISE VMONALTAVDDFALL VMONALTAVDDRISE VMONDVDDFALL VMONDVDDRISE VMONIO0FALL VMONIO0RISE VMONFVDDFALL VMONFVDDRISE PFETOVERCURRENTLIMIT NFETOVERCURRENTLIMIT DCDCLPRUNNING DCDCLNRUNNING DCDCINBYPASS EM23WAKEUP TEMP TEMPLOW TEMPHIGH

VMONAVDDFALL : VMONAVDDFALL Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

VMONAVDDRISE : VMONAVDDRISE Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

VMONALTAVDDFALL : VMONALTAVDDFALL Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

VMONALTAVDDRISE : VMONALTAVDDRISE Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

VMONDVDDFALL : VMONDVDDFALL Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

VMONDVDDRISE : VMONDVDDRISE Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

VMONIO0FALL : VMONIO0FALL Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

VMONIO0RISE : VMONIO0RISE Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

VMONFVDDFALL : VMONFVDDFALL Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

VMONFVDDRISE : VMONFVDDRISE Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write

PFETOVERCURRENTLIMIT : PFETOVERCURRENTLIMIT Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write

NFETOVERCURRENTLIMIT : NFETOVERCURRENTLIMIT Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

DCDCLPRUNNING : DCDCLPRUNNING Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write

DCDCLNRUNNING : DCDCLNRUNNING Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write

DCDCINBYPASS : DCDCINBYPASS Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write

EM23WAKEUP : EM23WAKEUP Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write

TEMP : TEMP Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write

TEMPLOW : TEMPLOW Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write

TEMPHIGH : TEMPHIGH Interrupt Enable
bits : 31 - 31 (1 bit)
access : read-write


PWRLOCK

Regulator and Supply Lock Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRLOCK PWRLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Regulator and Supply Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


PWRCFG

Power Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCFG PWRCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRCFG

PWRCFG : Power Configuration
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000000 : STARTUP

Power up configuration. Works with any external configuration.

0x00000002 : DCDCTODVDD

Configured: DCDC control logic is enabled.

End of enumeration elements list.


PWRCTRL

Power Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCTRL PWRCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANASW

ANASW : Analog Switch Selection
bits : 5 - 5 (1 bit)
access : read-write


STATUS

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VMONRDY VMONAVDD VMONALTAVDD VMONDVDD VMONIO0 VMONFVDD EM4IORET

VMONRDY : VMON Ready
bits : 0 - 0 (1 bit)
access : read-only

VMONAVDD : VMON AVDD Channel
bits : 1 - 1 (1 bit)
access : read-only

VMONALTAVDD : Alternate VMON AVDD Channel
bits : 2 - 2 (1 bit)
access : read-only

VMONDVDD : VMON DVDD Channel
bits : 3 - 3 (1 bit)
access : read-only

VMONIO0 : VMON IOVDD0 Channel
bits : 4 - 4 (1 bit)
access : read-only

VMONFVDD : VMON VDDFLASH Channel
bits : 8 - 8 (1 bit)
access : read-only

EM4IORET : IO Retention Status
bits : 20 - 20 (1 bit)
access : read-only


DCDCCTRL

DCDC Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCCTRL DCDCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDCMODE DCDCMODEEM23 DCDCMODEEM4

DCDCMODE : Regulator Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : BYPASS

DCDC regulator is operating in bypass mode. Prior to configuring DCDCMODE=BYPASS, software must set EMU_DCDCCLIMCTRL.BYPLIMEN=1 to prevent excessive current between VREGVDD and DVDD supplies.

0x00000001 : LOWNOISE

DCDC regulator is operating in low noise mode.

0x00000002 : LOWPOWER

DCDC regulator is operating in low power mode.

0x00000003 : OFF

DCDC regulator is off and the bypass switch is off. Note: DVDD must be supplied externally

End of enumeration elements list.

DCDCMODEEM23 : DCDC Mode EM23
bits : 4 - 4 (1 bit)
access : read-write

DCDCMODEEM4 : DCDC Mode EM4H
bits : 5 - 5 (1 bit)
access : read-write


DCDCMISCCTRL

DCDC Miscellaneous Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCMISCCTRL DCDCMISCCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNFORCECCM PFETCNT NFETCNT BYPLIMSEL LPCLIMILIMSEL LNCLIMILIMSEL LPCMPBIAS

LNFORCECCM : Force DCDC Into CCM Mode in Low Noise Operation
bits : 0 - 0 (1 bit)
access : read-write

PFETCNT : PFET Switch Number Selection
bits : 8 - 11 (4 bit)
access : read-write

NFETCNT : NFET Switch Number Selection
bits : 12 - 15 (4 bit)
access : read-write

BYPLIMSEL : Current Limit in Bypass Mode
bits : 16 - 19 (4 bit)
access : read-write

LPCLIMILIMSEL : Current Limit Level Selection for Current Limiter in LP Mode
bits : 20 - 22 (3 bit)
access : read-write

LNCLIMILIMSEL : Current Limit Level Selection for Current Limiter in LN Mode
bits : 24 - 26 (3 bit)
access : read-write

LPCMPBIAS : LP Mode Comparator Bias Selection
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x00000000 : BIAS0

Maximum load current less than 75uA.

0x00000001 : BIAS1

Maximum load current less than 500uA.

0x00000002 : BIAS2

Maximum load current less than 2.5mA.

0x00000003 : BIAS3

Maximum load current less than 10mA.

End of enumeration elements list.


DCDCZDETCTRL

DCDC Power Train NFET Zero Current Detector Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCZDETCTRL DCDCZDETCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZDETILIMSEL ZDETBLANKDLY

ZDETILIMSEL : Reverse Current Limit Level Selection for Zero Detector
bits : 4 - 6 (3 bit)
access : read-write

ZDETBLANKDLY : Reserved for internal use. Do not change.
bits : 8 - 9 (2 bit)
access : read-write


DCDCCLIMCTRL

DCDC Power Train PFET Current Limiter Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCCLIMCTRL DCDCCLIMCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLIMBLANKDLY BYPLIMEN

CLIMBLANKDLY : Reserved for internal use. Do not change.
bits : 8 - 9 (2 bit)
access : read-write

BYPLIMEN : Bypass Current Limit Enable
bits : 13 - 13 (1 bit)
access : read-write


DCDCLNCOMPCTRL

DCDC Low Noise Compensator Control Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCLNCOMPCTRL DCDCLNCOMPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMPENR1 COMPENR2 COMPENR3 COMPENC1 COMPENC2 COMPENC3

COMPENR1 : Low Noise Mode Compensator R1 Trim Value
bits : 0 - 2 (3 bit)
access : read-write

COMPENR2 : Low Noise Mode Compensator R2 Trim Value
bits : 4 - 8 (5 bit)
access : read-write

COMPENR3 : Low Noise Mode Compensator R3 Trim Value
bits : 12 - 15 (4 bit)
access : read-write

COMPENC1 : Low Noise Mode Compensator C1 Trim Value
bits : 20 - 21 (2 bit)
access : read-write

COMPENC2 : Low Noise Mode Compensator C2 Trim Value
bits : 24 - 26 (3 bit)
access : read-write

COMPENC3 : Low Noise Mode Compensator C3 Trim Value
bits : 28 - 31 (4 bit)
access : read-write


DCDCLNVCTRL

DCDC Low Noise Voltage Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCLNVCTRL DCDCLNVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNATT LNVREF

LNATT : Low Noise Mode Feedback Attenuation
bits : 1 - 1 (1 bit)
access : read-write

LNVREF : Low Noise Mode VREF Trim
bits : 8 - 14 (7 bit)
access : read-write


DCDCTIMING

DCDC Controller Timing Value Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCTIMING DCDCTIMING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPINITWAIT COMPENPRCHGEN LNWAIT BYPWAIT DUTYSCALE

LPINITWAIT : Low Power Initialization Wait Time
bits : 0 - 7 (8 bit)
access : read-write

COMPENPRCHGEN : LN Mode Precharge Enable
bits : 11 - 11 (1 bit)
access : read-write

LNWAIT : Low Noise Controller Initialization Wait Time
bits : 12 - 16 (5 bit)
access : read-write

BYPWAIT : Bypass Mode Transition From Low Power or Low Noise Modes Wait Wait
bits : 20 - 27 (8 bit)
access : read-write

DUTYSCALE : Select Bias Duty Cycle Clock
bits : 29 - 30 (2 bit)
access : read-write


DCDCLPVCTRL

DCDC Low Power Voltage Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCLPVCTRL DCDCLPVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPATT LPVREF

LPATT : Low Power Feedback Attenuation
bits : 0 - 0 (1 bit)
access : read-write

LPVREF : LP Mode Reference Selection for EM23 and EM4H
bits : 1 - 8 (8 bit)
access : read-write


DCDCLPCTRL

DCDC Low Power Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCLPCTRL DCDCLPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPCMPHYSSEL LPVREFDUTYEN LPBLANK

LPCMPHYSSEL : LP Mode Hysteresis Selection
bits : 12 - 15 (4 bit)
access : read-write

LPVREFDUTYEN : LP Mode Duty Cycling Enable
bits : 24 - 24 (1 bit)
access : read-write

LPBLANK : Reserved for internal use. Do not change.
bits : 25 - 26 (2 bit)
access : read-write


DCDCLNFREQCTRL

DCDC Low Noise Controller Frequency Control
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCDCLNFREQCTRL DCDCLNFREQCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCOBAND RCOTRIM

RCOBAND : LN Mode RCO Frequency Band Selection
bits : 0 - 2 (3 bit)
access : read-write

RCOTRIM : Reserved for internal use. Do not change.
bits : 24 - 28 (5 bit)
access : read-write


DCDCSYNC

DCDC Read Status Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DCDCSYNC DCDCSYNC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDCCTRLBUSY

DCDCCTRLBUSY : DCDC CTRL Register Transfer Busy
bits : 0 - 0 (1 bit)
access : read-only


LOCK

Configuration Lock Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


VMONAVDDCTRL

VMON AVDD Channel Control
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VMONAVDDCTRL VMONAVDDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RISEWU FALLWU FALLTHRESFINE FALLTHRESCOARSE RISETHRESFINE RISETHRESCOARSE

EN : Enable
bits : 0 - 0 (1 bit)
access : read-write

RISEWU : Rise Wakeup
bits : 2 - 2 (1 bit)
access : read-write

FALLWU : Fall Wakeup
bits : 3 - 3 (1 bit)
access : read-write

FALLTHRESFINE : Falling Threshold Fine Adjust
bits : 8 - 11 (4 bit)
access : read-write

FALLTHRESCOARSE : Falling Threshold Coarse Adjust
bits : 12 - 15 (4 bit)
access : read-write

RISETHRESFINE : Rising Threshold Fine Adjust
bits : 16 - 19 (4 bit)
access : read-write

RISETHRESCOARSE : Rising Threshold Coarse Adjust
bits : 20 - 23 (4 bit)
access : read-write


VMONALTAVDDCTRL

Alternate VMON AVDD Channel Control
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VMONALTAVDDCTRL VMONALTAVDDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RISEWU FALLWU THRESFINE THRESCOARSE

EN : Enable
bits : 0 - 0 (1 bit)
access : read-write

RISEWU : Rise Wakeup
bits : 2 - 2 (1 bit)
access : read-write

FALLWU : Fall Wakeup
bits : 3 - 3 (1 bit)
access : read-write

THRESFINE : Threshold Fine Adjust
bits : 8 - 11 (4 bit)
access : read-write

THRESCOARSE : Threshold Coarse Adjust
bits : 12 - 15 (4 bit)
access : read-write


VMONDVDDCTRL

VMON DVDD Channel Control
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VMONDVDDCTRL VMONDVDDCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RISEWU FALLWU THRESFINE THRESCOARSE

EN : Enable
bits : 0 - 0 (1 bit)
access : read-write

RISEWU : Rise Wakeup
bits : 2 - 2 (1 bit)
access : read-write

FALLWU : Fall Wakeup
bits : 3 - 3 (1 bit)
access : read-write

THRESFINE : Threshold Fine Adjust
bits : 8 - 11 (4 bit)
access : read-write

THRESCOARSE : Threshold Coarse Adjust
bits : 12 - 15 (4 bit)
access : read-write


VMONIO0CTRL

VMON IOVDD0 Channel Control
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VMONIO0CTRL VMONIO0CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN RISEWU FALLWU RETDIS THRESFINE THRESCOARSE

EN : Enable
bits : 0 - 0 (1 bit)
access : read-write

RISEWU : Rise Wakeup
bits : 2 - 2 (1 bit)
access : read-write

FALLWU : Fall Wakeup
bits : 3 - 3 (1 bit)
access : read-write

RETDIS : EM4 IO0 Retention Disable
bits : 4 - 4 (1 bit)
access : read-write

THRESFINE : Threshold Fine Adjust
bits : 8 - 11 (4 bit)
access : read-write

THRESCOARSE : Threshold Coarse Adjust
bits : 12 - 15 (4 bit)
access : read-write


RAM0CTRL

Memory Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAM0CTRL RAM0CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAMPOWERDOWN

RAMPOWERDOWN : RAM0 Blockset Power-down
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x00000000 : NONE

None of the RAM blocks powered down

0x00000008 : BLK4

Power down RAM blocks 4 and above

0x0000000C : BLK3TO4

Power down RAM blocks 3 and above

0x0000000E : BLK2TO4

Power down RAM blocks 2 and above

0x0000000F : BLK1TO4

Power down RAM blocks 1 and above

End of enumeration elements list.



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.