\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNNING : LETIMER Running
bits : 0 - 0 (1 bit)
access : read-only
No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value
bits : 0 - 23 (24 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Compare Value 0
bits : 0 - 23 (24 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP1 : Compare Value 1
bits : 0 - 23 (24 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOP : Counter TOP Value
bits : 0 - 23 (24 bit)
access : read-write
No Description
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOPBUFF : Buffered Counter TOP Value
bits : 0 - 23 (24 bit)
access : read-write
No Description
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP0 : Repeat Counter 0
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REP1 : Repeat Counter 1
bits : 0 - 7 (8 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Compare Match 0 Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
COMP1 : Compare Match 1 Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
UF : Underflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
REP0 : Repeat Counter 0 Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
REP1 : Repeat Counter 1 Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMP0 : Compare Match 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
COMP1 : Compare Match 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
UF : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
REP0 : Repeat Counter 0 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
REP1 : Repeat Counter 1 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : module en
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Sync busy for CNT
bits : 0 - 0 (1 bit)
access : read-only
TOP : Sync busy for TOP
bits : 2 - 2 (1 bit)
access : read-only
REP0 : Sync busy for REP0
bits : 3 - 3 (1 bit)
access : read-only
REP1 : Sync busy for REP1
bits : 4 - 4 (1 bit)
access : read-only
START : Sync busy for START
bits : 5 - 5 (1 bit)
access : read-only
STOP : Sync busy for STOP
bits : 6 - 6 (1 bit)
access : read-only
CLEAR : Sync busy for CLEAR
bits : 7 - 7 (1 bit)
access : read-only
CTO0 : Sync busy for CTO0
bits : 8 - 8 (1 bit)
access : read-only
CTO1 : Sync busy for CTO1
bits : 9 - 9 (1 bit)
access : read-only
No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRSSTARTMODE : PRS Start Mode
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : NONE
PRS cannot start the LETIMER
1 : RISING
Rising edge of selected PRS input can start the LETIMER
2 : FALLING
Falling edge of selected PRS input can start the LETIMER
3 : BOTH
Both the rising or falling edge of the selected PRS input can start the LETIMER
End of enumeration elements list.
PRSSTOPMODE : PRS Stop Mode
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : NONE
PRS cannot stop the LETIMER
1 : RISING
Rising edge of selected PRS input can stop the LETIMER
2 : FALLING
Falling edge of selected PRS input can stop the LETIMER
3 : BOTH
Both the rising or falling edge of the selected PRS input can stop the LETIMER
End of enumeration elements list.
PRSCLEARMODE : PRS Clear Mode
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : NONE
PRS cannot clear the LETIMER
1 : RISING
Rising edge of selected PRS input can clear the LETIMER
2 : FALLING
Falling edge of selected PRS input can clear the LETIMER
3 : BOTH
Both the rising or falling edge of the selected PRS input can clear the LETIMER
End of enumeration elements list.
No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REPMODE : Repeat Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FREE
When started, the LETIMER counts down until it is stopped by software
1 : ONESHOT
The counter counts REP0 times. When REP0 reaches zero, the counter stops
2 : BUFFERED
The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops
3 : DOUBLE
Both REP0 and REP1 are decremented when the LETIMER wraps around. The LETIMER counts until both REP0 and REP1 are zero
End of enumeration elements list.
UFOA0 : Underflow Output Action 0
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : NONE
LETIMERn_OUT0 is held at its idle value as defined by OPOL0
1 : TOGGLE
LETIMERn_OUT0 is toggled on CNT underflow
2 : PULSE
LETIMERn_OUT0 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL0
3 : PWM
LETIMERn_OUT0 is set idle on CNT underflow, and active on compare match with COMP1
End of enumeration elements list.
UFOA1 : Underflow Output Action 1
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : NONE
LETIMERn_OUT1 is held at its idle value as defined by OPOL1
1 : TOGGLE
LETIMERn_OUT1 is toggled on CNT underflow
2 : PULSE
LETIMERn_OUT1 is held active for one LETIMER0 clock cycle on CNT underflow. The output then returns to its idle value as defined by OPOL1
3 : PWM
LETIMERn_OUT1 is set idle on CNT underflow, and active on compare match with COMP1
End of enumeration elements list.
OPOL0 : Output 0 Polarity
bits : 6 - 6 (1 bit)
access : read-write
OPOL1 : Output 1 Polarity
bits : 7 - 7 (1 bit)
access : read-write
BUFTOP : Buffered Top
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
COMP0 is only written by software
1 : ENABLE
COMP0 is set to COMP1 when REP0 reaches 0
End of enumeration elements list.
CNTTOPEN : Compare Value 0 Is Top Value
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The top value of the LETIMER is 65535 (0xFFFF)
1 : ENABLE
The top value of the LETIMER is given by COMP0
End of enumeration elements list.
DEBUGRUN : Debug Mode Run Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
LETIMER is frozen in debug mode
1 : ENABLE
LETIMER is running in debug mode
End of enumeration elements list.
CNTPRESC : Counter prescaler value
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : DIV1
CLK_CNT = (LETIMER LF CLK)/1
1 : DIV2
CLK_CNT = (LETIMER LF CLK)/2
2 : DIV4
CLK_CNT = (LETIMER LF CLK)/4
3 : DIV8
CLK_CNT = (LETIMER LF CLK)/8
4 : DIV16
CLK_CNT = (LETIMER LF CLK)/16
5 : DIV32
CLK_CNT = (LETIMER LF CLK)/32
6 : DIV64
CLK_CNT = (LETIMER LF CLK)/64
7 : DIV128
CLK_CNT = (LETIMER LF CLK)/128
8 : DIV256
CLK_CNT = (LETIMER LF CLK)/256
End of enumeration elements list.
No Description
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start LETIMER
bits : 0 - 0 (1 bit)
access : write-only
STOP : Stop LETIMER
bits : 1 - 1 (1 bit)
access : write-only
CLEAR : Clear LETIMER
bits : 2 - 2 (1 bit)
access : write-only
CTO0 : Clear Toggle Output 0
bits : 3 - 3 (1 bit)
access : write-only
CTO1 : Clear Toggle Output 1
bits : 4 - 4 (1 bit)
access : write-only
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