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PRS_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

ASYNC_PEEK

CONSUMER_CORE_CTIIN0

CONSUMER_CORE_CTIIN1

CONSUMER_CORE_CTIIN2

CONSUMER_CORE_CTIIN3

CONSUMER_CORE_M33RXEV

CONSUMER_TIMER0_CC0

CONSUMER_TIMER0_CC1

CONSUMER_TIMER0_CC2

CONSUMER_TIMER0_DTI

CONSUMER_TIMER0_DTIFS1

CONSUMER_TIMER0_DTIFS2

CONSUMER_TIMER1_CC0

CONSUMER_TIMER1_CC1

CONSUMER_TIMER1_CC2

SYNC_PEEK

CONSUMER_TIMER1_DTI

CONSUMER_TIMER1_DTIFS1

CONSUMER_TIMER1_DTIFS2

CONSUMER_TIMER2_CC0

CONSUMER_TIMER2_CC1

CONSUMER_TIMER2_CC2

CONSUMER_TIMER2_DTI

CONSUMER_TIMER2_DTIFS1

CONSUMER_TIMER2_DTIFS2

CONSUMER_TIMER3_CC0

CONSUMER_TIMER3_CC1

CONSUMER_TIMER3_CC2

CONSUMER_TIMER3_DTI

CONSUMER_TIMER3_DTIFS1

CONSUMER_TIMER3_DTIFS2

CONSUMER_USART0_CLK

ASYNC_CH0_CTRL

CONSUMER_USART0_IR

CONSUMER_USART0_RX

CONSUMER_USART0_TRIGGER

CONSUMER_USART1_CLK

CONSUMER_USART1_IR

CONSUMER_USART1_RX

CONSUMER_USART1_TRIGGER

CONSUMER_USART2_CLK

CONSUMER_USART2_IR

CONSUMER_USART2_RX

CONSUMER_USART2_TRIGGER

CONSUMER_WDOG0_SRC0

CONSUMER_WDOG0_SRC1

CONSUMER_WDOG1_SRC0

CONSUMER_WDOG1_SRC1

ASYNC_CH1_CTRL

ASYNC_CH2_CTRL

ASYNC_CH3_CTRL

ASYNC_CH4_CTRL

ASYNC_CH5_CTRL

ASYNC_CH6_CTRL

ASYNC_CH7_CTRL

ASYNC_CH8_CTRL

ASYNC_CH9_CTRL

ASYNC_CH10_CTRL

ASYNC_CH11_CTRL

SYNC_CH0_CTRL

SYNC_CH1_CTRL

SYNC_CH2_CTRL

SYNC_CH3_CTRL

CONSUMER_CMU_CALDN

CONSUMER_CMU_CALUP

CONSUMER_IADC0_SCANTRIGGER

CONSUMER_IADC0_SINGLETRIGGER

CONSUMER_LDMAXBAR_DMAREQ0

CONSUMER_LDMAXBAR_DMAREQ1

CONSUMER_LETIMER0_CLEAR

CONSUMER_LETIMER0_START

CONSUMER_LETIMER0_STOP

ASYNC_SWPULSE

CONSUMER_MODEM_DIN

CONSUMER_RAC_CLR

CONSUMER_RAC_FORCETX

ASYNC_SWLEVEL

CONSUMER_RAC_RXDIS

CONSUMER_RAC_RXEN

CONSUMER_RAC_SEQ

CONSUMER_RAC_TXEN

CONSUMER_RTCC_CC0

CONSUMER_RTCC_CC1

CONSUMER_RTCC_CC2

CONSUMER_SE_TAMPERSRC0

CONSUMER_SE_TAMPERSRC1

CONSUMER_SE_TAMPERSRC2

CONSUMER_SE_TAMPERSRC3

CONSUMER_SE_TAMPERSRC4

CONSUMER_SE_TAMPERSRC5

CONSUMER_SE_TAMPERSRC6

CONSUMER_SE_TAMPERSRC7


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP version ID
bits : 0 - 31 (32 bit)
access : read-only


ASYNC_PEEK

No Description
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ASYNC_PEEK ASYNC_PEEK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL CH1VAL CH2VAL CH3VAL CH4VAL CH5VAL CH6VAL CH7VAL CH8VAL CH9VAL CH10VAL CH11VAL

CH0VAL : Channel 0 Current Value
bits : 0 - 0 (1 bit)
access : read-only

CH1VAL : Channel 1 Current Value
bits : 1 - 1 (1 bit)
access : read-only

CH2VAL : Channel 2 Current Value
bits : 2 - 2 (1 bit)
access : read-only

CH3VAL : Channel 3 Current Value
bits : 3 - 3 (1 bit)
access : read-only

CH4VAL : Channel 4 Current Value
bits : 4 - 4 (1 bit)
access : read-only

CH5VAL : Channel 5 Current Value
bits : 5 - 5 (1 bit)
access : read-only

CH6VAL : Channel 6 Current Value
bits : 6 - 6 (1 bit)
access : read-only

CH7VAL : Channel 7 Current Value
bits : 7 - 7 (1 bit)
access : read-only

CH8VAL : Channel 8 Current Value
bits : 8 - 8 (1 bit)
access : read-only

CH9VAL : Channel 9 Current Value
bits : 9 - 9 (1 bit)
access : read-only

CH10VAL : Channel 10 Current Value
bits : 10 - 10 (1 bit)
access : read-only

CH11VAL : Channel 11 Current Value
bits : 11 - 11 (1 bit)
access : read-only


CONSUMER_CORE_CTIIN0

No Description
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN0 CONSUMER_CORE_CTIIN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_CTIIN1

No Description
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN1 CONSUMER_CORE_CTIIN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_CTIIN2

No Description
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN2 CONSUMER_CORE_CTIIN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_CTIIN3

No Description
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_CTIIN3 CONSUMER_CORE_CTIIN3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CORE_M33RXEV

No Description
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CORE_M33RXEV CONSUMER_CORE_M33RXEV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER0_CC0

No Description
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_CC0 CONSUMER_TIMER0_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER0_CC1

No Description
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_CC1 CONSUMER_TIMER0_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER0_CC2

No Description
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_CC2 CONSUMER_TIMER0_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER0_DTI

No Description
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_DTI CONSUMER_TIMER0_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER0_DTIFS1

No Description
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_DTIFS1 CONSUMER_TIMER0_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER0_DTIFS2

No Description
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER0_DTIFS2 CONSUMER_TIMER0_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER1_CC0

No Description
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_CC0 CONSUMER_TIMER1_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER1_CC1

No Description
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_CC1 CONSUMER_TIMER1_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER1_CC2

No Description
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_CC2 CONSUMER_TIMER1_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


SYNC_PEEK

No Description
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNC_PEEK SYNC_PEEK read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0VAL CH1VAL CH2VAL CH3VAL

CH0VAL : Channel 0 Current Value
bits : 0 - 0 (1 bit)
access : read-only

CH1VAL : Channel 1 Current Value
bits : 1 - 1 (1 bit)
access : read-only

CH2VAL : Channel 2 Current Value
bits : 2 - 2 (1 bit)
access : read-only

CH3VAL : Channel 3 Current Value
bits : 3 - 3 (1 bit)
access : read-only


CONSUMER_TIMER1_DTI

No Description
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_DTI CONSUMER_TIMER1_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER1_DTIFS1

No Description
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_DTIFS1 CONSUMER_TIMER1_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER1_DTIFS2

No Description
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER1_DTIFS2 CONSUMER_TIMER1_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER2_CC0

No Description
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_CC0 CONSUMER_TIMER2_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER2_CC1

No Description
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_CC1 CONSUMER_TIMER2_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER2_CC2

No Description
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_CC2 CONSUMER_TIMER2_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER2_DTI

No Description
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_DTI CONSUMER_TIMER2_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER2_DTIFS1

No Description
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_DTIFS1 CONSUMER_TIMER2_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER2_DTIFS2

No Description
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER2_DTIFS2 CONSUMER_TIMER2_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER3_CC0

No Description
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_CC0 CONSUMER_TIMER3_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER3_CC1

No Description
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_CC1 CONSUMER_TIMER3_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER3_CC2

No Description
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_CC2 CONSUMER_TIMER3_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_TIMER3_DTI

No Description
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_DTI CONSUMER_TIMER3_DTI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER3_DTIFS1

No Description
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_DTIFS1 CONSUMER_TIMER3_DTIFS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_TIMER3_DTIFS2

No Description
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_TIMER3_DTIFS2 CONSUMER_TIMER3_DTIFS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART0_CLK

No Description
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_CLK CONSUMER_USART0_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_CH0_CTRL

No Description
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH0_CTRL ASYNC_CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


CONSUMER_USART0_IR

No Description
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_IR CONSUMER_USART0_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART0_RX

No Description
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_RX CONSUMER_USART0_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART0_TRIGGER

No Description
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART0_TRIGGER CONSUMER_USART0_TRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART1_CLK

No Description
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART1_CLK CONSUMER_USART1_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART1_IR

No Description
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART1_IR CONSUMER_USART1_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART1_RX

No Description
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART1_RX CONSUMER_USART1_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART1_TRIGGER

No Description
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART1_TRIGGER CONSUMER_USART1_TRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART2_CLK

No Description
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART2_CLK CONSUMER_USART2_CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART2_IR

No Description
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART2_IR CONSUMER_USART2_IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART2_RX

No Description
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART2_RX CONSUMER_USART2_RX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_USART2_TRIGGER

No Description
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_USART2_TRIGGER CONSUMER_USART2_TRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_WDOG0_SRC0

No Description
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG0_SRC0 CONSUMER_WDOG0_SRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_WDOG0_SRC1

No Description
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG0_SRC1 CONSUMER_WDOG0_SRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_WDOG1_SRC0

No Description
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG1_SRC0 CONSUMER_WDOG1_SRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_WDOG1_SRC1

No Description
address_offset : 0x1B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_WDOG1_SRC1 CONSUMER_WDOG1_SRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_CH1_CTRL

No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH1_CTRL ASYNC_CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH2_CTRL

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH2_CTRL ASYNC_CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH3_CTRL

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH3_CTRL ASYNC_CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH4_CTRL

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH4_CTRL ASYNC_CH4_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH5_CTRL

No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH5_CTRL ASYNC_CH5_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH6_CTRL

No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH6_CTRL ASYNC_CH6_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH7_CTRL

No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH7_CTRL ASYNC_CH7_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH8_CTRL

No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH8_CTRL ASYNC_CH8_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH9_CTRL

No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH9_CTRL ASYNC_CH9_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH10_CTRL

No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH10_CTRL ASYNC_CH10_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


ASYNC_CH11_CTRL

No Description
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_CH11_CTRL ASYNC_CH11_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL FNSEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write

FNSEL : Function Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : LOGICAL_ZERO

Logical 0

1 : A_NOR_B

A NOR B

2 : NOT_A_AND_B

(!A) AND B

3 : NOT_A

!A

4 : A_AND_NOT_B

A AND (!B)

5 : NOT_B

!B

6 : A_XOR_B

A XOR B

7 : A_NAND_B

A NAND B

8 : A_AND_B

A AND B

9 : A_XNOR_B

A XNOR B

10 : B

B

11 : NOT_A_OR_B

(!A) OR B

12 : A

A

13 : A_OR_NOT_B

A OR (!B)

14 : A_OR_B

A OR B

15 : LOGICAL_ONE

Logical 1

End of enumeration elements list.


SYNC_CH0_CTRL

No Description
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH0_CTRL SYNC_CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


SYNC_CH1_CTRL

No Description
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH1_CTRL SYNC_CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


SYNC_CH2_CTRL

No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH2_CTRL SYNC_CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


SYNC_CH3_CTRL

No Description
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNC_CH3_CTRL SYNC_CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : NONE


End of enumeration elements list.

SOURCESEL : Source Select
bits : 8 - 14 (7 bit)
access : read-write


CONSUMER_CMU_CALDN

No Description
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CMU_CALDN CONSUMER_CMU_CALDN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_CMU_CALUP

No Description
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_CMU_CALUP CONSUMER_CMU_CALUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_IADC0_SCANTRIGGER

No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_IADC0_SCANTRIGGER CONSUMER_IADC0_SCANTRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_IADC0_SINGLETRIGGER

No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_IADC0_SINGLETRIGGER CONSUMER_IADC0_SINGLETRIGGER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL SPRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write

SPRSSEL : Synchronous Channel Selection
bits : 8 - 9 (2 bit)
access : read-write


CONSUMER_LDMAXBAR_DMAREQ0

No Description
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LDMAXBAR_DMAREQ0 CONSUMER_LDMAXBAR_DMAREQ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LDMAXBAR_DMAREQ1

No Description
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LDMAXBAR_DMAREQ1 CONSUMER_LDMAXBAR_DMAREQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LETIMER0_CLEAR

No Description
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LETIMER0_CLEAR CONSUMER_LETIMER0_CLEAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LETIMER0_START

No Description
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LETIMER0_START CONSUMER_LETIMER0_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_LETIMER0_STOP

No Description
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_LETIMER0_STOP CONSUMER_LETIMER0_STOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_SWPULSE

No Description
address_offset : 0x8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ASYNC_SWPULSE ASYNC_SWPULSE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0PULSE CH1PULSE CH2PULSE CH3PULSE CH4PULSE CH5PULSE CH6PULSE CH7PULSE CH8PULSE CH9PULSE CH10PULSE CH11PULSE

CH0PULSE : Channel pulse
bits : 0 - 0 (1 bit)
access : write-only

CH1PULSE : Channel pulse
bits : 1 - 1 (1 bit)
access : write-only

CH2PULSE : Channel pulse
bits : 2 - 2 (1 bit)
access : write-only

CH3PULSE : Channel pulse
bits : 3 - 3 (1 bit)
access : write-only

CH4PULSE : Channel pulse
bits : 4 - 4 (1 bit)
access : write-only

CH5PULSE : Channel pulse
bits : 5 - 5 (1 bit)
access : write-only

CH6PULSE : Channel pulse
bits : 6 - 6 (1 bit)
access : write-only

CH7PULSE : Channel pulse
bits : 7 - 7 (1 bit)
access : write-only

CH8PULSE : Channel pulse
bits : 8 - 8 (1 bit)
access : write-only

CH9PULSE : Channel pulse
bits : 9 - 9 (1 bit)
access : write-only

CH10PULSE : Channel pulse
bits : 10 - 10 (1 bit)
access : write-only

CH11PULSE : Channel pulse
bits : 11 - 11 (1 bit)
access : write-only


CONSUMER_MODEM_DIN

No Description
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_MODEM_DIN CONSUMER_MODEM_DIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_CLR

No Description
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_CLR CONSUMER_RAC_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_FORCETX

No Description
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_FORCETX CONSUMER_RAC_FORCETX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


ASYNC_SWLEVEL

No Description
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASYNC_SWLEVEL ASYNC_SWLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0LEVEL CH1LEVEL CH2LEVEL CH3LEVEL CH4LEVEL CH5LEVEL CH6LEVEL CH7LEVEL CH8LEVEL CH9LEVEL CH10LEVEL CH11LEVEL

CH0LEVEL : Channel Level
bits : 0 - 0 (1 bit)
access : read-write

CH1LEVEL : Channel Level
bits : 1 - 1 (1 bit)
access : read-write

CH2LEVEL : Channel Level
bits : 2 - 2 (1 bit)
access : read-write

CH3LEVEL : Channel Level
bits : 3 - 3 (1 bit)
access : read-write

CH4LEVEL : Channel Level
bits : 4 - 4 (1 bit)
access : read-write

CH5LEVEL : Channel Level
bits : 5 - 5 (1 bit)
access : read-write

CH6LEVEL : Channel Level
bits : 6 - 6 (1 bit)
access : read-write

CH7LEVEL : Channel Level
bits : 7 - 7 (1 bit)
access : read-write

CH8LEVEL : Channel Level
bits : 8 - 8 (1 bit)
access : read-write

CH9LEVEL : Channel Level
bits : 9 - 9 (1 bit)
access : read-write

CH10LEVEL : Channel Level
bits : 10 - 10 (1 bit)
access : read-write

CH11LEVEL : Channel Level
bits : 11 - 11 (1 bit)
access : read-write


CONSUMER_RAC_RXDIS

No Description
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_RXDIS CONSUMER_RAC_RXDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_RXEN

No Description
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_RXEN CONSUMER_RAC_RXEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_SEQ

No Description
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_SEQ CONSUMER_RAC_SEQ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RAC_TXEN

No Description
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RAC_TXEN CONSUMER_RAC_TXEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RTCC_CC0

No Description
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RTCC_CC0 CONSUMER_RTCC_CC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RTCC_CC1

No Description
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RTCC_CC1 CONSUMER_RTCC_CC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_RTCC_CC2

No Description
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_RTCC_CC2 CONSUMER_RTCC_CC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC0

No Description
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC0 CONSUMER_SE_TAMPERSRC0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC1

No Description
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC1 CONSUMER_SE_TAMPERSRC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC2

No Description
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC2 CONSUMER_SE_TAMPERSRC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC3

No Description
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC3 CONSUMER_SE_TAMPERSRC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC4

No Description
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC4 CONSUMER_SE_TAMPERSRC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC5

No Description
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC5 CONSUMER_SE_TAMPERSRC5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC6

No Description
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC6 CONSUMER_SE_TAMPERSRC6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write


CONSUMER_SE_TAMPERSRC7

No Description
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONSUMER_SE_TAMPERSRC7 CONSUMER_SE_TAMPERSRC7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRSSEL

PRSSEL : Asynchronous Channel Selection
bits : 0 - 3 (4 bit)
access : read-write



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