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LFXO_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

STATUS

CAL

IF

IEN

SYNCBUSY

LOCK

CTRL

CFG


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP Version ID
bits : 0 - 31 (32 bit)
access : read-only


STATUS

No Description
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDY ENS LOCK

RDY : LFXO Ready Status
bits : 0 - 0 (1 bit)
access : read-only

ENS : LFXO Enable Status
bits : 16 - 16 (1 bit)
access : read-only

LOCK : LFXO Locked Status
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : UNLOCKED

LFXO lockable registers are not locked

1 : LOCKED

LFXO lockable registers are locked

End of enumeration elements list.


CAL

Do not write to this register unless CALBSY in SYNCBUSY register is low.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAL CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTUNE GAIN

CAPTUNE : Internal Capacitance Tuning
bits : 0 - 6 (7 bit)
access : read-write

GAIN : LFXO Startup Gain
bits : 8 - 9 (2 bit)
access : read-write


IF

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDY POSEDGE NEGEDGE FAIL

RDY : LFXO Ready Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

POSEDGE : Rising Edge Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

NEGEDGE : Falling Edge Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

FAIL : LFXO Failure Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDY POSEDGE NEGEDGE FAIL

RDY : LFXO Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

POSEDGE : Rising Edge Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

NEGEDGE : Falling Edge Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

FAIL : LFXO Failure Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write


SYNCBUSY

No Description
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCBUSY SYNCBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL

CAL : LFXO Synchronization status
bits : 0 - 0 (1 bit)
access : read-only


LOCK

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Lock Key
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

6688 : UNLOCK

Unlock LFXO lockable registers

End of enumeration elements list.


CTRL

No Description
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FORCEEN DISONDEMAND FAILDETEN FAILDETEM4WUEN

FORCEEN : LFXO Force Enable
bits : 0 - 0 (1 bit)
access : read-write

DISONDEMAND : LFXO Disable On-demand requests
bits : 1 - 1 (1 bit)
access : read-write

FAILDETEN : LFXO Failure Detection Enable
bits : 4 - 4 (1 bit)
access : read-write

FAILDETEM4WUEN : LFXO Failure Detection EM4WU Enable
bits : 5 - 5 (1 bit)
access : read-write


CFG

Do not write to this register unless the oscillator is forced off. The oscillator is forced off if DISONDEMAND is set and FORCEEN is cleared.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGC HIGHAMPL MODE TIMEOUT

AGC : LFXO AGC Enable
bits : 0 - 0 (1 bit)
access : read-write

HIGHAMPL : LFXO High Amplitude Enable
bits : 1 - 1 (1 bit)
access : read-write

MODE : LFXO Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : XTAL

A 32768Hz crystal should be connected to the LF crystal pads. Voltage must not exceed VDDIO.

1 : BUFEXTCLK

An external sine source with minimum amplitude 100mv (zero-to-peak) and maximum amplitude 500mV (zero-to-peak) should be connected in series with LFXTAL_I pin. Minimum voltage should be larger than ground and maximum voltage smaller than VDDIO. The sine source does not need to be ac coupled externally as it is ac couples inside LFXO. LFXTAL_O is free to be used as a general purpose GPIO.

2 : DIGEXTCLK

An external 32KHz CMOS clock should be provided on LFXTAL_I. LFXTAL_O is free to be used as a general purpose GPIO.

End of enumeration elements list.

TIMEOUT : LFXO Start-up Delay
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : CYCLES2

Timeout period of 2 cycles

1 : CYCLES256

Timeout period of 256 cycles

2 : CYCLES1K

Timeout period of 1024 cycles

3 : CYCLES2K

Timeout period of 2048 cycles

4 : CYCLES4K

Timeout period of 4096 cycles

5 : CYCLES8K

Timeout period of 8192 cycles

6 : CYCLES16K

Timeout period of 16384 cycles

7 : CYCLES32K

Timeout period of 32768 cycles

End of enumeration elements list.



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