\n

LDMA_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

SYNCSWSET

CH3_LINK

CH4_CFG

CH4_LOOP

CH4_CTRL

CH4_SRC

CH4_DST

CH4_LINK

SYNCSWCLR

CH5_CFG

CH5_LOOP

CH5_CTRL

CH5_SRC

CH5_DST

CH5_LINK

CH6_CFG

SYNCHWEN

CH6_LOOP

CH6_CTRL

CH6_SRC

CH6_DST

CH6_LINK

CH7_CFG

CH7_LOOP

CH7_CTRL

CH7_SRC

CH7_DST

SYNCHWSEL

CH7_LINK

SYNCSTATUS

CHEN

CHDIS

CHSTATUS

CHBUSY

CHDONE

DBGHALT

SWREQ

EN

REQDIS

REQPEND

LINKLOAD

REQCLEAR

IF

IEN

CH0_CFG

CH0_LOOP

CH0_CTRL

CH0_SRC

CH0_DST

CH0_LINK

CTRL

CH1_CFG

CH1_LOOP

CH1_CTRL

CH1_SRC

CH1_DST

CH1_LINK

CH2_CFG

STATUS

CH2_LOOP

CH2_CTRL

CH2_SRC

CH2_DST

CH2_LINK

CH3_CFG

CH3_LOOP

CH3_CTRL

CH3_SRC

CH3_DST


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IPVERSION
bits : 0 - 7 (8 bit)
access : read-only


SYNCSWSET

No Description
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SYNCSWSET SYNCSWSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCSWSET

SYNCSWSET : DMA SYNC Software Trigger Set
bits : 0 - 7 (8 bit)
access : write-only


No Description
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_LINK CH3_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


CH4_CFG

No Description
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CFG CH4_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


CH4_LOOP

No Description
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_LOOP CH4_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH4_CTRL

No Description
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CTRL CH4_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH4_SRC

No Description
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_SRC CH4_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH4_DST

No Description
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_DST CH4_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


No Description
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_LINK CH4_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


SYNCSWCLR

No Description
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SYNCSWCLR SYNCSWCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCSWCLR

SYNCSWCLR : DMA SYNC Software Trigger Clear
bits : 0 - 7 (8 bit)
access : write-only


CH5_CFG

No Description
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CFG CH5_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


CH5_LOOP

No Description
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_LOOP CH5_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH5_CTRL

No Description
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CTRL CH5_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH5_SRC

No Description
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_SRC CH5_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH5_DST

No Description
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_DST CH5_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


No Description
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_LINK CH5_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


CH6_CFG

No Description
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CFG CH6_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


SYNCHWEN

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCHWEN SYNCHWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCSETEN SYNCCLREN

SYNCSETEN : Hardware Sync Trigger Set Enable
bits : 0 - 7 (8 bit)
access : read-write

SYNCCLREN : Hardware Sync Trigger Clear Enable
bits : 16 - 23 (8 bit)
access : read-write


CH6_LOOP

No Description
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_LOOP CH6_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH6_CTRL

No Description
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CTRL CH6_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH6_SRC

No Description
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_SRC CH6_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH6_DST

No Description
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_DST CH6_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


No Description
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_LINK CH6_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


CH7_CFG

No Description
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CFG CH7_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


CH7_LOOP

No Description
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_LOOP CH7_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH7_CTRL

No Description
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CTRL CH7_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH7_SRC

No Description
address_offset : 0x1B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_SRC CH7_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH7_DST

No Description
address_offset : 0x1BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_DST CH7_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


SYNCHWSEL

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCHWSEL SYNCHWSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCSETEDGE SYNCCLREDGE

SYNCSETEDGE : Hardware Sync Trigger Set Edge Select
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : RISE

Use rising edge detection

1 : FALL

Use falling edge detection

End of enumeration elements list.

SYNCCLREDGE : Hardware Sync Trigger Clear Edge Select
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : RISE

Use rising edge detection

1 : FALL

Use falling edge detection

End of enumeration elements list.


No Description
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_LINK CH7_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


SYNCSTATUS

No Description
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYNCSTATUS SYNCSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCTRIG

SYNCTRIG : sync trig status
bits : 0 - 7 (8 bit)
access : read-only


CHEN

No Description
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHEN CHEN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN

CHEN : Channel Enables
bits : 0 - 7 (8 bit)
access : write-only


CHDIS

No Description
address_offset : 0x28 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CHDIS CHDIS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHDIS

CHDIS : DMA Channel disable
bits : 0 - 7 (8 bit)
access : write-only


CHSTATUS

No Description
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHSTATUS CHSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSTATUS

CHSTATUS : DMA Channel Status
bits : 0 - 7 (8 bit)
access : read-only


CHBUSY

No Description
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CHBUSY CHBUSY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY

BUSY : Channels Busy
bits : 0 - 7 (8 bit)
access : read-only


CHDONE

No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHDONE CHDONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHDONE0 CHDONE1 CHDONE2 CHDONE3 CHDONE4 CHDONE5 CHDONE6 CHDONE7

CHDONE0 : DMA Channel Link done intr flag
bits : 0 - 0 (1 bit)
access : read-write

CHDONE1 : DMA Channel Link done intr flag
bits : 1 - 1 (1 bit)
access : read-write

CHDONE2 : DMA Channel Link done intr flag
bits : 2 - 2 (1 bit)
access : read-write

CHDONE3 : DMA Channel Link done intr flag
bits : 3 - 3 (1 bit)
access : read-write

CHDONE4 : DMA Channel Link done intr flag
bits : 4 - 4 (1 bit)
access : read-write

CHDONE5 : DMA Channel Link done intr flag
bits : 5 - 5 (1 bit)
access : read-write

CHDONE6 : DMA Channel Link done intr flag
bits : 6 - 6 (1 bit)
access : read-write

CHDONE7 : DMA Channel Link done intr flag
bits : 7 - 7 (1 bit)
access : read-write


DBGHALT

No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGHALT DBGHALT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGHALT

DBGHALT : DMA Debug Halt
bits : 0 - 7 (8 bit)
access : read-write


SWREQ

No Description
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWREQ SWREQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWREQ

SWREQ : Software Transfer Requests
bits : 0 - 7 (8 bit)
access : write-only


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : LDMA module enable and disable register
bits : 0 - 0 (1 bit)
access : read-write


REQDIS

No Description
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQDIS REQDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQDIS

REQDIS : DMA Request Disables
bits : 0 - 7 (8 bit)
access : read-write


REQPEND

No Description
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

REQPEND REQPEND read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQPEND

REQPEND : DMA Requests Pending
bits : 0 - 7 (8 bit)
access : read-only


LINKLOAD

No Description
address_offset : 0x48 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

LINKLOAD LINKLOAD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKLOAD

LINKLOAD : DMA Link Loads
bits : 0 - 7 (8 bit)
access : write-only


REQCLEAR

No Description
address_offset : 0x4C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

REQCLEAR REQCLEAR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQCLEAR

REQCLEAR : DMA Request Clear
bits : 0 - 7 (8 bit)
access : write-only


IF

No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE0 DONE1 DONE2 DONE3 DONE4 DONE5 DONE6 DONE7 ERROR

DONE0 : DMA Structure Operation Done
bits : 0 - 0 (1 bit)
access : read-write

DONE1 : DMA Structure Operation Done
bits : 1 - 1 (1 bit)
access : read-write

DONE2 : DMA Structure Operation Done
bits : 2 - 2 (1 bit)
access : read-write

DONE3 : DMA Structure Operation Done
bits : 3 - 3 (1 bit)
access : read-write

DONE4 : DMA Structure Operation Done
bits : 4 - 4 (1 bit)
access : read-write

DONE5 : DMA Structure Operation Done
bits : 5 - 5 (1 bit)
access : read-write

DONE6 : DMA Structure Operation Done
bits : 6 - 6 (1 bit)
access : read-write

DONE7 : DMA Structure Operation Done
bits : 7 - 7 (1 bit)
access : read-write

ERROR : Error Flag
bits : 31 - 31 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHDONE ERROR

CHDONE : Enable or disable the done interrupt
bits : 0 - 7 (8 bit)
access : read-write

ERROR : Enable or disable the error interrupt
bits : 31 - 31 (1 bit)
access : read-write


CH0_CFG

No Description
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CFG CH0_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


CH0_LOOP

No Description
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_LOOP CH0_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH0_CTRL

No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CTRL CH0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH0_SRC

No Description
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_SRC CH0_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH0_DST

No Description
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_DST CH0_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


No Description
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_LINK CH0_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


CTRL

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUMFIXED CORERST

NUMFIXED : Number of Fixed Priority Channels
bits : 24 - 28 (5 bit)
access : read-write

CORERST : Reset DMA controller
bits : 31 - 31 (1 bit)
access : read-write


CH1_CFG

No Description
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CFG CH1_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


CH1_LOOP

No Description
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_LOOP CH1_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH1_CTRL

No Description
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CTRL CH1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH1_SRC

No Description
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_SRC CH1_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH1_DST

No Description
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_DST CH1_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


No Description
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_LINK CH1_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


CH2_CFG

No Description
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CFG CH2_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


STATUS

No Description
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANYBUSY ANYREQ CHGRANT CHERROR FIFOLEVEL CHNUM

ANYBUSY : Any DMA Channel Busy
bits : 0 - 0 (1 bit)
access : read-only

ANYREQ : Any DMA Channel Request Pending
bits : 1 - 1 (1 bit)
access : read-only

CHGRANT : Granted Channel Number
bits : 3 - 7 (5 bit)
access : read-only

CHERROR : Errant Channel Number
bits : 8 - 12 (5 bit)
access : read-only

FIFOLEVEL : FIFO Level
bits : 16 - 20 (5 bit)
access : read-only

CHNUM : Number of Channels
bits : 24 - 28 (5 bit)
access : read-only


CH2_LOOP

No Description
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_LOOP CH2_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH2_CTRL

No Description
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CTRL CH2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH2_SRC

No Description
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_SRC CH2_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH2_DST

No Description
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_DST CH2_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write


No Description
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_LINK CH2_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINKMODE LINK LINKADDR

LINKMODE : Link Structure Addressing Mode
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The LINKADDR field of LDMA_CHx_LINK contains the absolute address of the linked descriptor.

1 : RELATIVE

The LINKADDR field of LDMA_CHx_LINK contains the relative offset of the linked descriptor.

End of enumeration elements list.

LINK : Link Next Structure
bits : 1 - 1 (1 bit)
access : read-write

LINKADDR : Link Structure Address
bits : 2 - 31 (30 bit)
access : read-write


CH3_CFG

No Description
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CFG CH3_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARBSLOTS SRCINCSIGN DSTINCSIGN

ARBSLOTS : Arbitration Slot Number Select
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : ONE

One arbitration slot selected

1 : TWO

Two arbitration slots selected

2 : FOUR

Four arbitration slots selected

3 : EIGHT

Eight arbitration slots selected

End of enumeration elements list.

SRCINCSIGN : Source Address Increment Sign
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment source address

1 : NEGATIVE

Decrement source address

End of enumeration elements list.

DSTINCSIGN : Destination Address Increment Sign
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : POSITIVE

Increment destination address

1 : NEGATIVE

Decrement destination address

End of enumeration elements list.


CH3_LOOP

No Description
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_LOOP CH3_LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOPCNT

LOOPCNT : Linked Structure Sequence Loop Counter
bits : 0 - 7 (8 bit)
access : read-write


CH3_CTRL

No Description
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CTRL CH3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRUCTTYPE STRUCTREQ XFERCNT BYTESWAP BLOCKSIZE DONEIEN REQMODE DECLOOPCNT IGNORESREQ SRCINC SIZE DSTINC SRCMODE DSTMODE

STRUCTTYPE : DMA Structure Type
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : TRANSFER

DMA transfer structure type selected.

1 : SYNCHRONIZE

Synchronization structure type selected.

2 : WRITE

Write immediate value structure type selected.

End of enumeration elements list.

STRUCTREQ : Structure DMA Transfer Request
bits : 3 - 3 (1 bit)
access : read-only

XFERCNT : DMA Unit Data Transfer Count
bits : 4 - 14 (11 bit)
access : read-write

BYTESWAP : Endian Byte Swap
bits : 15 - 15 (1 bit)
access : read-write

BLOCKSIZE : Block Transfer Size
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : UNIT1

One unit transfer per arbitration

1 : UNIT2

Two unit transfers per arbitration

2 : UNIT3

Three unit transfers per arbitration

3 : UNIT4

Four unit transfers per arbitration

4 : UNIT6

Six unit transfers per arbitration

5 : UNIT8

Eight unit transfers per arbitration

7 : UNIT16

Sixteen unit transfers per arbitration

9 : UNIT32

32 unit transfers per arbitration

10 : UNIT64

64 unit transfers per arbitration

11 : UNIT128

128 unit transfers per arbitration

12 : UNIT256

256 unit transfers per arbitration

13 : UNIT512

512 unit transfers per arbitration

14 : UNIT1024

1024 unit transfers per arbitration

15 : ALL

Transfer all units as specified by the XFRCNT field

End of enumeration elements list.

DONEIEN : DMA Operation Done Interrupt Flag Set En
bits : 20 - 20 (1 bit)
access : read-write

REQMODE : DMA Request Transfer Mode Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

0 : BLOCK

The LDMA transfers one BLOCKSIZE per transfer request.

1 : ALL

One transfer request transfers all units as defined by the XFRCNT field.

End of enumeration elements list.

DECLOOPCNT : Decrement Loop Count
bits : 22 - 22 (1 bit)
access : read-write

IGNORESREQ : Ignore Sreq
bits : 23 - 23 (1 bit)
access : read-write

SRCINC : Source Address Increment Size
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment source address by one unit data size after each read

1 : TWO

Increment source address by two unit data sizes after each read

2 : FOUR

Increment source address by four unit data sizes after each read

3 : NONE

Do not increment the source address. In this mode reads are made from a fixed source address, for example reading FIFO.

End of enumeration elements list.

SIZE : Unit Data Transfer Size
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

0 : BYTE

Each unit transfer is a byte

1 : HALFWORD

Each unit transfer is a half-word

2 : WORD

Each unit transfer is a word

End of enumeration elements list.

DSTINC : Destination Address Increment Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : ONE

Increment destination address by one unit data size after each write

1 : TWO

Increment destination address by two unit data sizes after each write

2 : FOUR

Increment destination address by four unit data sizes after each write

3 : NONE

Do not increment the destination address. Writes are made to a fixed destination address, for example writing to a FIFO.

End of enumeration elements list.

SRCMODE : Source Addressing Mode
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The SRCADDR field of LDMA_CHx_SRC contains the absolute address of the source data.

1 : RELATIVE

The SRCADDR field of LDMA_CHx_SRC contains the relative offset of the source data.

End of enumeration elements list.

DSTMODE : Destination Addressing Mode
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

0 : ABSOLUTE

The DSTADDR field of LDMA_CHx_DST contains the absolute address of the destination data.

1 : RELATIVE

The DSTADDR field of LDMA_CHx_DST contains the relative offset of the destination data.

End of enumeration elements list.


CH3_SRC

No Description
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_SRC CH3_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRCADDR

SRCADDR : Source Data Address
bits : 0 - 31 (32 bit)
access : read-write


CH3_DST

No Description
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_DST CH3_DST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSTADDR

DSTADDR : Destination Data Address
bits : 0 - 31 (32 bit)
access : read-write



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