\n

LDMAXBAR_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CH0_REQSEL

CH4_REQSEL

CH5_REQSEL

CH6_REQSEL

CH7_REQSEL

CH1_REQSEL

CH2_REQSEL

CH3_REQSEL


CH0_REQSEL

No Description
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_REQSEL CH0_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH4_REQSEL

No Description
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_REQSEL CH4_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH5_REQSEL

No Description
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_REQSEL CH5_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH6_REQSEL

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_REQSEL CH6_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH7_REQSEL

No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_REQSEL CH7_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH1_REQSEL

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_REQSEL CH1_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH2_REQSEL

No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_REQSEL CH2_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write


CH3_REQSEL

No Description
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_REQSEL CH3_REQSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGSEL SOURCESEL

SIGSEL : Signal Select
bits : 0 - 3 (4 bit)
access : read-write

SOURCESEL : Source Select
bits : 16 - 21 (6 bit)
access : read-write



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