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RFCRC_S

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

CMD

INPUTDATA

INIT

DATA

POLY

EN

CTRL

STATUS


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only


CMD

No Description
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CMD CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INITIALIZE

INITIALIZE : Initialize CRC
bits : 0 - 0 (1 bit)
access : write-only


INPUTDATA

No Description
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INPUTDATA INPUTDATA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTDATA

INPUTDATA : Input Data
bits : 0 - 15 (16 bit)
access : write-only


INIT

No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INIT INIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT

INIT : CRC Initialization Value
bits : 0 - 31 (32 bit)
access : read-write


DATA

No Description
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : CRC Data Register
bits : 0 - 31 (32 bit)
access : read-only


POLY

No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POLY POLY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POLY

POLY : CRC Polynomial Value
bits : 0 - 31 (32 bit)
access : read-write


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write


CTRL

No Description
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INPUTINV OUTPUTINV CRCWIDTH INPUTBITORDER BYTEREVERSE BITREVERSE BITSPERWORD PADCRCINPUT

INPUTINV : Input Invert
bits : 0 - 0 (1 bit)
access : read-write

OUTPUTINV : Output Invert
bits : 1 - 1 (1 bit)
access : read-write

CRCWIDTH : None
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0 : CRCWIDTH8

8 bit (1 Byte) CRC code

1 : CRCWIDTH16

16 bit (2 Bytes) CRC code

2 : CRCWIDTH24

24 bit (3 Bytes) CRC code

3 : CRCWIDTH32

32 bit (4 Bytes) CRC code

End of enumeration elements list.

INPUTBITORDER : CRC input bit ordering setting
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : LSBFIRST

The least significant data bit is first input to the CRC generator.

1 : MSBFIRST

The most significant data bit is first input to the CRC generator.

End of enumeration elements list.

BYTEREVERSE : Reverse CRC byte ordering over air
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

The least significant byte of the CRC register is transferred first over air via the Frame Controller.

1 : REVERSED

The most significant byte of the CRC register is transferred first over air via the Frame Controller.

End of enumeration elements list.

BITREVERSE : Reverse CRC bit ordering over air
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : NORMAL

The bit ordering of CRC data is the same as defined by the BITORDER field in the Frame Controller.

1 : REVERSED

The bit ordering of CRC data is the opposite as defined by the BITORDER field in the Frame Controller.

End of enumeration elements list.

BITSPERWORD : Number of bits per input word
bits : 8 - 11 (4 bit)
access : read-write

PADCRCINPUT : Pad CRC input data
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : X0

No zero-padding of CRC input data is applied

1 : X1

CRC input data is zero-padded, such that the number of bytes over which the CRC value is calculated at least equals the length of the calculated CRC value.

End of enumeration elements list.


STATUS

No Description
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY

BUSY : CRC Running
bits : 0 - 0 (1 bit)
access : read-only



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