\n

AGC_NS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IPVERSION

RSSI

FRAMERSSI

CTRL0

CTRL1

CTRL2

CTRL3

RSSISTEPTHR

IF

EN

IEN

GAINRANGE

AGCPERIOD

HICNTREGION

STEPDWN

GAINSTEPLIM

PNRFATT0

PNRFATT1

PNRFATT2

LNAMIXCODE0

LNAMIXCODE1

PGACODE0

STATUS0

PGACODE1

LBT

MIRRORIF


IPVERSION

No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IPVERSION IPVERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPVERSION

IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only


RSSI

No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RSSI RSSI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSSIFRAC RSSIINT

RSSIFRAC : RSSI fractional part
bits : 6 - 7 (2 bit)
access : read-only

RSSIINT : RSSI integer part
bits : 8 - 15 (8 bit)
access : read-only


FRAMERSSI

No Description
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRAMERSSI FRAMERSSI read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAMERSSIFRAC FRAMERSSIINT

FRAMERSSIFRAC : FRAMERSSI fractional part
bits : 6 - 7 (2 bit)
access : read-only

FRAMERSSIINT : FRAMERSSI integer part
bits : 8 - 15 (8 bit)
access : read-only


CTRL0

No Description
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWRTARGET MODE RSSISHIFT DISCFLOOPADJ AGCCLKUNDIVREQ DISRESETCHPWR ADCATTENMODE ADCATTENCODE ENRSSIRESET DSADISCFLOOP DISPNGAINUP DISPNDWNCOMP AGCRST

PWRTARGET : Power Target
bits : 0 - 7 (8 bit)
access : read-write

MODE : Mode
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : CONT

AGC loop is adjusting gain continuously.

1 : LOCKPREDET

Gain is locked once a preamble is detected.

2 : LOCKFRAMEDET

Gain is locked once a sync word is detected.

3 : LOCKDSA

Gain is locked once DSA is detected.

End of enumeration elements list.

RSSISHIFT : RSSI Shift
bits : 11 - 18 (8 bit)
access : read-write

DISCFLOOPADJ : Disable gain adjustment by CFLOOP
bits : 19 - 19 (1 bit)
access : read-write

AGCCLKUNDIVREQ : Enable CLKUNDIV to AGC
bits : 21 - 21 (1 bit)
access : read-write

DISRESETCHPWR : Disable Reset of CHPWR
bits : 22 - 22 (1 bit)
access : read-write

ADCATTENMODE : ADC Attenuator mode
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

0 : DISABLE

ADC attenuator back-off will not be done by AGC

1 : NOTMAXGAIN

ADC attenuator is backed-off if rxgain is NOT MAXGAIN

End of enumeration elements list.

ADCATTENCODE : ADC Attenuator code
bits : 25 - 26 (2 bit)
access : read-write

ENRSSIRESET : Enables reset of RSSI and CCA
bits : 27 - 27 (1 bit)
access : read-write

DSADISCFLOOP : Disable channel filter loop
bits : 28 - 28 (1 bit)
access : read-write

DISPNGAINUP : Disable PN gain increase
bits : 29 - 29 (1 bit)
access : read-write

DISPNDWNCOMP : Disable PN gain decrease compensation
bits : 30 - 30 (1 bit)
access : read-write

AGCRST : AGC reset
bits : 31 - 31 (1 bit)
access : read-write


CTRL1

No Description
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCATHRSH RSSIPERIOD PWRPERIOD SUBPERIOD SUBNUM SUBDEN SUBINT

CCATHRSH : Clear Channel Assessment (CCA) Threshold
bits : 0 - 7 (8 bit)
access : read-write

RSSIPERIOD : RSSI measure period
bits : 8 - 11 (4 bit)
access : read-write

PWRPERIOD : AGC measure period
bits : 12 - 14 (3 bit)
access : read-write

SUBPERIOD : Subperiod
bits : 15 - 15 (1 bit)
access : read-write

SUBNUM : Subperiod numerator
bits : 16 - 20 (5 bit)
access : read-write

SUBDEN : Subperiod denominator
bits : 21 - 25 (5 bit)
access : read-write

SUBINT : Subperiod integer
bits : 26 - 31 (6 bit)
access : read-write


CTRL2

No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASEL SAFEMODE SAFEMODETHD REHICNTTHD RELOTHD RELBYCHPWR RELTARGETPWR PRSDEBUGEN DISRFPKD

DMASEL : DMA select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : RSSI

RSSI

1 : GAIN

Gain

End of enumeration elements list.

SAFEMODE : AGC safe mode
bits : 1 - 1 (1 bit)
access : read-write

SAFEMODETHD : Enter threshold
bits : 2 - 4 (3 bit)
access : read-write

REHICNTTHD : Exit threshold based on HICNT
bits : 5 - 12 (8 bit)
access : read-write

RELOTHD : Exit threshold based on Release Counter
bits : 13 - 15 (3 bit)
access : read-write

RELBYCHPWR : Safe mode release mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : LO_CNT

Increment counter if IFPKD_LO_LAT signal is not set.

1 : PWR

Increment counter if channel power is below RELTARGETPWR.

2 : LO_CNT_PWR

Increment if either LO_CNT or PWR.

3 : LO_CNT_AND_PWR

Increment if both LO_CNT and PWR.

End of enumeration elements list.

RELTARGETPWR : Safe Mode Release Power Target
bits : 18 - 25 (8 bit)
access : read-write

PRSDEBUGEN : PRS Debug Enable
bits : 30 - 30 (1 bit)
access : read-write

DISRFPKD : Disable RF PEAKDET
bits : 31 - 31 (1 bit)
access : read-write


CTRL3

No Description
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3 CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IFPKDDEB IFPKDDEBTHD IFPKDDEBPRD IFPKDDEBRST RFPKDDEB RFPKDDEBTHD RFPKDDEBPRD RFPKDDEBRST

IFPKDDEB : IF PEAKDET debounce mode enable
bits : 0 - 0 (1 bit)
access : read-write

IFPKDDEBTHD : IF PEAKDET debance thrshold
bits : 1 - 2 (2 bit)
access : read-write

IFPKDDEBPRD : IF PEAKDET debance period
bits : 3 - 8 (6 bit)
access : read-write

IFPKDDEBRST : IF PEAKDET debounce period
bits : 9 - 12 (4 bit)
access : read-write

RFPKDDEB : RF PEAKDET debounce mode enable
bits : 13 - 13 (1 bit)
access : read-write

RFPKDDEBTHD : RF PEAKDET debance thrshold
bits : 14 - 15 (2 bit)
access : read-write

RFPKDDEBPRD : RF PEAKDET debance period
bits : 16 - 21 (6 bit)
access : read-write

RFPKDDEBRST : RFPKD_LAT debounce reset delay
bits : 22 - 25 (4 bit)
access : read-write


RSSISTEPTHR

No Description
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSSISTEPTHR RSSISTEPTHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSSTEPTHR NEGSTEPTHR STEPPER DEMODRESTARTPER DEMODRESTARTTHR RSSIFAST

POSSTEPTHR : Positive Step Threshold
bits : 0 - 7 (8 bit)
access : read-write

NEGSTEPTHR : Negative Step Threshold
bits : 8 - 15 (8 bit)
access : read-write

STEPPER : Step Period
bits : 16 - 16 (1 bit)
access : read-write

DEMODRESTARTPER : Demodulator Restart Period
bits : 17 - 20 (4 bit)
access : read-write

DEMODRESTARTTHR : Demodulator Restart Threshold
bits : 21 - 28 (8 bit)
access : read-write

RSSIFAST : RSSI fast startup
bits : 29 - 29 (1 bit)
access : read-write


IF

No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF IF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSSIVALID CCA RSSIPOSSTEP RSSINEGSTEP SHORTRSSIPOSSTEP

RSSIVALID : RSSI Value is Valid
bits : 0 - 0 (1 bit)
access : read-write

CCA : Clear Channel Assessment
bits : 2 - 2 (1 bit)
access : read-write

RSSIPOSSTEP : Positive RSSI Step Detected
bits : 3 - 3 (1 bit)
access : read-write

RSSINEGSTEP : Negative RSSI Step Detected
bits : 4 - 4 (1 bit)
access : read-write

SHORTRSSIPOSSTEP : Short-term Positive RSSI Step Detected
bits : 6 - 6 (1 bit)
access : read-write


EN

No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write


IEN

No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSSIVALID CCA RSSIPOSSTEP RSSINEGSTEP SHORTRSSIPOSSTEP

RSSIVALID : RSSIVALID Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

CCA : CCA Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

RSSIPOSSTEP : RSSIPOSSTEP Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

RSSINEGSTEP : RSSINEGSTEP Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

SHORTRSSIPOSSTEP : SHORTRSSIPOSSTEP Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write


GAINRANGE

No Description
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAINRANGE GAINRANGE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAINDEXBORDER PGAINDEXBORDER GAININCSTEP PNGAINSTEP LATCHEDHISTEP HIPWRTHD BOOSTLNA LNABWADJ

LNAINDEXBORDER : LNA gain border
bits : 0 - 3 (4 bit)
access : read-write

PGAINDEXBORDER : PGA gain border
bits : 4 - 7 (4 bit)
access : read-write

GAININCSTEP : AGC gain increase step size
bits : 8 - 11 (4 bit)
access : read-write

PNGAINSTEP : PN Gain Step size
bits : 12 - 15 (4 bit)
access : read-write

LATCHEDHISTEP : Ltached Hi step size
bits : 16 - 19 (4 bit)
access : read-write

HIPWRTHD : High power detect thrshold
bits : 20 - 25 (6 bit)
access : read-write

BOOSTLNA : LNA GAIN BOOST mode
bits : 26 - 26 (1 bit)
access : read-write

LNABWADJ : LNA BW ADJUST
bits : 27 - 27 (1 bit)
access : read-write


AGCPERIOD

No Description
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AGCPERIOD AGCPERIOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIODHI PERIODLO MAXHICNTTHD SETTLETIMEIF SETTLETIMERF

PERIODHI : AGC measure period hi
bits : 0 - 7 (8 bit)
access : read-write

PERIODLO : AGC measure period low
bits : 8 - 15 (8 bit)
access : read-write

MAXHICNTTHD : max hi-countrer threshold
bits : 16 - 23 (8 bit)
access : read-write

SETTLETIMEIF : IF peak Detector settling time
bits : 24 - 27 (4 bit)
access : read-write

SETTLETIMERF : RF peak Detector settling time
bits : 28 - 31 (4 bit)
access : read-write


HICNTREGION

No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HICNTREGION HICNTREGION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HICNTREGION0 HICNTREGION1 HICNTREGION2 HICNTREGION3 HICNTREGION4

HICNTREGION0 : AGC HICNT to step size map region 0
bits : 0 - 3 (4 bit)
access : read-write

HICNTREGION1 : AGC HICNT to step size map region 1
bits : 4 - 7 (4 bit)
access : read-write

HICNTREGION2 : AGC HICNT to step size map region 2
bits : 8 - 15 (8 bit)
access : read-write

HICNTREGION3 : AGC HICNT to step size map region 3
bits : 16 - 23 (8 bit)
access : read-write

HICNTREGION4 : AGC HICNT to step size map region 4
bits : 24 - 31 (8 bit)
access : read-write


STEPDWN

No Description
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STEPDWN STEPDWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STEPDWN0 STEPDWN1 STEPDWN2 STEPDWN3 STEPDWN4 STEPDWN5

STEPDWN0 : AGC gain step size 0
bits : 0 - 2 (3 bit)
access : read-write

STEPDWN1 : AGC gain step size 1
bits : 3 - 5 (3 bit)
access : read-write

STEPDWN2 : AGC gain step size 2
bits : 6 - 8 (3 bit)
access : read-write

STEPDWN3 : AGC gain step size 3
bits : 9 - 11 (3 bit)
access : read-write

STEPDWN4 : AGC gain step size 4
bits : 12 - 14 (3 bit)
access : read-write

STEPDWN5 : AGC gain step size 5
bits : 15 - 17 (3 bit)
access : read-write


GAINSTEPLIM

No Description
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAINSTEPLIM GAINSTEPLIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFLOOPSTEPMAX CFLOOPDEL HYST MAXPWRVAR TRANRSTAGC

CFLOOPSTEPMAX : Maximum step in slow loop
bits : 0 - 4 (5 bit)
access : read-write

CFLOOPDEL : Channel Filter Loop Delay
bits : 5 - 11 (7 bit)
access : read-write

HYST : Hysteresis
bits : 12 - 15 (4 bit)
access : read-write

MAXPWRVAR : Maximum Power Variation
bits : 16 - 23 (8 bit)
access : read-write

TRANRSTAGC : power transient detector Reset AGC
bits : 24 - 24 (1 bit)
access : read-write


PNRFATT0

No Description
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PNRFATT0 PNRFATT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXRFATT1 LNAMIXRFATT2 LNAMIXRFATT3 LNAMIXRFATT4 LNAMIXRFATT5

LNAMIXRFATT1 : PN RF attenuation code for index 1
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXRFATT2 : PN RF attenuation code for index 2
bits : 6 - 11 (6 bit)
access : read-write

LNAMIXRFATT3 : PN RF attenuation code for index 3
bits : 12 - 17 (6 bit)
access : read-write

LNAMIXRFATT4 : PN RF attenuation code for index 4
bits : 18 - 23 (6 bit)
access : read-write

LNAMIXRFATT5 : PN RF attenuation code for index 5
bits : 24 - 29 (6 bit)
access : read-write


PNRFATT1

No Description
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PNRFATT1 PNRFATT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXRFATT6 LNAMIXRFATT7 LNAMIXRFATT8 LNAMIXRFATT9 LNAMIXRFATT10

LNAMIXRFATT6 : PN RF attenuation code for index 6
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXRFATT7 : PN RF attenuation code for index 7
bits : 6 - 11 (6 bit)
access : read-write

LNAMIXRFATT8 : PN RF attenuation code for index 8
bits : 12 - 17 (6 bit)
access : read-write

LNAMIXRFATT9 : PN RF attenuation code for index 9
bits : 18 - 23 (6 bit)
access : read-write

LNAMIXRFATT10 : PN RF attenuation code for index 10
bits : 24 - 29 (6 bit)
access : read-write


PNRFATT2

No Description
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PNRFATT2 PNRFATT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXRFATT11 LNAMIXRFATT12 LNAMIXRFATT13 LNAMIXRFATT14

LNAMIXRFATT11 : PN RF attenuation code for index 11
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXRFATT12 : PN RF attenuation code for index 12
bits : 6 - 11 (6 bit)
access : read-write

LNAMIXRFATT13 : PN RF attenuation code for index 13
bits : 12 - 17 (6 bit)
access : read-write

LNAMIXRFATT14 : PN RF attenuation code for index 14
bits : 18 - 23 (6 bit)
access : read-write


LNAMIXCODE0

No Description
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXCODE0 LNAMIXCODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXSLICE1 LNAMIXSLICE2 LNAMIXSLICE3 LNAMIXSLICE4 LNAMIXSLICE5

LNAMIXSLICE1 : LNA/MIX slice code for index 1
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXSLICE2 : LNA/MIX slice code for index 2
bits : 6 - 11 (6 bit)
access : read-write

LNAMIXSLICE3 : LNA/MIX slice code for index 3
bits : 12 - 17 (6 bit)
access : read-write

LNAMIXSLICE4 : LNA/MIX slice code for index 4
bits : 18 - 23 (6 bit)
access : read-write

LNAMIXSLICE5 : LNA/MIX slice code for index 5
bits : 24 - 29 (6 bit)
access : read-write


LNAMIXCODE1

No Description
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNAMIXCODE1 LNAMIXCODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LNAMIXSLICE6 LNAMIXSLICE7 LNAMIXSLICE8 LNAMIXSLICE9 LNAMIXSLICE10

LNAMIXSLICE6 : LNA/MIX slice code for index 6
bits : 0 - 5 (6 bit)
access : read-write

LNAMIXSLICE7 : LNA/MIX slice code for index 7
bits : 6 - 11 (6 bit)
access : read-write

LNAMIXSLICE8 : LNA/MIX slice code for index 8
bits : 12 - 17 (6 bit)
access : read-write

LNAMIXSLICE9 : LNA/MIX slice code for index 9
bits : 18 - 23 (6 bit)
access : read-write

LNAMIXSLICE10 : LNA/MIX slice code for index 10
bits : 24 - 29 (6 bit)
access : read-write


PGACODE0

No Description
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGACODE0 PGACODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGAGAIN1 PGAGAIN2 PGAGAIN3 PGAGAIN4 PGAGAIN5 PGAGAIN6 PGAGAIN7 PGAGAIN8

PGAGAIN1 : PGA GAIN code for index 1
bits : 0 - 3 (4 bit)
access : read-write

PGAGAIN2 : PGA GAIN code for index 2
bits : 4 - 7 (4 bit)
access : read-write

PGAGAIN3 : PGA GAIN code for index 3
bits : 8 - 11 (4 bit)
access : read-write

PGAGAIN4 : PGA GAIN code for index 4
bits : 12 - 15 (4 bit)
access : read-write

PGAGAIN5 : PGA GAIN code for index 5
bits : 16 - 19 (4 bit)
access : read-write

PGAGAIN6 : PGA GAIN code for index 6
bits : 20 - 23 (4 bit)
access : read-write

PGAGAIN7 : PGA GAIN code for index 7
bits : 24 - 27 (4 bit)
access : read-write

PGAGAIN8 : PGA GAIN code for index 8
bits : 28 - 31 (4 bit)
access : read-write


STATUS0

No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS0 STATUS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAININDEX RFPKDLAT IFPKDLOLAT IFPKDHILAT CCA GAINOK PGAINDEX LNAINDEX PNINDEX ADCINDEX

GAININDEX : Gain Table Index
bits : 0 - 5 (6 bit)
access : read-only

RFPKDLAT : RFPKD Latch
bits : 6 - 6 (1 bit)
access : read-only

IFPKDLOLAT : IFPKD Lo threshold pass Latch
bits : 7 - 7 (1 bit)
access : read-only

IFPKDHILAT : IFPKD Hi threshold pass Latch
bits : 8 - 8 (1 bit)
access : read-only

CCA : Clear Channel Assessment
bits : 9 - 9 (1 bit)
access : read-only

GAINOK : Gain OK
bits : 10 - 10 (1 bit)
access : read-only

PGAINDEX : PGA GAIN INDEX
bits : 11 - 14 (4 bit)
access : read-only

LNAINDEX : LNA GAIN INDEX
bits : 15 - 18 (4 bit)
access : read-only

PNINDEX : PN GAIN INDEX
bits : 19 - 22 (4 bit)
access : read-only

ADCINDEX : ADC Attenuator INDEX
bits : 23 - 24 (2 bit)
access : read-write


PGACODE1

No Description
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PGACODE1 PGACODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PGAGAIN9 PGAGAIN10 PGAGAIN11

PGAGAIN9 : PGA GAIN code for index 9
bits : 0 - 3 (4 bit)
access : read-write

PGAGAIN10 : PGA GAIN code for index 10
bits : 4 - 7 (4 bit)
access : read-write

PGAGAIN11 : PGA GAIN code for index 11
bits : 8 - 11 (4 bit)
access : read-write


LBT

No Description
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LBT LBT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCARSSIPERIOD ENCCARSSIPERIOD ENCCAGAINREDUCED ENCCARSSIMAX

CCARSSIPERIOD : RSSI Period during CCA measurements
bits : 0 - 3 (4 bit)
access : read-write

ENCCARSSIPERIOD : RSSI PERIOD during CCA measurements
bits : 4 - 4 (1 bit)
access : read-write

ENCCAGAINREDUCED : CCA gain reduced
bits : 5 - 5 (1 bit)
access : read-write

ENCCARSSIMAX : Use RSSIMAX to indicate CCA
bits : 6 - 6 (1 bit)
access : read-write


MIRRORIF

No Description
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIRRORIF MIRRORIF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSSIPOSSTEPM RSSINEGSTEPM SHORTRSSIPOSSTEPM IFMIRRORCLEAR

RSSIPOSSTEPM : Positive RSSI Step Detected
bits : 0 - 0 (1 bit)
access : read-only

RSSINEGSTEPM : Negative RSSI Step Detected
bits : 1 - 1 (1 bit)
access : read-only

SHORTRSSIPOSSTEPM : Short-term Positive RSSI Step Detected
bits : 2 - 2 (1 bit)
access : read-only

IFMIRRORCLEAR : Clear bit for the AGC IF MIRROR Register
bits : 3 - 3 (1 bit)
access : read-write



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