Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP Version
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKTHRESHOLD : Frequency synthesizer lock threshold
bits : 0 - 2 (3 bit)
access : read-write
PRSMUX0 : PRS output mux 0 selector
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
PRS output 0 is disabled
1 : INLOCK
Synthesizer is in lock
2 : LOCK_WINDOW
PLL Lock Window, sampled by PFD
3 : FPLL
Divided PLL clock
4 : VCCMP_HI
VCO voltage high detected
5 : VCO_AMPLITUDE_OK
Obsolete. Read returns 1.
6 : VCO_DET_OUT_D
Obsolete. Read returns 0.
End of enumeration elements list.
PRSMUX1 : PRS output mux 1 selector
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0 : DISABLED
PRS output 1 is disabled
1 : AUXINLOCK
Obsolete. read returns 0.
2 : REF_IS_LEADING
Disabled. Read returns 0.
3 : FPLL
Divided PLL clock
4 : VCCMP_LOW
VCO voltage low detected
5 : MMD_PRESCALER_RESET_N
MMD prescaler reset, active low
6 : CLK_SYNTH_DIV2
MMD next denom output, corresponding to the delta-sigma clock, divided by 2.
End of enumeration elements list.
MMDRSTNOVERRIDEEN : Enable MMD reset override
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable MMD reset override
1 : ENABLE
Enable MMD reset override
End of enumeration elements list.
MMDMANRSTN : Manual MMD reset
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : RESET
Reset MMD and DSM logic
1 : NORESET
Allow MMD and DSM to run
End of enumeration elements list.
No Description
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCDACVAL : Control voltage to VCO
bits : 0 - 5 (6 bit)
access : read-write
VCDACEN : Enable VCDAC
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
VC DAC disabled
1 : ENABLE
VC DAC enabled
End of enumeration elements list.
LPFEN : LPF Enable Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable LPF
1 : ENABLE
Enable LPF
End of enumeration elements list.
LPFQSEN : LPF Quickstart Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable LPF
1 : ENABLE
Enable LPF
End of enumeration elements list.
No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ : RF Carrier Frequency.
bits : 0 - 27 (28 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFFREQ : IF used in receive mode
bits : 0 - 19 (20 bit)
access : read-write
LOSIDE : Configure LO in receive
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : LOW
The local oscillator (LO) is lower in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to NORMAL and DIGIQSWAPEN must be cleared.
1 : HIGH
The local oscillator (LO) is higher in frequency than the receive RF channel. In MODEM_MIXCTRL the ANAMIXMODE field must be set to CONJUGATE and DIGIQSWAPEN must be set.
End of enumeration elements list.
No Description
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LODIVFREQCTRL : Frequency division
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
1 : LODIV1
Divide LO frequency by 1.
2 : LODIV2
Divide LO frequency by 2.
3 : LODIV3
Divide LO frequency by 3.
4 : LODIV4
Divide LO frequency by 4.
5 : LODIV5
Divide LO frequency by 5.
7 : LODIV7
Divide LO frequency by 7.
19 : LODIV6
Divide LO frequency by 6.
20 : LODIV8
Divide LO frequency by 8.
21 : LODIV10
Divide LO frequency by 10.
23 : LODIV14
Divide LO frequency by 14.
27 : LODIV9
Divide LO frequency by 9.
28 : LODIV12
Divide LO frequency by 12.
29 : LODIV15
Divide LO frequency by 15.
36 : LODIV16
Divide LO frequency by 16.
37 : LODIV20
Divide LO frequency by 20.
155 : LODIV18
Divide LO frequency by 18.
156 : LODIV24
Divide LO frequency by 24.
End of enumeration elements list.
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable peripheral clock to this module
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNO : Channel number
bits : 0 - 5 (6 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSP : Channel spacing
bits : 0 - 17 (18 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALOFFSET : Carrier calibration offset
bits : 0 - 14 (15 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCOTUNING : VCO capacitor array calibration value.
bits : 0 - 10 (11 bit)
access : read-write
VCAPSEL : VCO varactor cap select
bits : 11 - 15 (5 bit)
access : read-write
No Description
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VCOKVCOARSE : VCO varactor coarse gain setting
bits : 0 - 3 (4 bit)
access : read-write
VCOKVFINE : VCO varactor fine gain setting
bits : 4 - 7 (4 bit)
access : read-write
No Description
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : Synthesizer locked Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
UNLOCKED : Synthesizer unlocked Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
CAPCALDONE : Capacitor calibration Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
VCOHIGH : VCO high voltage Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
VCOLOW : VCO low voltage Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write
LOCNTDONE : LOCNT measurement done Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INLOCK : RF Synthesizer in Lock
bits : 0 - 0 (1 bit)
access : read-only
IFFREQEN : Synthesizer IF frequency enable status
bits : 1 - 1 (1 bit)
access : read-only
No Description
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKED : LOCKED Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
UNLOCKED : UNLOCKED Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
CAPCALDONE : CAPCALDONE Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
VCOHIGH : VCOHIGH Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
VCOLOW : VCOLOW Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
LOCNTDONE : LOCNTDONE Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
No Description
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable LO Counter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : OFF
LO counter is disabled
1 : ON
LO counter is enabled
End of enumeration elements list.
CLEAR : Clear LO Counter
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
0 : OFF
Do not clear LO counter
1 : ON
Clear LO counter
End of enumeration elements list.
RUN : Run LO Counter
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0 : OFF
Do not run LO counter
1 : ON
Run LO counter
End of enumeration elements list.
READ : Read LO Counter
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : OFF
LOCOUNT register read returns all 0's
1 : ON
LOCOUNT register read returns count value
End of enumeration elements list.
NUMCYCLE : Number of Clock Cycles to Run LO Counter
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : CNT_2
Set count length to 2 XO clock cycles
1 : CNT_4
Set count length to 4 XO clock cycles
2 : CNT_8
Set count length to 8 XO clock cycles
3 : CNT_16
Set count length to 16 XO clock cycles
4 : CNT_32
Set count length to 32 XO clock cycles
5 : CNT_64
Set count length to 64 XO clock cycles
6 : CNT_128
Set count length to 128 XO clock cycles
7 : CNT_256
Set count length to 256 XO clock cycles
8 : CNT_512
Set count length to 512 XO clock cycles
9 : CNT_1024
Set count length to 1024 XO clock cycles
10 : CNT_2048
Set count length to 2048 XO clock cycles
11 : CNT_4096
Set count length to 4096 XO clock cycles
12 : CNT_8192
Set count length to 8192 XO clock cycles
End of enumeration elements list.
LOCNTOVERRIDEEN : Enable manual override of CLEAR and RUN
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable manual override
1 : ENABLE
Enable manual override
End of enumeration elements list.
LOCNTMANCLEAR : Manual Control of LO counter CLEAR
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : NOCLEAR
Don't clear LO counter
1 : CLEAR
Clear LO counter
End of enumeration elements list.
LOCNTMANRUN : Manual Control of the LO counter RUN
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : NORUN
Don't initiate start/stop LO counter
1 : RUN
Initiate start/stop of LO counter
End of enumeration elements list.
No Description
address_offset : 0x8C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOCOUNT : LO Counter Value
bits : 0 - 18 (19 bit)
access : read-only
BUSY : LO Counter is Busy
bits : 19 - 19 (1 bit)
access : read-only
No Description
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TARGET : LO Counter Measurement Target
bits : 0 - 18 (19 bit)
access : read-only
No Description
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DENOMINIT0 : New BitField
bits : 0 - 8 (9 bit)
access : read-write
DENOMINIT1 : New BitField
bits : 9 - 17 (9 bit)
access : read-write
DENOMINIT2 : New BitField
bits : 18 - 26 (9 bit)
access : read-write
No Description
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACINIT : Initial CHP DAC Value
bits : 0 - 11 (12 bit)
access : read-write
No Description
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP1BWCAL : LPF Op1 BW Control in Cal Mode
bits : 0 - 3 (4 bit)
access : read-write
OP1COMPCAL : LPF Op1 Comp Control in Cal Mode
bits : 4 - 7 (4 bit)
access : read-write
RFBVALCAL : LPF Rfb Value Select in Cal Mode
bits : 8 - 10 (3 bit)
access : read-write
RPVALCAL : LPF Rp Value Select in Cal Mode
bits : 11 - 13 (3 bit)
access : read-write
RZVALCAL : LPF Rz Value Select in Cal Mode
bits : 14 - 17 (4 bit)
access : read-write
No Description
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP1BWRX : LPF Op1 BW Control in RX Mode
bits : 0 - 3 (4 bit)
access : read-write
OP1COMPRX : LPF Op1 Comp Control in RX Mode
bits : 4 - 7 (4 bit)
access : read-write
RFBVALRX : LPF Rfb Value Select in RX Mode
bits : 8 - 10 (3 bit)
access : read-write
RPVALRX : LPF Rp Value Select in RX Mode
bits : 11 - 13 (3 bit)
access : read-write
RZVALRX : LPF Rz Value Select in RX Mode
bits : 14 - 17 (4 bit)
access : read-write
No Description
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OP1BWTX : LPF Op1 BW Control in TX Mode
bits : 0 - 3 (4 bit)
access : read-write
OP1COMPTX : LPF Op1 Comp Control in TX Mode
bits : 4 - 7 (4 bit)
access : read-write
RFBVALTX : LPF Rfb Value Select in TX Mode
bits : 8 - 10 (3 bit)
access : read-write
RPVALTX : LPF Rp Value Select in TX Mode
bits : 11 - 13 (3 bit)
access : read-write
RZVALTX : LPF Rz Value Select in TX Mode
bits : 14 - 17 (4 bit)
access : read-write
No Description
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPFSWENRX : LPF Switching Enable in RX Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable switching
1 : ENABLE
Enable switching
End of enumeration elements list.
LPFINCAPRX : LPF Input Cap Select in RX Mode
bits : 1 - 2 (2 bit)
access : read-write
LPFGNDSWENRX : LPF Gnd Switch Enable in RX Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable GND switching
1 : ENABLE
Enable GND switching
End of enumeration elements list.
CALCRX : LPF Cap Cal Select in RX Mode
bits : 4 - 8 (5 bit)
access : read-write
CASELRX : LPF Ca Select in RX Mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Ca
1 : ENABLE
Enable Ca
End of enumeration elements list.
CAVALRX : LPF Ca Value Select in RX Mode
bits : 10 - 14 (5 bit)
access : read-write
CFBSELRX : LPF Cfb Select in RX Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Cfb
1 : ENABLE
Enable Cfb
End of enumeration elements list.
CZSELRX : LPF Cz Select in RX Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Cz
1 : ENABLE
Enable Cz
End of enumeration elements list.
CZVALRX : LPF Cz Value Select in RX Mode
bits : 17 - 24 (8 bit)
access : read-write
MODESELRX : LPF Filter Mode Select in RX Mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ONEOP
Sets 1 opamp configuration
1 : TWOOP
Sets 2 opamp configuration
End of enumeration elements list.
VCMLVLRX : LPF Vcm Level Select in RX Mode
bits : 26 - 28 (3 bit)
access : read-write
No Description
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPFSWENTX : LPF Switching Enable in TX Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable switching
1 : ENABLE
Enable switching
End of enumeration elements list.
LPFINCAPTX : LPF Input Cap Select in TX Mode
bits : 1 - 2 (2 bit)
access : read-write
LPFGNDSWENTX : LPF Gnd Switch Enable in TX Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable GND switching
1 : ENABLE
Enable GND switching
End of enumeration elements list.
CALCTX : LPF Cap Cal Select in TX Mode
bits : 4 - 8 (5 bit)
access : read-write
CASELTX : LPF Ca Select in TX Mode
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Ca
1 : ENABLE
Enable Ca
End of enumeration elements list.
CAVALTX : LPF Ca Value Select in TX Mode
bits : 10 - 14 (5 bit)
access : read-write
CFBSELTX : LPF Cfb Select in TX Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Cfb
1 : ENABLE
Enable Cfb
End of enumeration elements list.
CZSELTX : LPF Cz Select in TX Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
Disable Cz
1 : ENABLE
Enable Cz
End of enumeration elements list.
CZVALTX : LPF Cz Value Select in TX Mode
bits : 17 - 24 (8 bit)
access : read-write
MODESELTX : LPF Filter Mode Select in TX Mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : ONEOP
1 opamp configuration
1 : TWOOP
2 opamp configuration
End of enumeration elements list.
VCMLVLTX : LPF Vcm Level Select in TX Mode
bits : 26 - 28 (3 bit)
access : read-write
No Description
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DITHERDSMINPUTRX : Dithering of DSM input for RX mode
bits : 0 - 0 (1 bit)
access : read-write
DITHERDSMOUTPUTRX : Dithering of DSM output for RX mode
bits : 1 - 3 (3 bit)
access : read-write
DITHERDACRX : Dithering of charge pump DAC for RX mode
bits : 4 - 7 (4 bit)
access : read-write
DSMMODERX : Delta-sigma topology for RX mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FEEDFORWARD
Feed forward architecture
1 : MASH
MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode.
End of enumeration elements list.
LSBFORCERX : Delta-sigma input force LSB for RX mode
bits : 9 - 9 (1 bit)
access : read-write
DEMMODERX : DEM Mode for RX mode
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DEM is disabled
1 : ENABLED
DEM is enabled
End of enumeration elements list.
MASHORDERRX : MASH order for RX mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECOND
2nd Order Mash
1 : THIRD
3rd Order Mash
End of enumeration elements list.
REQORDERRX : ReQuant order for RX mode
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : FIRST
1st Order DAC
1 : SECOND
2rd Order DAC
End of enumeration elements list.
No Description
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DITHERDSMINPUTTX : Dithering of DSM input for TX mode
bits : 0 - 0 (1 bit)
access : read-write
DITHERDSMOUTPUTTX : Dithering of DSM output for TX mode
bits : 1 - 3 (3 bit)
access : read-write
DITHERDACTX : Dithering of charge pump DAC for TX mode
bits : 4 - 7 (4 bit)
access : read-write
DSMMODETX : Delta-sigma topology for TX mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FEEDFORWARD
Feed forward architecture
1 : MASH
MASH architecture. Note that the delta-sigma output dithering (DITHERDSMOUTPUT) is not available in this mode.
End of enumeration elements list.
LSBFORCETX : Delta-sigma input force LSB for TX mode
bits : 9 - 9 (1 bit)
access : read-write
DEMMODETX : DEM Mode for TX mode
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
DEM is disabled
1 : ENABLED
DEM is enabled
End of enumeration elements list.
MASHORDERTX : MASH order for TX mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : SECOND
2nd Order Mash
1 : THIRD
3rd Order Mash
End of enumeration elements list.
REQORDERTX : ReQuant order for TX mode
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : FIRST
1st Order DAC
1 : SECOND
2rd Order DAC
End of enumeration elements list.
No Description
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNTHSTART : Starts the RF synthesizer
bits : 0 - 0 (1 bit)
access : write-only
SYNTHSTOP : Stops the RF synthesizer
bits : 1 - 1 (1 bit)
access : write-only
ENABLEIF : Enable the synthesizer IF frequency
bits : 2 - 2 (1 bit)
access : write-only
DISABLEIF : Disable the synthesizer IF frequency
bits : 3 - 3 (1 bit)
access : write-only
CAPCALSTART : Start VCO capacitor array calibration
bits : 4 - 4 (1 bit)
access : write-only
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