Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IPVERSION
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTPRSEN : Enable Protimer start commands from PRS.
bits : 1 - 1 (1 bit)
access : read-write
STARTEDGE : Start Command Edge Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
STOPPRSEN : Enable Protimer stop commands from PRS.
bits : 9 - 9 (1 bit)
access : read-write
STOPEDGE : Stop Command Edge Select
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
RTCCTRIGGERPRSEN : Enable RTCC Trigger from PRS.
bits : 17 - 17 (1 bit)
access : read-write
RTCCTRIGGEREDGE : RTCC Trigger Edge Select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNNING : Running
bits : 0 - 0 (1 bit)
access : read-only
LBTSYNC : LBT Synchronizing
bits : 1 - 1 (1 bit)
access : read-only
LBTRUNNING : LBT Running
bits : 2 - 2 (1 bit)
access : read-only
LBTPAUSED : LBT has been paused.
bits : 3 - 3 (1 bit)
access : read-only
TOUT0RUNNING : Timeout Counter 0 Running
bits : 4 - 4 (1 bit)
access : read-only
TOUT0SYNC : Timeout Counter 0 Synchronizing
bits : 5 - 5 (1 bit)
access : read-only
TOUT1RUNNING : Timeout Counter 1 Running
bits : 6 - 6 (1 bit)
access : read-only
TOUT1SYNC : Timeout Counter 1 Synchronizing
bits : 7 - 7 (1 bit)
access : read-only
ICV0 : CC0 Capture Valid
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : X0
PROTIMER_CC0_PRE, -BASE or -WRAP does not contain a valid capture value
1 : X1
PROTIMER_CC0_PRE, -BASE or -WRAP contains a valid and unread capture value
End of enumeration elements list.
ICV1 : CC1 Capture Valid
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : X0
PROTIMER_CC1_PRE, -BASE or -WRAP does not contain a valid capture value
1 : X1
PROTIMER_CC1_PRE, -BASE or -WRAP contains a valid and unread capture value
End of enumeration elements list.
ICV2 : CC2 Capture Valid
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : X0
PROTIMER_CC2_PRE, -BASE or -WRAP does not contain a valid capture value
1 : X1
PROTIMER_CC2_PRE, -BASE or -WRAP contains a valid and unread capture value
End of enumeration elements list.
ICV3 : CC3 Capture Valid
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : X0
PROTIMER_CC3_PRE, -BASE or -WRAP does not contain a valid capture value
1 : X1
PROTIMER_CC3_PRE, -BASE or -WRAP contains a valid and unread capture value
End of enumeration elements list.
ICV4 : CC4 Capture Valid
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : X0
PROTIMER_CC4_PRE, -BASE or -WRAP does not contain a valid capture value
1 : X1
PROTIMER_CC4_PRE, -BASE or -WRAP contains a valid and unread capture value
End of enumeration elements list.
ICV5 : CC5 Capture Valid
bits : 13 - 13 (1 bit)
access : read-only
ICV6 : CC6 Capture Valid
bits : 14 - 14 (1 bit)
access : read-only
ICV7 : CC7 Capture Valid
bits : 15 - 15 (1 bit)
access : read-only
No Description
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
CCMODE : Compare/Capture mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : COMPARE
Compare mode selected
1 : CAPTURE
Capture mode selected
End of enumeration elements list.
PREMATCHEN : Enable PRECNT matching
bits : 2 - 2 (1 bit)
access : read-write
BASEMATCHEN : Enable BASECNT matching
bits : 3 - 3 (1 bit)
access : read-write
WRAPMATCHEN : Enable WRAPCNT matching
bits : 4 - 4 (1 bit)
access : read-write
OIST : Output Initial State
bits : 5 - 5 (1 bit)
access : read-write
OUTINV : Output Invert
bits : 6 - 6 (1 bit)
access : read-write
MOA : Match Output Action
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action on compare match
1 : TOGGLE
Toggle output on compare match in COMPARE mode.
2 : CLEAR
Clear output on compare match in COMPARE mode.
3 : SET
Set output on compare match in COMPARE mode.
End of enumeration elements list.
OFOA : Overflow Output Action
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No action
1 : TOGGLE
Toggle output when the selected counter has an overflow event.
2 : CLEAR
Clear output when the selected counter has an overflow event.
3 : SET
Set output when the selected counter has an overflow event.
End of enumeration elements list.
OFSEL : Select counter for OFOA bits
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : PRECNT
Use PRECNT overflow
1 : BASECNT
Use BASECNT overflow
2 : WRAPCNT
Use WRAPCNT overflow
3 : DISABLED
Disabled
End of enumeration elements list.
PRSCONF : PRS Configuration
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : PULSE
Each CC event will generate a one HFRADIOCLK cycle high pulse
1 : LEVEL
Should be used when OFSEL, OFOA or MOA are specified.
End of enumeration elements list.
INSEL : Capture input selection
bits : 21 - 24 (4 bit)
access : read-write
Enumeration:
0 : PRS
Use the selected PRS channel
1 : TXDONE
TX completed
2 : RXDONE
RX completed
3 : TXORRXDONE
TX or RX completed
4 : FRAMEDET0
Demodulator found sync word 0
5 : FRAMEDET1
Demodulator found sync word 1
6 : FDET0OR1
Demodulator found sync word 0 or 1
7 : MODSYNCSENT
Modulator sync word sent
8 : RXEOF
RX at end of frame from demodulator
9 : PRORTC0
PRORTC capture/compare 0
10 : PRORTC1
PRORTC capture/compare 1
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : DISABLED
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRE : CC Channel PRE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : CC Channel BASE Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAP : CC Channel WRAP Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECNT : Pre Counter Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASECNT : Base Counter Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAPCNT : Wrap Counter Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRECNTV : Pre counter value
bits : 0 - 15 (16 bit)
access : read-only
BASECNTV : Base counter value
bits : 16 - 31 (16 bit)
access : read-only
No Description
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LWRAPCNT : Latched Wrap Counter Value
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECNTTOPADJ : PRECNT Top Adjust Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECNTTOPFRAC : PRECNT Top Fractional Value
bits : 0 - 7 (8 bit)
access : read-write
PRECNTTOP : PRECNT Top Value
bits : 8 - 23 (16 bit)
access : read-write
No Description
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASECNTTOP : BASECNT Top Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRAPCNTTOP : WRAPCNT Top Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT0PCNT : TOUT0PCNT Value
bits : 0 - 15 (16 bit)
access : read-write
TOUT0CNT : TOUT0CNT Value
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EN
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT0PCNTTOP : TOUT0PCNTTOP Value
bits : 0 - 15 (16 bit)
access : read-write
TOUT0CNTTOP : TOUT0CNTTOP Value
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT0PCNTCOMP : TOUT0PCNTCOMP
bits : 0 - 15 (16 bit)
access : read-write
TOUT0CNTCOMP : TOUT0CNTCOMP Value
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT1PCNT : TOUT1PCNT Value
bits : 0 - 15 (16 bit)
access : read-write
TOUT1CNT : TOUT1CNT Value
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT1PCNTTOP : TOUT1PCNTTOP Value
bits : 0 - 15 (16 bit)
access : read-write
TOUT1CNTTOP : TOUT1CNTTOP Value
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT1PCNTCOMP : TOUT1PCNTCOMP
bits : 0 - 15 (16 bit)
access : read-write
TOUT1CNTCOMP : TOUT1CNTCOMP Value
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTEXP : Start Exponent
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : EXP0
STARTEXP value = 0 (used for Fast TX)
1 : EXP1
STARTEXP value = 1
2 : EXP2
STARTEXP value = 2
3 : EXP3
STARTEXP value = 3
4 : EXP4
STARTEXP value = 4
5 : EXP5
STARTEXP value = 5
6 : EXP6
STARTEXP value = 6
7 : EXP7
STARTEXP value = 7
8 : EXP8
STARTEXP value = 8
End of enumeration elements list.
MAXEXP : Maximum Exponent
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : EXP0
MAXEXP value = 0
1 : EXP1
MAXEXP value = 1
2 : EXP2
MAXEXP value = 2
3 : EXP3
MAXEXP value = 3
4 : EXP4
MAXEXP value = 4
5 : EXP5
MAXEXP value = 5
6 : EXP6
MAXEXP value = 6
7 : EXP7
MAXEXP value = 7
8 : EXP8
MAXEXP value = 8
End of enumeration elements list.
CCADELAY : Clear Channel Assessment Delay
bits : 8 - 12 (5 bit)
access : read-write
CCAREPEAT : Clear Channel Assessment Repeat
bits : 16 - 19 (4 bit)
access : read-write
FIXEDBACKOFF : Fixed backoff
bits : 20 - 20 (1 bit)
access : read-write
RETRYLIMIT : Retry Limit
bits : 24 - 27 (4 bit)
access : read-write
No Description
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LBTSTARTPRSEN : Enable LBT start commands from PRS.
bits : 8 - 8 (1 bit)
access : read-write
LBTPAUSEPRSEN : Enable LBT pause commands from PRS.
bits : 16 - 16 (1 bit)
access : read-write
LBTSTOPPRSEN : Enable LBT stop commands from PRS.
bits : 24 - 24 (1 bit)
access : read-write
No Description
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT0PCNT : TOUT0PCNT value to be saved
bits : 0 - 15 (16 bit)
access : read-write
TOUT0CNT : TOUT0CNT value to be saved
bits : 16 - 31 (16 bit)
access : read-write
No Description
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDOM : Pseudo Random Value
bits : 0 - 15 (16 bit)
access : read-write
No Description
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECNTOF : PRECNT Overflow Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
BASECNTOF : BASECNT Overflow Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write
WRAPCNTOF : WRAPCNT Overflow Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
TOUT0 : TOUT0 underflow interrupt flag
bits : 4 - 4 (1 bit)
access : read-write
TOUT1 : TOUT1 underflow interrupt flag
bits : 5 - 5 (1 bit)
access : read-write
TOUT0MATCH : TOUT0 compare match interrupt flag
bits : 6 - 6 (1 bit)
access : read-write
TOUT1MATCH : TOUT1 compare match interrupt flag
bits : 7 - 7 (1 bit)
access : read-write
CC0 : CC Channel 0 Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write
CC1 : CC Channel 1 Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write
CC2 : CC Channel 2 Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-write
CC3 : CC Channel 3 Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write
CC4 : CC Channel 4 Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write
CC5 : CC Channel 5 Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write
CC6 : CC Channel 6 Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-write
CC7 : CC Channel 7 Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-write
COF0 : CC Channel 0 Overflow Interrupt Flag
bits : 16 - 16 (1 bit)
access : read-write
COF1 : CC Channel 1 Overflow Interrupt Flag
bits : 17 - 17 (1 bit)
access : read-write
COF2 : CC Channel 2 Overflow Interrupt Flag
bits : 18 - 18 (1 bit)
access : read-write
COF3 : CC Channel 3 Overflow Interrupt Flag
bits : 19 - 19 (1 bit)
access : read-write
COF4 : CC Channel 4 Overflow Interrupt Flag
bits : 20 - 20 (1 bit)
access : read-write
COF5 : CC Channel 5 Overflow Interrupt Flag
bits : 21 - 21 (1 bit)
access : read-write
COF6 : CC Channel 6 Overflow Interrupt Flag
bits : 22 - 22 (1 bit)
access : read-write
COF7 : CC Channel 7 Overflow Interrupt Flag
bits : 23 - 23 (1 bit)
access : read-write
LBTSUCCESS : Listen Before Talk Success
bits : 24 - 24 (1 bit)
access : read-write
LBTFAILURE : Listen Before Talk Failure
bits : 25 - 25 (1 bit)
access : read-write
LBTPAUSED : Listen Before Talk Paused
bits : 26 - 26 (1 bit)
access : read-write
LBTRETRY : Listen Before Talk Retry
bits : 27 - 27 (1 bit)
access : read-write
RTCCSYNCHED : PROTIMER synchronized with the RTCC
bits : 28 - 28 (1 bit)
access : read-write
TOUT0MATCHLBT : TOUT0 compare match interrupt flag
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECNTOF : PRECNTOF Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
BASECNTOF : BASECNTOF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
WRAPCNTOF : WRAPCNTOF Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
TOUT0 : TOUT0 Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
TOUT1 : TOUT1 Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
TOUT0MATCH : TOUT0MATCH Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
TOUT1MATCH : TOUT1MATCH Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
CC0 : CC0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
CC1 : CC1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
CC2 : CC2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
CC3 : CC3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
CC4 : CC4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
CC5 : CC5 Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
CC6 : CC6 Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
CC7 : CC7 Interrupt Enable
bits : 15 - 15 (1 bit)
access : read-write
COF0 : COF0 Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
COF1 : COF1 Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
COF2 : COF2 Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
COF3 : COF3 Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
COF4 : COF4 Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
COF5 : COF5 Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
COF6 : COF6 Interrupt Enable
bits : 22 - 22 (1 bit)
access : read-write
COF7 : COF7 Interrupt Enable
bits : 23 - 23 (1 bit)
access : read-write
LBTSUCCESS : LBTSUCCESS Interrupt Enable
bits : 24 - 24 (1 bit)
access : read-write
LBTFAILURE : LBTFAILURE Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-write
LBTPAUSED : LBTPAUSED Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-write
LBTRETRY : LBTRETRY Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-write
RTCCSYNCHED : RTCCSYNCHED Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-write
TOUT0MATCHLBT : TOUT0MATCHLBT Interrupt Enable
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXSETEVENT1 : First event that sets RX req signal
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DISABLED
Request is never set
1 : ALWAYS
Does not wait for any particular event
2 : PRECNTOF
Pre counter overflow
3 : BASECNTOF
Base counter overflow
4 : WRAPCNTOF
Wrap counter overflow
5 : TOUT0UF
Timeout counter 0 underflow
6 : TOUT1UF
Timeout counter 1 underflow
7 : TOUT0MATCH
Timeout counter 0 match
8 : TOUT1MATCH
Timeout counter 1 match
9 : CC0
Channel 0 Capture/Compare event
10 : CC1
Channel 1 Capture/Compare event
11 : CC2
Channel 2 Capture/Compare event
12 : CC3
Channel 3 Capture/Compare event
13 : CC4
Channel 4 Capture/Compare event
14 : TXDONE
MOD indicated that TX completed
15 : RXDONE
FRC indicated that RX completed
16 : TXORRXDONE
MOD/FRC indicated that TX or RX completed
17 : FDET0
DEMOD indicated that syncword 0 was detected
18 : FDET1
DEMOD indicated that syncword 1 was detected
19 : FDET0OR1
DEMOD indicated that syncword 0 or 1 was detected
20 : LBTSUCCESS
LBT completed successfully
21 : LBTRETRY
LBT detected occupied channel and will try again
22 : LBTFAILURE
LBT could not start transmission
23 : ANYLBT
Any LBT event
24 : CCAACK
A CCA measurement completed
25 : CCA
A CCA measurement completed, and channel was clear
26 : NOTCCA
A CCA measurement completed, and channel was busy
27 : TOUT0MATCHLBT
Timeout counter 0 match occurred during LBT operation
End of enumeration elements list.
RXSETEVENT2 : Second event that sets RX req signal
bits : 8 - 12 (5 bit)
access : read-write
RXCLREVENT1 : First event that clears RX req signal
bits : 16 - 20 (5 bit)
access : read-write
RXCLREVENT2 : Second event that clears RX req signal
bits : 24 - 28 (5 bit)
access : read-write
No Description
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSETEVENT1 : First event that sets TX req signal
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : DISABLED
Request is never set
1 : ALWAYS
Does not wait for any particular event
2 : PRECNTOF
Pre counter overflow
3 : BASECNTOF
Base counter overflow
4 : WRAPCNTOF
Wrap counter overflow
5 : TOUT0UF
Timeout counter 0 underflow
6 : TOUT1UF
Timeout counter 1 underflow
7 : TOUT0MATCH
Timeout counter 0 match
8 : TOUT1MATCH
Timeout counter 1 match
9 : CC0
Channel 0 Capture/Compare event
10 : CC1
Channel 1 Capture/Compare event
11 : CC2
Channel 2 Capture/Compare event
12 : CC3
Channel 3 Capture/Compare event
13 : CC4
Channel 4 Capture/Compare event
14 : TXDONE
MOD indicated that TX completed
15 : RXDONE
FRC indicated that RX completed
16 : TXORRXDONE
MOD/FRC indicated that TX or RX completed
17 : FDET0
DEMOD indicated that syncword 0 was detected
18 : FDET1
DEMOD indicated that syncword 1 was detected
19 : FDET0OR1
DEMOD indicated that syncword 0 or 1 was detected
20 : LBTSUCCESS
LBT completed successfully
21 : LBTRETRY
LBT detected occupied channel and will try again
22 : LBTFAILURE
LBT could not start transmission
23 : ANYLBT
Any LBT event
24 : CCAACK
A CCA measurement completed
25 : CCA
A CCA measurement completed, and channel was clear
26 : NOTCCA
A CCA measurement completed, and channel was busy
27 : TOUT0MATCHLBT
Timeout counter 0 match occurred during LBT operation
End of enumeration elements list.
TXSETEVENT2 : Second event that sets TX req signal
bits : 8 - 12 (5 bit)
access : read-write
No Description
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ETSIEN : ETSI LBT enabling
bits : 0 - 0 (1 bit)
access : read-write
GRANULARLESSTHANRXWARM : Granular less than RXWARM
bits : 1 - 1 (1 bit)
access : read-write
RXWARMTHLD : Minimum backoff period for RXWARM
bits : 2 - 9 (8 bit)
access : read-write
CCAFIXED : Fixed listening time
bits : 10 - 25 (16 bit)
access : read-write
No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUGRUN : Debug Mode Run Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : X0
PROTIMER is frozen in debug mode
1 : X1
PROTIMER is running in debug mode
End of enumeration elements list.
DMACLRACT : DMA Request Clear on Active
bits : 2 - 2 (1 bit)
access : read-write
OSMEN : One-Shot Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : X0
Protimer continues to count when WRAP counter overflows.
1 : X1
Protimer stops counting when WRAP counter overflows.
End of enumeration elements list.
ZEROSTARTEN : Start from zero enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : X0
Protimer starts from the previous count value
1 : X1
Protimer starts counting from zero
End of enumeration elements list.
PRECNTSRC : Selects clock to Pre-counter
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Disable Pre-counter
1 : CLOCK
Module clock
2 : UNUSED0
Do not use
3 : UNUSED1
Do not use
End of enumeration elements list.
BASECNTSRC : Selects clock to Base counter
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Disable base counter
1 : PRECNTOF
Pre-counter overflow events
2 : UNUSED0
Do not use
3 : UNUSED1
Do not use
End of enumeration elements list.
WRAPCNTSRC : Selects clock to Wrap counter
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
Disable Wrap counter
1 : PRECNTOF
Pre-counter overflow events
2 : BASECNTOF
Base counter overflow events
3 : UNUSED
Do not use
End of enumeration elements list.
TOUT0SRC : Selects clock to timeout counter 0
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No counting
1 : PRECNTOF
Pre-counter overflow events
2 : BASECNTOF
Base counter overflow events
3 : WRAPCNTOF
Wrap counter overflow events
End of enumeration elements list.
TOUT0SYNCSRC : Select timeout counter 0 event
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No synchronization
1 : PRECNTOF
Pre-counter overflow event
2 : BASECNTOF
Base counter overflow event
3 : WRAPCNTOF
Wrap counter overflow event
End of enumeration elements list.
TOUT1SRC : Selects clock to timeout counter 1
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No counting
1 : PRECNTOF
Pre-counter overflow events
2 : BASECNTOF
Base counter overflow events
3 : WRAPCNTOF
Wrap counter overflow events
End of enumeration elements list.
TOUT1SYNCSRC : Select timeout counter 1 event
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0 : DISABLED
No synchronization
1 : PRECNTOF
Pre-counter overflow event
2 : BASECNTOF
Base counter overflow event
3 : WRAPCNTOF
Wrap counter overflow event
End of enumeration elements list.
TOUT0MODE : Repeat Mode
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : FREE
When started, the TOUT0 counts down until it is stopped by software
1 : ONESHOT
TOUT0 is stopped after it reaches zero
End of enumeration elements list.
TOUT1MODE : Repeat Mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : FREE
When started, the TOUT1 counts down until it is stopped by software
1 : ONESHOT
TOUT1 is stopped after it reaches zero
End of enumeration elements list.
No Description
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCACNT : Current CCA counter value
bits : 0 - 3 (4 bit)
access : read-write
EXP : LBT Exponent
bits : 4 - 7 (4 bit)
access : read-write
RETRYCNT : LBT Retry counter
bits : 8 - 11 (4 bit)
access : read-write
No Description
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDOM0 : Linear random backoff period from FW
bits : 0 - 8 (9 bit)
access : read-write
RANDOM1 : Linear random backoff period from FW
bits : 9 - 17 (9 bit)
access : read-write
RANDOM2 : Linear random backoff period from FW
bits : 18 - 26 (9 bit)
access : read-write
No Description
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDOM3 : Linear random backoff period from FW
bits : 0 - 8 (9 bit)
access : read-write
RANDOM4 : Linear random backoff period from FW
bits : 9 - 17 (9 bit)
access : read-write
RANDOM5 : Linear random backoff period from FW
bits : 18 - 26 (9 bit)
access : read-write
No Description
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDOM6 : Linear random backoff period from FW
bits : 0 - 8 (9 bit)
access : read-write
RANDOM7 : Linear random backoff period from FW
bits : 9 - 17 (9 bit)
access : read-write
No Description
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start PROTIMER
bits : 0 - 0 (1 bit)
access : write-only
RTCSYNCSTART : Start PROTIMER Synchronized with RTCC
bits : 1 - 1 (1 bit)
access : write-only
STOP : Stop PROTIMER
bits : 2 - 2 (1 bit)
access : write-only
TOUT0START : Start Timeout counter 0
bits : 4 - 4 (1 bit)
access : write-only
TOUT0STOP : Stop Timeout counter 0
bits : 5 - 5 (1 bit)
access : write-only
TOUT1START : Start Timeout counter 1
bits : 6 - 6 (1 bit)
access : write-only
TOUT1STOP : Stop Timeout counter 0
bits : 7 - 7 (1 bit)
access : write-only
LBTSTART : LBT sequence start
bits : 16 - 16 (1 bit)
access : write-only
LBTPAUSE : Pause LBT sequence
bits : 17 - 17 (1 bit)
access : write-only
LBTSTOP : LBT sequence stop
bits : 18 - 18 (1 bit)
access : write-only
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