\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IPVERSION : IP VERSION
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RUNNING : RTCC running status
bits : 0 - 0 (1 bit)
access : read-only
RTCCLOCKSTATUS : Lock Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : UNLOCKED
RTCC registers are unlocked
1 : LOCKED
RTCC registers are locked
End of enumeration elements list.
No Description
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF : Overflow Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
CNTTICK : Main counter tick
bits : 1 - 1 (1 bit)
access : read-write
CC0 : CC Channel n Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write
CC1 : CC Channel n Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write
CC2 : CC Channel n Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OF : OF Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
CNTTICK : CNTTICK Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
CC0 : CC Channel n Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
CC1 : CC Channel n Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
CC2 : CC Channel n Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
No Description
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECNT : Pre-Counter Value
bits : 0 - 14 (15 bit)
access : read-write
No Description
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Counter Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRECNT : Pre-Counter Value
bits : 0 - 14 (15 bit)
access : read-only
CNTLSB : Counter Value
bits : 15 - 31 (17 bit)
access : read-only
No Description
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
START : Sync busy for START
bits : 0 - 0 (1 bit)
access : read-only
STOP : Sync busy for STOP
bits : 1 - 1 (1 bit)
access : read-only
PRECNT : Sync busy for PRECNT
bits : 2 - 2 (1 bit)
access : read-only
CNT : Sync busy for CNT
bits : 3 - 3 (1 bit)
access : read-only
No Description
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCKKEY : Configuration Lock Key
bits : 0 - 15 (16 bit)
access : write-only
Enumeration:
44776 : UNLOCK
Write to unlock RTCC lockable registers
End of enumeration elements list.
No Description
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Compare/Capture channel turned off
1 : INPUTCAPTURE
Input capture
2 : OUTPUTCOMPARE
Output compare
End of enumeration elements list.
CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : PULSE
A single clock cycle pulse is generated on output
1 : TOGGLE
Toggle output on compare match
2 : CLEAR
Clear output on compare match
3 : SET
Set output on compare match
End of enumeration elements list.
COMPBASE : Capture compare channel comparison base.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CNT
RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register.
1 : PRECNT
Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT.
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : NONE
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IC : Input Capture Value
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Compare/Capture channel turned off
1 : INPUTCAPTURE
Input capture
2 : OUTPUTCOMPARE
Output compare
End of enumeration elements list.
CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : PULSE
A single clock cycle pulse is generated on output
1 : TOGGLE
Toggle output on compare match
2 : CLEAR
Clear output on compare match
3 : SET
Set output on compare match
End of enumeration elements list.
COMPBASE : Capture compare channel comparison base.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CNT
RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register.
1 : PRECNT
Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT.
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : NONE
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : RTCC Enable
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IC : Input Capture Value
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : CC Channel Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : OFF
Compare/Capture channel turned off
1 : INPUTCAPTURE
Input capture
2 : OUTPUTCOMPARE
Output compare
End of enumeration elements list.
CMOA : Compare Match Output Action
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : PULSE
A single clock cycle pulse is generated on output
1 : TOGGLE
Toggle output on compare match
2 : CLEAR
Clear output on compare match
3 : SET
Set output on compare match
End of enumeration elements list.
COMPBASE : Capture compare channel comparison base.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CNT
RTCC_CCx_ICVALUE/OCVALUE is compared with CNT register.
1 : PRECNT
Least significant bits of RTCC_CCx_ICVALUE/OCVALUE are compared with COMBCNT.
End of enumeration elements list.
ICEDGE : Input Capture Edge Select
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
0 : RISING
Rising edges detected
1 : FALLING
Falling edges detected
2 : BOTH
Both edges detected
3 : NONE
No edge detection, signal is left as it is
End of enumeration elements list.
No Description
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OC : Output Compare Value
bits : 0 - 31 (32 bit)
access : read-write
No Description
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IC : Input Capture Value
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEBUGRUN : Debug Mode Run Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : X0
RTCC is frozen in debug mode
1 : X1
RTCC is running in debug mode
End of enumeration elements list.
PRECNTCCV0TOP : Pre-counter CCV0 top value enable.
bits : 1 - 1 (1 bit)
access : read-write
CNTCCV1TOP : CCV1 top value enable
bits : 2 - 2 (1 bit)
access : read-write
CNTTICK : Counter prescaler mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : PRESC
CNT register ticks according to configuration in CNTPRESC.
1 : CCV0MATCH
CNT register ticks when PRECNT matches RTCC_CC0_CCV[14:0]
End of enumeration elements list.
CNTPRESC : Counter prescaler value.
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : DIV1
CLK_CNT = (RTCC LF CLK)/1
1 : DIV2
CLK_CNT = (RTCC LF CLK)/2
2 : DIV4
CLK_CNT = (RTCC LF CLK)/4
3 : DIV8
CLK_CNT = (RTCC LF CLK)/8
4 : DIV16
CLK_CNT = (RTCC LF CLK)/16
5 : DIV32
CLK_CNT = (RTCC LF CLK)/32
6 : DIV64
CLK_CNT = (RTCC LF CLK)/64
7 : DIV128
CLK_CNT = (RTCC LF CLK)/128
8 : DIV256
CLK_CNT = (RTCC LF CLK)/256
9 : DIV512
CLK_CNT = (RTCC LF CLK)/512
10 : DIV1024
CLK_CNT = (RTCC LF CLK)/1024
11 : DIV2048
CLK_CNT = (RTCC LF CLK)/2048
12 : DIV4096
CLK_CNT = (RTCC LF CLK)/4096
13 : DIV8192
CLK_CNT = (RTCC LF CLK)/8192
14 : DIV16384
CLK_CNT = (RTCC LF CLK)/16384
15 : DIV32768
CLK_CNT = (RTCC LF CLK)/32768
End of enumeration elements list.
No Description
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start RTCC main counter
bits : 0 - 0 (1 bit)
access : write-only
STOP : Stop RTCC main counter
bits : 1 - 1 (1 bit)
access : write-only
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