CMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

LFRCOCTRL

AUXHFRCOCTRL

CALCTRL

CALCNT

OSCENCMD

CMD

LFCLKSEL

STATUS

IF

IFS

IFC

IEN

HFCORECLKDIV

HFCORECLKEN0

HFPERCLKEN0

SYNCBUSY

FREEZE

LFACLKEN0

LFBCLKEN0

LFCCLKEN0

LFAPRESC0

LFBPRESC0

PCNTCTRL

HFPERCLKDIV

ROUTE

LOCK

HFRCOCTRL

USBCRCTRL

USHFRCOCTRL

USHFRCOTUNE

USHFRCOCONF


CTRL

CMU Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFXOMODE HFXOBOOST HFXOBUFCUR HFXOGLITCHDETEN HFXOTIMEOUT LFXOMODE LFXOBOOST HFCLKDIV LFXOBUFCUR LFXOTIMEOUT CLKOUTSEL0 CLKOUTSEL1

HFXOMODE : HFXO Mode
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : XTAL

4-25 MHz crystal oscillator.

0x00000001 : BUFEXTCLK

An AC coupled buffer is coupled in series with HFXTAL_N, suitable for external sine wave (4-25 MHz). The sine wave should have a minimum of 200 mV peak to peak.

0x00000002 : DIGEXTCLK

Digital external clock on HFXTAL_N pin. Oscillator is effectively bypassed.

End of enumeration elements list.

HFXOBOOST : HFXO Start-up Boost Current
bits : 2 - 3
access : read-write

Enumeration:

0x00000000 : 50PCENT

50 %.

0x00000001 : 70PCENT

70 %.

0x00000002 : 80PCENT

80 %.

0x00000003 : 100PCENT

100 % (default).

End of enumeration elements list.

HFXOBUFCUR : HFXO Boost Buffer Current
bits : 5 - 6
access : read-write

HFXOGLITCHDETEN : HFXO Glitch Detector Enable
bits : 7 - 7
access : read-write

HFXOTIMEOUT : HFXO Timeout
bits : 9 - 10
access : read-write

Enumeration:

0x00000000 : 8CYCLES

Timeout period of 8 cycles.

0x00000001 : 256CYCLES

Timeout period of 256 cycles.

0x00000002 : 1KCYCLES

Timeout period of 1024 cycles.

0x00000003 : 16KCYCLES

Timeout period of 16384 cycles.

End of enumeration elements list.

LFXOMODE : LFXO Mode
bits : 11 - 12
access : read-write

Enumeration:

0x00000000 : XTAL

32.768 kHz crystal oscillator.

0x00000001 : BUFEXTCLK

An AC coupled buffer is coupled in series with LFXTAL_N pin, suitable for external sinus wave (32.768 kHz).

0x00000002 : DIGEXTCLK

Digital external clock on LFXTAL_N pin. Oscillator is effectively bypassed.

End of enumeration elements list.

LFXOBOOST : LFXO Start-up Boost Current
bits : 13 - 13
access : read-write

HFCLKDIV : HFCLK Division
bits : 14 - 16
access : read-write

LFXOBUFCUR : LFXO Boost Buffer Current
bits : 17 - 17
access : read-write

LFXOTIMEOUT : LFXO Timeout
bits : 18 - 19
access : read-write

Enumeration:

0x00000000 : 8CYCLES

Timeout period of 8 cycles.

0x00000001 : 1KCYCLES

Timeout period of 1024 cycles.

0x00000002 : 16KCYCLES

Timeout period of 16384 cycles.

0x00000003 : 32KCYCLES

Timeout period of 32768 cycles.

End of enumeration elements list.

CLKOUTSEL0 : Clock Output Select 0
bits : 20 - 22
access : read-write

Enumeration:

0x00000000 : HFRCO

HFRCO (directly from oscillator).

0x00000001 : HFXO

HFXO (directly from oscillator).

0x00000002 : HFCLK2

HFCLK/2.

0x00000003 : HFCLK4

HFCLK/4.

0x00000004 : HFCLK8

HFCLK/8.

0x00000005 : HFCLK16

HFCLK/16.

0x00000006 : ULFRCO

ULFRCO (directly from oscillator).

0x00000007 : AUXHFRCO

AUXHFRCO (directly from oscillator).

End of enumeration elements list.

CLKOUTSEL1 : Clock Output Select 1
bits : 23 - 26
access : read-write

Enumeration:

0x00000000 : LFRCO

LFRCO (directly from oscillator).

0x00000001 : LFXO

LFXO (directly from oscillator).

0x00000002 : HFCLK

HFCLK (undivided).

0x00000003 : LFXOQ

LFXO (qualified).

0x00000004 : HFXOQ

HFXO (qualified).

0x00000005 : LFRCOQ

LFRCO (qualified).

0x00000006 : HFRCOQ

HFRCO (qualified).

0x00000007 : AUXHFRCOQ

AUXHFRCO (qualified).

0x00000008 : USHFRCO

USHFRCO

End of enumeration elements list.


LFRCOCTRL

LFRCO Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING

TUNING : LFRCO Tuning Value
bits : 0 - 6
access : read-write


AUXHFRCOCTRL

AUXHFRCO Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING BAND

TUNING : AUXHFRCO Tuning Value
bits : 0 - 7
access : read-write

BAND : AUXHFRCO Band Select
bits : 8 - 10
access : read-write

Enumeration:

0x00000000 : 14MHZ

14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000001 : 11MHZ

11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000002 : 7MHZ

7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000003 : 1MHZ

1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000007 : 21MHZ

21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

End of enumeration elements list.


CALCTRL

Calibration Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UPSEL DOWNSEL CONT

UPSEL : Calibration Up-counter Select
bits : 0 - 2
access : read-write

Enumeration:

0x00000000 : HFXO

Select HFXO as up-counter.

0x00000001 : LFXO

Select LFXO as up-counter.

0x00000002 : HFRCO

Select HFRCO as up-counter.

0x00000003 : LFRCO

Select LFRCO as up-counter.

0x00000004 : AUXHFRCO

Select AUXHFRCO as up-counter.

0x00000005 : USHFRCO

Select USHFRCO as up-counter.

End of enumeration elements list.

DOWNSEL : Calibration Down-counter Select
bits : 3 - 5
access : read-write

Enumeration:

0x00000000 : HFCLK

Select HFCLK for down-counter.

0x00000001 : HFXO

Select HFXO for down-counter.

0x00000002 : LFXO

Select LFXO for down-counter.

0x00000003 : HFRCO

Select HFRCO for down-counter.

0x00000004 : LFRCO

Select LFRCO for down-counter.

0x00000005 : AUXHFRCO

Select AUXHFRCO for down-counter.

0x00000006 : USHFRCO

Select USHFRCO for down-counter.

End of enumeration elements list.

CONT : Continuous Calibration
bits : 6 - 6
access : read-write


CALCNT

Calibration Counter Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALCNT

CALCNT : Calibration Counter
bits : 0 - 19
access : read-write


OSCENCMD

Oscillator Enable/Disable Command Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCOEN HFRCODIS HFXOEN HFXODIS AUXHFRCOEN AUXHFRCODIS LFRCOEN LFRCODIS LFXOEN LFXODIS USHFRCOEN USHFRCODIS

HFRCOEN : HFRCO Enable
bits : 0 - 0
access : write-only

HFRCODIS : HFRCO Disable
bits : 1 - 1
access : write-only

HFXOEN : HFXO Enable
bits : 2 - 2
access : write-only

HFXODIS : HFXO Disable
bits : 3 - 3
access : write-only

AUXHFRCOEN : AUXHFRCO Enable
bits : 4 - 4
access : write-only

AUXHFRCODIS : AUXHFRCO Disable
bits : 5 - 5
access : write-only

LFRCOEN : LFRCO Enable
bits : 6 - 6
access : write-only

LFRCODIS : LFRCO Disable
bits : 7 - 7
access : write-only

LFXOEN : LFXO Enable
bits : 8 - 8
access : write-only

LFXODIS : LFXO Disable
bits : 9 - 9
access : write-only

USHFRCOEN : USHFRCO Enable
bits : 10 - 10
access : write-only

USHFRCODIS : USHFRCO Disable
bits : 11 - 11
access : write-only


CMD

Command Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFCLKSEL CALSTART CALSTOP

HFCLKSEL : HFCLK Select
bits : 0 - 2
access : write-only

Enumeration:

0x00000001 : HFRCO

Select HFRCO as HFCLK.

0x00000002 : HFXO

Select HFXO as HFCLK.

0x00000003 : LFRCO

Select LFRCO as HFCLK.

0x00000004 : LFXO

Select LFXO as HFCLK.

0x00000005 : USHFRCODIV2

Select USHFRCO divided by two as HFCLK.

End of enumeration elements list.

CALSTART : Calibration Start
bits : 3 - 3
access : write-only

CALSTOP : Calibration Stop
bits : 4 - 4
access : write-only


LFCLKSEL

Low Frequency Clock Select Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFA LFB LFC LFAE LFBE

LFA : Clock Select for LFA
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : DISABLED

LFACLK is disabled

0x00000001 : LFRCO

LFRCO selected as LFACLK

0x00000002 : LFXO

LFXO selected as LFACLK

0x00000003 : HFCORECLKLEDIV2

HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.

End of enumeration elements list.

LFB : Clock Select for LFB
bits : 2 - 3
access : read-write

Enumeration:

0x00000000 : DISABLED

LFBCLK is disabled

0x00000001 : LFRCO

LFRCO selected as LFBCLK

0x00000002 : LFXO

LFXO selected as LFBCLK

0x00000003 : HFCORECLKLEDIV2

HFCORECLKLE divided by two or four is selected as LFACLK. The division factor is determined by CMU_CTRL_HFLE and CMU_HFCORECLKDIV_HFCORECLKLEDIV.

End of enumeration elements list.

LFC : Clock Select for LFC
bits : 4 - 5
access : read-write

Enumeration:

0x00000000 : DISABLED

LFCCLK clock disabled.

0x00000001 : LFRCO

LFRCO selected as LFCCLK clock

0x00000002 : LFXO

LFXO selected as LFCCLK clock

End of enumeration elements list.

LFAE : Clock Select for LFA Extended
bits : 16 - 16
access : read-write

LFBE : Clock Select for LFB Extended
bits : 20 - 20
access : read-write


STATUS

Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCOENS HFRCORDY HFXOENS HFXORDY AUXHFRCOENS AUXHFRCORDY LFRCOENS LFRCORDY LFXOENS LFXORDY HFRCOSEL HFXOSEL LFRCOSEL LFXOSEL CALBSY USHFRCOENS USHFRCORDY USHFRCOSUSPEND USHFRCODIV2SEL

HFRCOENS : HFRCO Enable Status
bits : 0 - 0
access : read-only

HFRCORDY : HFRCO Ready
bits : 1 - 1
access : read-only

HFXOENS : HFXO Enable Status
bits : 2 - 2
access : read-only

HFXORDY : HFXO Ready
bits : 3 - 3
access : read-only

AUXHFRCOENS : AUXHFRCO Enable Status
bits : 4 - 4
access : read-only

AUXHFRCORDY : AUXHFRCO Ready
bits : 5 - 5
access : read-only

LFRCOENS : LFRCO Enable Status
bits : 6 - 6
access : read-only

LFRCORDY : LFRCO Ready
bits : 7 - 7
access : read-only

LFXOENS : LFXO Enable Status
bits : 8 - 8
access : read-only

LFXORDY : LFXO Ready
bits : 9 - 9
access : read-only

HFRCOSEL : HFRCO Selected
bits : 10 - 10
access : read-only

HFXOSEL : HFXO Selected
bits : 11 - 11
access : read-only

LFRCOSEL : LFRCO Selected
bits : 12 - 12
access : read-only

LFXOSEL : LFXO Selected
bits : 13 - 13
access : read-only

CALBSY : Calibration Busy
bits : 14 - 14
access : read-only

USHFRCOENS : USHFRCO Enable Status
bits : 21 - 21
access : read-only

USHFRCORDY : USHFRCO Ready
bits : 22 - 22
access : read-only

USHFRCOSUSPEND : USHFRCO is suspended
bits : 23 - 23
access : read-only

USHFRCODIV2SEL : USHFRCODIV2 Selected
bits : 26 - 26
access : read-only


IF

Interrupt Flag Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY

HFRCORDY : HFRCO Ready Interrupt Flag
bits : 0 - 0
access : read-only

HFXORDY : HFXO Ready Interrupt Flag
bits : 1 - 1
access : read-only

LFRCORDY : LFRCO Ready Interrupt Flag
bits : 2 - 2
access : read-only

LFXORDY : LFXO Ready Interrupt Flag
bits : 3 - 3
access : read-only

AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag
bits : 4 - 4
access : read-only

CALRDY : Calibration Ready Interrupt Flag
bits : 5 - 5
access : read-only

CALOF : Calibration Overflow Interrupt Flag
bits : 6 - 6
access : read-only

USHFRCORDY : USHFRCO Ready Interrupt Flag
bits : 8 - 8
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY

HFRCORDY : HFRCO Ready Interrupt Flag Set
bits : 0 - 0
access : write-only

HFXORDY : HFXO Ready Interrupt Flag Set
bits : 1 - 1
access : write-only

LFRCORDY : LFRCO Ready Interrupt Flag Set
bits : 2 - 2
access : write-only

LFXORDY : LFXO Ready Interrupt Flag Set
bits : 3 - 3
access : write-only

AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag Set
bits : 4 - 4
access : write-only

CALRDY : Calibration Ready Interrupt Flag Set
bits : 5 - 5
access : write-only

CALOF : Calibration Overflow Interrupt Flag Set
bits : 6 - 6
access : write-only

USHFRCORDY : USHFRCO Ready Interrupt Flag Set
bits : 8 - 8
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY

HFRCORDY : HFRCO Ready Interrupt Flag Clear
bits : 0 - 0
access : write-only

HFXORDY : HFXO Ready Interrupt Flag Clear
bits : 1 - 1
access : write-only

LFRCORDY : LFRCO Ready Interrupt Flag Clear
bits : 2 - 2
access : write-only

LFXORDY : LFXO Ready Interrupt Flag Clear
bits : 3 - 3
access : write-only

AUXHFRCORDY : AUXHFRCO Ready Interrupt Flag Clear
bits : 4 - 4
access : write-only

CALRDY : Calibration Ready Interrupt Flag Clear
bits : 5 - 5
access : write-only

CALOF : Calibration Overflow Interrupt Flag Clear
bits : 6 - 6
access : write-only

USHFRCORDY : USHFRCO Ready Interrupt Flag Clear
bits : 8 - 8
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFRCORDY HFXORDY LFRCORDY LFXORDY AUXHFRCORDY CALRDY CALOF USHFRCORDY

HFRCORDY : HFRCO Ready Interrupt Enable
bits : 0 - 0
access : read-write

HFXORDY : HFXO Ready Interrupt Enable
bits : 1 - 1
access : read-write

LFRCORDY : LFRCO Ready Interrupt Enable
bits : 2 - 2
access : read-write

LFXORDY : LFXO Ready Interrupt Enable
bits : 3 - 3
access : read-write

AUXHFRCORDY : AUXHFRCO Ready Interrupt Enable
bits : 4 - 4
access : read-write

CALRDY : Calibration Ready Interrupt Enable
bits : 5 - 5
access : read-write

CALOF : Calibration Overflow Interrupt Enable
bits : 6 - 6
access : read-write

USHFRCORDY : USHFRCO Ready Interrupt Enable
bits : 8 - 8
access : read-write


HFCORECLKDIV

High Frequency Core Clock Division Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFCORECLKDIV HFCORECLKLEDIV

HFCORECLKDIV : HFCORECLK Divider
bits : 0 - 3
access : read-write

Enumeration:

0x00000000 : HFCLK

HFCORECLK = HFCLK.

0x00000001 : HFCLK2

HFCORECLK = HFCLK/2.

0x00000002 : HFCLK4

HFCORECLK = HFCLK/4.

0x00000003 : HFCLK8

HFCORECLK = HFCLK/8.

0x00000004 : HFCLK16

HFCORECLK = HFCLK/16.

0x00000005 : HFCLK32

HFCORECLK = HFCLK/32.

0x00000006 : HFCLK64

HFCORECLK = HFCLK/64.

0x00000007 : HFCLK128

HFCORECLK = HFCLK/128.

0x00000008 : HFCLK256

HFCORECLK = HFCLK/256.

0x00000009 : HFCLK512

HFCORECLK = HFCLK/512.

End of enumeration elements list.

HFCORECLKLEDIV : Additional Division Factor For HFCORECLKLE
bits : 8 - 8
access : read-write


HFCORECLKEN0

High Frequency Core Clock Enable Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES DMA LE

AES : Advanced Encryption Standard Accelerator Clock Enable
bits : 0 - 0
access : read-write

DMA : Direct Memory Access Controller Clock Enable
bits : 1 - 1
access : read-write

LE : Low Energy Peripheral Interface Clock Enable
bits : 2 - 2
access : read-write


HFPERCLKEN0

High Frequency Peripheral Clock Enable Register 0
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER0 TIMER1 TIMER2 USART0 USARTRF1 PRS IDAC0 GPIO VCMP ADC0 I2C0

TIMER0 : Timer 0 Clock Enable
bits : 0 - 0
access : read-write

TIMER1 : Timer 1 Clock Enable
bits : 1 - 1
access : read-write

TIMER2 : Timer 2 Clock Enable
bits : 2 - 2
access : read-write

USART0 : Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable
bits : 3 - 3
access : read-write

USARTRF1 : Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable
bits : 4 - 4
access : read-write

PRS : Peripheral Reflex System Clock Enable
bits : 6 - 6
access : read-write

IDAC0 : Current Digital to Analog Converter 0 Clock Enable
bits : 7 - 7
access : read-write

GPIO : General purpose Input/Output Clock Enable
bits : 8 - 8
access : read-write

VCMP : Voltage Comparator Clock Enable
bits : 9 - 9
access : read-write

ADC0 : Analog to Digital Converter 0 Clock Enable
bits : 10 - 10
access : read-write

I2C0 : I2C 0 Clock Enable
bits : 11 - 11
access : read-write


SYNCBUSY

Synchronization Busy Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFACLKEN0 LFAPRESC0 LFBCLKEN0 LFBPRESC0 LFCCLKEN0

LFACLKEN0 : Low Frequency A Clock Enable 0 Busy
bits : 0 - 0
access : read-only

LFAPRESC0 : Low Frequency A Prescaler 0 Busy
bits : 2 - 2
access : read-only

LFBCLKEN0 : Low Frequency B Clock Enable 0 Busy
bits : 4 - 4
access : read-only

LFBPRESC0 : Low Frequency B Prescaler 0 Busy
bits : 6 - 6
access : read-only

LFCCLKEN0 : Low Frequency C Clock Enable 0 Busy
bits : 8 - 8
access : read-only


FREEZE

Freeze Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE

REGFREEZE : Register Update Freeze
bits : 0 - 0
access : read-write


LFACLKEN0

Low Frequency A Clock Enable Register 0 (Async Reg)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC

RTC : Real-Time Counter Clock Enable
bits : 0 - 0
access : read-write


LFBCLKEN0

Low Frequency B Clock Enable Register 0 (Async Reg)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEUART0

LEUART0 : Low Energy UART 0 Clock Enable
bits : 0 - 0
access : read-write


LFCCLKEN0

Low Frequency C Clock Enable Register 0 (Async Reg)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBLE

USBLE : Universal Serial Bus Low Energy Clock Clock Enable
bits : 0 - 0
access : read-write


LFAPRESC0

Low Frequency A Prescaler Register 0 (Async Reg)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC

RTC : Real-Time Counter Prescaler
bits : 0 - 3
access : read-write

Enumeration:

0x00000000 : DIV1

LFACLKRTC = LFACLK

0x00000001 : DIV2

LFACLKRTC = LFACLK/2

0x00000002 : DIV4

LFACLKRTC = LFACLK/4

0x00000003 : DIV8

LFACLKRTC = LFACLK/8

0x00000004 : DIV16

LFACLKRTC = LFACLK/16

0x00000005 : DIV32

LFACLKRTC = LFACLK/32

0x00000006 : DIV64

LFACLKRTC = LFACLK/64

0x00000007 : DIV128

LFACLKRTC = LFACLK/128

0x00000008 : DIV256

LFACLKRTC = LFACLK/256

0x00000009 : DIV512

LFACLKRTC = LFACLK/512

0x0000000A : DIV1024

LFACLKRTC = LFACLK/1024

0x0000000B : DIV2048

LFACLKRTC = LFACLK/2048

0x0000000C : DIV4096

LFACLKRTC = LFACLK/4096

0x0000000D : DIV8192

LFACLKRTC = LFACLK/8192

0x0000000E : DIV16384

LFACLKRTC = LFACLK/16384

0x0000000F : DIV32768

LFACLKRTC = LFACLK/32768

End of enumeration elements list.


LFBPRESC0

Low Frequency B Prescaler Register 0 (Async Reg)
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEUART0

LEUART0 : Low Energy UART 0 Prescaler
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : DIV1

LFBCLKLEUART0 = LFBCLK

0x00000001 : DIV2

LFBCLKLEUART0 = LFBCLK/2

0x00000002 : DIV4

LFBCLKLEUART0 = LFBCLK/4

0x00000003 : DIV8

LFBCLKLEUART0 = LFBCLK/8

End of enumeration elements list.


PCNTCTRL

PCNT Control Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCNT0CLKEN PCNT0CLKSEL

PCNT0CLKEN : PCNT0 Clock Enable
bits : 0 - 0
access : read-write

PCNT0CLKSEL : PCNT0 Clock Select
bits : 1 - 1
access : read-write


HFPERCLKDIV

High Frequency Peripheral Clock Division Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HFPERCLKDIV HFPERCLKEN

HFPERCLKDIV : HFPERCLK Divider
bits : 0 - 3
access : read-write

Enumeration:

0x00000000 : HFCLK

HFPERCLK = HFCLK.

0x00000001 : HFCLK2

HFPERCLK = HFCLK/2.

0x00000002 : HFCLK4

HFPERCLK = HFCLK/4.

0x00000003 : HFCLK8

HFPERCLK = HFCLK/8.

0x00000004 : HFCLK16

HFPERCLK = HFCLK/16.

0x00000005 : HFCLK32

HFPERCLK = HFCLK/32.

0x00000006 : HFCLK64

HFPERCLK = HFCLK/64.

0x00000007 : HFCLK128

HFPERCLK = HFCLK/128.

0x00000008 : HFCLK256

HFPERCLK = HFCLK/256.

0x00000009 : HFCLK512

HFPERCLK = HFCLK/512.

End of enumeration elements list.

HFPERCLKEN : HFPERCLK Enable
bits : 8 - 8
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKOUT0PEN CLKOUT1PEN LOCATION

CLKOUT0PEN : CLKOUT0 Pin Enable
bits : 0 - 0
access : read-write

CLKOUT1PEN : CLKOUT1 Pin Enable
bits : 1 - 1
access : read-write

LOCATION : I/O Location
bits : 2 - 4
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

End of enumeration elements list.


LOCK

Configuration Lock Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : Configuration Lock Key
bits : 0 - 15
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


HFRCOCTRL

HFRCO Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING BAND SUDELAY

TUNING : HFRCO Tuning Value
bits : 0 - 7
access : read-write

BAND : HFRCO Band Select
bits : 8 - 10
access : read-write

Enumeration:

0x00000000 : 1MHZ

1 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000001 : 7MHZ

7 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000002 : 11MHZ

11 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000003 : 14MHZ

14 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

0x00000004 : 21MHZ

21 MHz band. NOTE: Also set the TUNING value (bits 7:0) when changing band.

End of enumeration elements list.

SUDELAY : HFRCO Start-up Delay
bits : 12 - 16
access : read-write


USBCRCTRL

USB Clock Recovery Control
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN LSMODE

EN : Clock Recovery Enable
bits : 0 - 0
access : read-write

LSMODE : Low Speed Clock Recovery Mode
bits : 1 - 1
access : read-write


USHFRCOCTRL

USHFRCO Control
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TUNING DITHEN SUSPEND TIMEOUT

TUNING : USHFRCO frequency adjust
bits : 0 - 6
access : read-write

DITHEN : USHFRCO dither enable
bits : 8 - 8
access : read-write

SUSPEND : USHFRCO suspend
bits : 9 - 9
access : read-write

TIMEOUT : USHFRCO Timeout
bits : 12 - 19
access : read-write


USHFRCOTUNE

USHFRCO Frequency Tune
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINETUNING

FINETUNING : Oscillator fine frequency adjust
bits : 0 - 5
access : read-write


USHFRCOCONF

USHFRCO Configuration
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BAND USHFRCODIV2DIS

BAND : USHFRCO Band Select
bits : 0 - 2
access : read-write

Enumeration:

0x00000001 : 48MHZ

48 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band.

0x00000003 : 24MHZ

24 MHz band. NOTE: Also set the TUNING and FINETUNING value when changing band.

End of enumeration elements list.

USHFRCODIV2DIS : USHFRCO divider for HFCLK disable
bits : 4 - 4
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.