TIMER2

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

IF

IFS

IFC

TOP

TOPB

CNT

ROUTE

CC0_CTRL

CC0_CCV

CC0_CCVP

CC0_CCVB

CMD

CC1_CTRL

CC1_CCV

CC1_CCVP

CC1_CCVB

CC2_CTRL

CC2_CCV

CC2_CCVP

CC2_CCVB

DTCTRL

DTTIME

DTFC

DTOGEN

STATUS

DTFAULT

DTFAULTC

DTLOCK

IEN


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE SYNC OSMEN QDM DEBUGRUN DMACLRACT RISEA FALLA X2CNT CLKSEL PRESC ATI RSSCOIST

MODE : Timer Mode
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : UP

Up-count mode

0x00000001 : DOWN

Down-count mode

0x00000002 : UPDOWN

Up/down-count mode

0x00000003 : QDEC

Quadrature decoder mode

End of enumeration elements list.

SYNC : Timer Start/Stop/Reload Synchronization
bits : 3 - 3
access : read-write

OSMEN : One-shot Mode Enable
bits : 4 - 4
access : read-write

QDM : Quadrature Decoder Mode Selection
bits : 5 - 5
access : read-write

DEBUGRUN : Debug Mode Run Enable
bits : 6 - 6
access : read-write

DMACLRACT : DMA Request Clear on Active
bits : 7 - 7
access : read-write

RISEA : Timer Rising Input Edge Action
bits : 8 - 9
access : read-write

Enumeration:

0x00000000 : NONE

No action

0x00000001 : START

Start counter without reload

0x00000002 : STOP

Stop counter without reload

0x00000003 : RELOADSTART

Reload and start counter

End of enumeration elements list.

FALLA : Timer Falling Input Edge Action
bits : 10 - 11
access : read-write

Enumeration:

0x00000000 : NONE

No action

0x00000001 : START

Start counter without reload

0x00000002 : STOP

Stop counter without reload

0x00000003 : RELOADSTART

Reload and start counter

End of enumeration elements list.

X2CNT : 2x Count Mode
bits : 13 - 13
access : read-write

CLKSEL : Clock Source Select
bits : 16 - 17
access : read-write

Enumeration:

0x00000000 : PRESCHFPERCLK

Prescaled HFPERCLK

0x00000001 : CC1

Compare/Capture Channel 1 Input

0x00000002 : TIMEROUF

Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer

End of enumeration elements list.

PRESC : Prescaler Setting
bits : 24 - 27
access : read-write

Enumeration:

0x00000000 : DIV1

The HFPERCLK is undivided

0x00000001 : DIV2

The HFPERCLK is divided by 2

0x00000002 : DIV4

The HFPERCLK is divided by 4

0x00000003 : DIV8

The HFPERCLK is divided by 8

0x00000004 : DIV16

The HFPERCLK is divided by 16

0x00000005 : DIV32

The HFPERCLK is divided by 32

0x00000006 : DIV64

The HFPERCLK is divided by 64

0x00000007 : DIV128

The HFPERCLK is divided by 128

0x00000008 : DIV256

The HFPERCLK is divided by 256

0x00000009 : DIV512

The HFPERCLK is divided by 512

0x0000000A : DIV1024

The HFPERCLK is divided by 1024

End of enumeration elements list.

ATI : Always Track Inputs
bits : 28 - 28
access : read-write

RSSCOIST : Reload-Start Sets Compare Output initial State
bits : 29 - 29
access : read-write


IF

Interrupt Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF UF CC0 CC1 CC2 ICBOF0 ICBOF1 ICBOF2

OF : Overflow Interrupt Flag
bits : 0 - 0
access : read-only

UF : Underflow Interrupt Flag
bits : 1 - 1
access : read-only

CC0 : CC Channel 0 Interrupt Flag
bits : 4 - 4
access : read-only

CC1 : CC Channel 1 Interrupt Flag
bits : 5 - 5
access : read-only

CC2 : CC Channel 2 Interrupt Flag
bits : 6 - 6
access : read-only

ICBOF0 : CC Channel 0 Input Capture Buffer Overflow Interrupt Flag
bits : 8 - 8
access : read-only

ICBOF1 : CC Channel 1 Input Capture Buffer Overflow Interrupt Flag
bits : 9 - 9
access : read-only

ICBOF2 : CC Channel 2 Input Capture Buffer Overflow Interrupt Flag
bits : 10 - 10
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF UF CC0 CC1 CC2 ICBOF0 ICBOF1 ICBOF2

OF : Overflow Interrupt Flag Set
bits : 0 - 0
access : write-only

UF : Underflow Interrupt Flag Set
bits : 1 - 1
access : write-only

CC0 : CC Channel 0 Interrupt Flag Set
bits : 4 - 4
access : write-only

CC1 : CC Channel 1 Interrupt Flag Set
bits : 5 - 5
access : write-only

CC2 : CC Channel 2 Interrupt Flag Set
bits : 6 - 6
access : write-only

ICBOF0 : CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Set
bits : 8 - 8
access : write-only

ICBOF1 : CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Set
bits : 9 - 9
access : write-only

ICBOF2 : CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Set
bits : 10 - 10
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF UF CC0 CC1 CC2 ICBOF0 ICBOF1 ICBOF2

OF : Overflow Interrupt Flag Clear
bits : 0 - 0
access : write-only

UF : Underflow Interrupt Flag Clear
bits : 1 - 1
access : write-only

CC0 : CC Channel 0 Interrupt Flag Clear
bits : 4 - 4
access : write-only

CC1 : CC Channel 1 Interrupt Flag Clear
bits : 5 - 5
access : write-only

CC2 : CC Channel 2 Interrupt Flag Clear
bits : 6 - 6
access : write-only

ICBOF0 : CC Channel 0 Input Capture Buffer Overflow Interrupt Flag Clear
bits : 8 - 8
access : write-only

ICBOF1 : CC Channel 1 Input Capture Buffer Overflow Interrupt Flag Clear
bits : 9 - 9
access : write-only

ICBOF2 : CC Channel 2 Input Capture Buffer Overflow Interrupt Flag Clear
bits : 10 - 10
access : write-only


TOP

Counter Top Value Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP

TOP : Counter Top Value
bits : 0 - 15
access : read-write


TOPB

Counter Top Value Buffer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOPB

TOPB : Counter Top Value Buffer
bits : 0 - 15
access : read-write


CNT

Counter Value Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value
bits : 0 - 15
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC0PEN CC1PEN CC2PEN CDTI0PEN CDTI1PEN CDTI2PEN LOCATION

CC0PEN : CC Channel 0 Pin Enable
bits : 0 - 0
access : read-write

CC1PEN : CC Channel 1 Pin Enable
bits : 1 - 1
access : read-write

CC2PEN : CC Channel 2 Pin Enable
bits : 2 - 2
access : read-write

CDTI0PEN : CC Channel 0 Complementary Dead-Time Insertion Pin Enable
bits : 8 - 8
access : read-write

CDTI1PEN : CC Channel 1 Complementary Dead-Time Insertion Pin Enable
bits : 9 - 9
access : read-write

CDTI2PEN : CC Channel 2 Complementary Dead-Time Insertion Pin Enable
bits : 10 - 10
access : read-write

LOCATION : I/O Location
bits : 16 - 18
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.


CC0_CTRL

CC Channel Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE OUTINV COIST CMOA COFOA CUFOA PRSSEL INSEL FILT ICEDGE ICEVCTRL PRSCONF

MODE : CC Channel Mode
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : OFF

Compare/Capture channel turned off

0x00000001 : INPUTCAPTURE

Input capture

0x00000002 : OUTPUTCOMPARE

Output compare

0x00000003 : PWM

Pulse-Width Modulation

End of enumeration elements list.

OUTINV : Output Invert
bits : 2 - 2
access : read-write

COIST : Compare Output Initial State
bits : 4 - 4
access : read-write

CMOA : Compare Match Output Action
bits : 8 - 9
access : read-write

Enumeration:

0x00000000 : NONE

No action on compare match

0x00000001 : TOGGLE

Toggle output on compare match

0x00000002 : CLEAR

Clear output on compare match

0x00000003 : SET

Set output on compare match

End of enumeration elements list.

COFOA : Counter Overflow Output Action
bits : 10 - 11
access : read-write

Enumeration:

0x00000000 : NONE

No action on counter overflow

0x00000001 : TOGGLE

Toggle output on counter overflow

0x00000002 : CLEAR

Clear output on counter overflow

0x00000003 : SET

Set output on counter overflow

End of enumeration elements list.

CUFOA : Counter Underflow Output Action
bits : 12 - 13
access : read-write

Enumeration:

0x00000000 : NONE

No action on counter underflow

0x00000001 : TOGGLE

Toggle output on counter underflow

0x00000002 : CLEAR

Clear output on counter underflow

0x00000003 : SET

Set output on counter underflow

End of enumeration elements list.

PRSSEL : Compare/Capture Channel PRS Input Channel Selection
bits : 16 - 18
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

End of enumeration elements list.

INSEL : Input Selection
bits : 20 - 20
access : read-write

FILT : Digital Filter
bits : 21 - 21
access : read-write

ICEDGE : Input Capture Edge Select
bits : 24 - 25
access : read-write

Enumeration:

0x00000000 : RISING

Rising edges detected

0x00000001 : FALLING

Falling edges detected

0x00000002 : BOTH

Both edges detected

0x00000003 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.

ICEVCTRL : Input Capture Event Control
bits : 26 - 27
access : read-write

Enumeration:

0x00000000 : EVERYEDGE

PRS output pulse, interrupt flag and DMA request set on every capture

0x00000001 : EVERYSECONDEDGE

PRS output pulse, interrupt flag and DMA request set on every second capture

0x00000002 : RISING

PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)

0x00000003 : FALLING

PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)

End of enumeration elements list.

PRSCONF : PRS Configuration
bits : 28 - 28
access : read-write


CC0_CCV

CC Channel Value Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : CC Channel Value
bits : 0 - 15
access : read-write


CC0_CCVP

CC Channel Value Peek Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCVP

CCVP : CC Channel Value Peek
bits : 0 - 15
access : read-only


CC0_CCVB

CC Channel Buffer Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCVB

CCVB : CC Channel Value Buffer
bits : 0 - 15
access : read-write


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP

START : Start Timer
bits : 0 - 0
access : write-only

STOP : Stop Timer
bits : 1 - 1
access : write-only


CC1_CTRL

CC Channel Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE OUTINV COIST CMOA COFOA CUFOA PRSSEL INSEL FILT ICEDGE ICEVCTRL PRSCONF

MODE : CC Channel Mode
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : OFF

Compare/Capture channel turned off

0x00000001 : INPUTCAPTURE

Input capture

0x00000002 : OUTPUTCOMPARE

Output compare

0x00000003 : PWM

Pulse-Width Modulation

End of enumeration elements list.

OUTINV : Output Invert
bits : 2 - 2
access : read-write

COIST : Compare Output Initial State
bits : 4 - 4
access : read-write

CMOA : Compare Match Output Action
bits : 8 - 9
access : read-write

Enumeration:

0x00000000 : NONE

No action on compare match

0x00000001 : TOGGLE

Toggle output on compare match

0x00000002 : CLEAR

Clear output on compare match

0x00000003 : SET

Set output on compare match

End of enumeration elements list.

COFOA : Counter Overflow Output Action
bits : 10 - 11
access : read-write

Enumeration:

0x00000000 : NONE

No action on counter overflow

0x00000001 : TOGGLE

Toggle output on counter overflow

0x00000002 : CLEAR

Clear output on counter overflow

0x00000003 : SET

Set output on counter overflow

End of enumeration elements list.

CUFOA : Counter Underflow Output Action
bits : 12 - 13
access : read-write

Enumeration:

0x00000000 : NONE

No action on counter underflow

0x00000001 : TOGGLE

Toggle output on counter underflow

0x00000002 : CLEAR

Clear output on counter underflow

0x00000003 : SET

Set output on counter underflow

End of enumeration elements list.

PRSSEL : Compare/Capture Channel PRS Input Channel Selection
bits : 16 - 18
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

End of enumeration elements list.

INSEL : Input Selection
bits : 20 - 20
access : read-write

FILT : Digital Filter
bits : 21 - 21
access : read-write

ICEDGE : Input Capture Edge Select
bits : 24 - 25
access : read-write

Enumeration:

0x00000000 : RISING

Rising edges detected

0x00000001 : FALLING

Falling edges detected

0x00000002 : BOTH

Both edges detected

0x00000003 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.

ICEVCTRL : Input Capture Event Control
bits : 26 - 27
access : read-write

Enumeration:

0x00000000 : EVERYEDGE

PRS output pulse, interrupt flag and DMA request set on every capture

0x00000001 : EVERYSECONDEDGE

PRS output pulse, interrupt flag and DMA request set on every second capture

0x00000002 : RISING

PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)

0x00000003 : FALLING

PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)

End of enumeration elements list.

PRSCONF : PRS Configuration
bits : 28 - 28
access : read-write


CC1_CCV

CC Channel Value Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : CC Channel Value
bits : 0 - 15
access : read-write


CC1_CCVP

CC Channel Value Peek Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCVP

CCVP : CC Channel Value Peek
bits : 0 - 15
access : read-only


CC1_CCVB

CC Channel Buffer Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCVB

CCVB : CC Channel Value Buffer
bits : 0 - 15
access : read-write


CC2_CTRL

CC Channel Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE OUTINV COIST CMOA COFOA CUFOA PRSSEL INSEL FILT ICEDGE ICEVCTRL PRSCONF

MODE : CC Channel Mode
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : OFF

Compare/Capture channel turned off

0x00000001 : INPUTCAPTURE

Input capture

0x00000002 : OUTPUTCOMPARE

Output compare

0x00000003 : PWM

Pulse-Width Modulation

End of enumeration elements list.

OUTINV : Output Invert
bits : 2 - 2
access : read-write

COIST : Compare Output Initial State
bits : 4 - 4
access : read-write

CMOA : Compare Match Output Action
bits : 8 - 9
access : read-write

Enumeration:

0x00000000 : NONE

No action on compare match

0x00000001 : TOGGLE

Toggle output on compare match

0x00000002 : CLEAR

Clear output on compare match

0x00000003 : SET

Set output on compare match

End of enumeration elements list.

COFOA : Counter Overflow Output Action
bits : 10 - 11
access : read-write

Enumeration:

0x00000000 : NONE

No action on counter overflow

0x00000001 : TOGGLE

Toggle output on counter overflow

0x00000002 : CLEAR

Clear output on counter overflow

0x00000003 : SET

Set output on counter overflow

End of enumeration elements list.

CUFOA : Counter Underflow Output Action
bits : 12 - 13
access : read-write

Enumeration:

0x00000000 : NONE

No action on counter underflow

0x00000001 : TOGGLE

Toggle output on counter underflow

0x00000002 : CLEAR

Clear output on counter underflow

0x00000003 : SET

Set output on counter underflow

End of enumeration elements list.

PRSSEL : Compare/Capture Channel PRS Input Channel Selection
bits : 16 - 18
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

End of enumeration elements list.

INSEL : Input Selection
bits : 20 - 20
access : read-write

FILT : Digital Filter
bits : 21 - 21
access : read-write

ICEDGE : Input Capture Edge Select
bits : 24 - 25
access : read-write

Enumeration:

0x00000000 : RISING

Rising edges detected

0x00000001 : FALLING

Falling edges detected

0x00000002 : BOTH

Both edges detected

0x00000003 : NONE

No edge detection, signal is left as it is

End of enumeration elements list.

ICEVCTRL : Input Capture Event Control
bits : 26 - 27
access : read-write

Enumeration:

0x00000000 : EVERYEDGE

PRS output pulse, interrupt flag and DMA request set on every capture

0x00000001 : EVERYSECONDEDGE

PRS output pulse, interrupt flag and DMA request set on every second capture

0x00000002 : RISING

PRS output pulse, interrupt flag and DMA request set on rising edge only (if ICEDGE = BOTH)

0x00000003 : FALLING

PRS output pulse, interrupt flag and DMA request set on falling edge only (if ICEDGE = BOTH)

End of enumeration elements list.

PRSCONF : PRS Configuration
bits : 28 - 28
access : read-write


CC2_CCV

CC Channel Value Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCV

CCV : CC Channel Value
bits : 0 - 15
access : read-write


CC2_CCVP

CC Channel Value Peek Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCVP

CCVP : CC Channel Value Peek
bits : 0 - 15
access : read-only


CC2_CCVB

CC Channel Buffer Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCVB

CCVB : CC Channel Value Buffer
bits : 0 - 15
access : read-write


DTCTRL

DTI Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTEN DTDAS DTIPOL DTCINV DTPRSSEL DTPRSEN

DTEN : DTI Enable
bits : 0 - 0
access : read-write

DTDAS : DTI Automatic Start-up Functionality
bits : 1 - 1
access : read-write

DTIPOL : DTI Inactive Polarity
bits : 2 - 2
access : read-write

DTCINV : DTI Complementary Output Invert.
bits : 3 - 3
access : read-write

DTPRSSEL : DTI PRS Source Channel Select
bits : 4 - 6
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as input

0x00000001 : PRSCH1

PRS Channel 1 selected as input

0x00000002 : PRSCH2

PRS Channel 2 selected as input

0x00000003 : PRSCH3

PRS Channel 3 selected as input

0x00000004 : PRSCH4

PRS Channel 4 selected as input

0x00000005 : PRSCH5

PRS Channel 5 selected as input

End of enumeration elements list.

DTPRSEN : DTI PRS Source Enable
bits : 24 - 24
access : read-write


DTTIME

DTI Time Control Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTPRESC DTRISET DTFALLT

DTPRESC : DTI Prescaler Setting
bits : 0 - 3
access : read-write

Enumeration:

0x00000000 : DIV1

The HFPERCLK is undivided

0x00000001 : DIV2

The HFPERCLK is divided by 2

0x00000002 : DIV4

The HFPERCLK is divided by 4

0x00000003 : DIV8

The HFPERCLK is divided by 8

0x00000004 : DIV16

The HFPERCLK is divided by 16

0x00000005 : DIV32

The HFPERCLK is divided by 32

0x00000006 : DIV64

The HFPERCLK is divided by 64

0x00000007 : DIV128

The HFPERCLK is divided by 128

0x00000008 : DIV256

The HFPERCLK is divided by 256

0x00000009 : DIV512

The HFPERCLK is divided by 512

0x0000000A : DIV1024

The HFPERCLK is divided by 1024

End of enumeration elements list.

DTRISET : DTI Rise-time
bits : 8 - 13
access : read-write

DTFALLT : DTI Fall-time
bits : 16 - 21
access : read-write


DTFC

DTI Fault Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTPRS0FSEL DTPRS1FSEL DTFA DTPRS0FEN DTPRS1FEN DTDBGFEN DTLOCKUPFEN

DTPRS0FSEL : DTI PRS Fault Source 0 Select
bits : 0 - 2
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as fault source 0

0x00000001 : PRSCH1

PRS Channel 1 selected as fault source 0

0x00000002 : PRSCH2

PRS Channel 2 selected as fault source 0

0x00000003 : PRSCH3

PRS Channel 3 selected as fault source 0

0x00000004 : PRSCH4

PRS Channel 4 selected as fault source 0

0x00000005 : PRSCH5

PRS Channel 5 selected as fault source 0

0x00000006 : PRSCH6

PRS Channel 6 selected as fault source 0

0x00000007 : PRSCH7

PRS Channel 7 selected as fault source 0

End of enumeration elements list.

DTPRS1FSEL : DTI PRS Fault Source 1 Select
bits : 8 - 10
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected as fault source 1

0x00000001 : PRSCH1

PRS Channel 1 selected as fault source 1

0x00000002 : PRSCH2

PRS Channel 2 selected as fault source 1

0x00000003 : PRSCH3

PRS Channel 3 selected as fault source 1

0x00000004 : PRSCH4

PRS Channel 4 selected as fault source 1

0x00000005 : PRSCH5

PRS Channel 5 selected as fault source 1

0x00000006 : PRSCH6

PRS Channel 6 selected as fault source 1

0x00000007 : PRSCH7

PRS Channel 7 selected as fault source 1

End of enumeration elements list.

DTFA : DTI Fault Action
bits : 16 - 17
access : read-write

Enumeration:

0x00000000 : NONE

No action on fault

0x00000001 : INACTIVE

Set outputs inactive

0x00000002 : CLEAR

Clear outputs

0x00000003 : TRISTATE

Tristate outputs

End of enumeration elements list.

DTPRS0FEN : DTI PRS 0 Fault Enable
bits : 24 - 24
access : read-write

DTPRS1FEN : DTI PRS 1 Fault Enable
bits : 25 - 25
access : read-write

DTDBGFEN : DTI Debugger Fault Enable
bits : 26 - 26
access : read-write

DTLOCKUPFEN : DTI Lockup Fault Enable
bits : 27 - 27
access : read-write


DTOGEN

DTI Output Generation Enable Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTOGCC0EN DTOGCC1EN DTOGCC2EN DTOGCDTI0EN DTOGCDTI1EN DTOGCDTI2EN

DTOGCC0EN : DTI CC0 Output Generation Enable
bits : 0 - 0
access : read-write

DTOGCC1EN : DTI CC1 Output Generation Enable
bits : 1 - 1
access : read-write

DTOGCC2EN : DTI CC2 Output Generation Enable
bits : 2 - 2
access : read-write

DTOGCDTI0EN : DTI CDTI0 Output Generation Enable
bits : 3 - 3
access : read-write

DTOGCDTI1EN : DTI CDTI1 Output Generation Enable
bits : 4 - 4
access : read-write

DTOGCDTI2EN : DTI CDTI2 Output Generation Enable
bits : 5 - 5
access : read-write


STATUS

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUNNING DIR TOPBV CCVBV0 CCVBV1 CCVBV2 ICV0 ICV1 ICV2 CCPOL0 CCPOL1 CCPOL2

RUNNING : Running
bits : 0 - 0
access : read-only

DIR : Direction
bits : 1 - 1
access : read-only

TOPBV : TOPB Valid
bits : 2 - 2
access : read-only

CCVBV0 : CC0 CCVB Valid
bits : 8 - 8
access : read-only

CCVBV1 : CC1 CCVB Valid
bits : 9 - 9
access : read-only

CCVBV2 : CC2 CCVB Valid
bits : 10 - 10
access : read-only

ICV0 : CC0 Input Capture Valid
bits : 16 - 16
access : read-only

ICV1 : CC1 Input Capture Valid
bits : 17 - 17
access : read-only

ICV2 : CC2 Input Capture Valid
bits : 18 - 18
access : read-only

CCPOL0 : CC0 Polarity
bits : 24 - 24
access : read-only

CCPOL1 : CC1 Polarity
bits : 25 - 25
access : read-only

CCPOL2 : CC2 Polarity
bits : 26 - 26
access : read-only


DTFAULT

DTI Fault Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTPRS0F DTPRS1F DTDBGF DTLOCKUPF

DTPRS0F : DTI PRS 0 Fault
bits : 0 - 0
access : read-only

DTPRS1F : DTI PRS 1 Fault
bits : 1 - 1
access : read-only

DTDBGF : DTI Debugger Fault
bits : 2 - 2
access : read-only

DTLOCKUPF : DTI Lockup Fault
bits : 3 - 3
access : read-only


DTFAULTC

DTI Fault Clear Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTPRS0FC DTPRS1FC DTDBGFC TLOCKUPFC

DTPRS0FC : DTI PRS0 Fault Clear
bits : 0 - 0
access : write-only

DTPRS1FC : DTI PRS1 Fault Clear
bits : 1 - 1
access : write-only

DTDBGFC : DTI Debugger Fault Clear
bits : 2 - 2
access : write-only

TLOCKUPFC : DTI Lockup Fault Clear
bits : 3 - 3
access : write-only


DTLOCK

DTI Configuration Lock Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCKKEY

LOCKKEY : DTI Lock Key
bits : 0 - 15
access : read-write

Enumeration:

0x00000000 : UNLOCKED

None

0x00000001 : LOCKED

None

End of enumeration elements list.


IEN

Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OF UF CC0 CC1 CC2 ICBOF0 ICBOF1 ICBOF2

OF : Overflow Interrupt Enable
bits : 0 - 0
access : read-write

UF : Underflow Interrupt Enable
bits : 1 - 1
access : read-write

CC0 : CC Channel 0 Interrupt Enable
bits : 4 - 4
access : read-write

CC1 : CC Channel 1 Interrupt Enable
bits : 5 - 5
access : read-write

CC2 : CC Channel 2 Interrupt Enable
bits : 6 - 6
access : read-write

ICBOF0 : CC Channel 0 Input Capture Buffer Overflow Interrupt Enable
bits : 8 - 8
access : read-write

ICBOF1 : CC Channel 1 Input Capture Buffer Overflow Interrupt Enable
bits : 9 - 9
access : read-write

ICBOF2 : CC Channel 2 Input Capture Buffer Overflow Interrupt Enable
bits : 10 - 10
access : read-write



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