LEUART0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

STARTFRAME

SIGFRAME

RXDATAX

RXDATA

RXDATAXP

TXDATAX

TXDATA

IF

IFS

IFC

IEN

PULSECTRL

CMD

FREEZE

SYNCBUSY

ROUTE

STATUS

INPUT

CLKDIV


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOTRI DATABITS PARITY STOPBITS INV ERRSDMA LOOPBK SFUBRX MPM MPAB BIT8DV RXDMAWU TXDMAWU TXDELAY

AUTOTRI : Automatic Transmitter Tristate
bits : 0 - 0
access : read-write

DATABITS : Data-Bit Mode
bits : 1 - 1
access : read-write

PARITY : Parity-Bit Mode
bits : 2 - 3
access : read-write

Enumeration:

0x00000000 : NONE

Parity bits are not used

0x00000002 : EVEN

Even parity are used. Parity bits are automatically generated and checked by hardware.

0x00000003 : ODD

Odd parity is used. Parity bits are automatically generated and checked by hardware.

End of enumeration elements list.

STOPBITS : Stop-Bit Mode
bits : 4 - 4
access : read-write

INV : Invert Input And Output
bits : 5 - 5
access : read-write

ERRSDMA : Clear RX DMA On Error
bits : 6 - 6
access : read-write

LOOPBK : Loopback Enable
bits : 7 - 7
access : read-write

SFUBRX : Start-Frame UnBlock RX
bits : 8 - 8
access : read-write

MPM : Multi-Processor Mode
bits : 9 - 9
access : read-write

MPAB : Multi-Processor Address-Bit
bits : 10 - 10
access : read-write

BIT8DV : Bit 8 Default Value
bits : 11 - 11
access : read-write

RXDMAWU : RX DMA Wakeup
bits : 12 - 12
access : read-write

TXDMAWU : TX DMA Wakeup
bits : 13 - 13
access : read-write

TXDELAY : TX Delay Transmission
bits : 14 - 15
access : read-write

Enumeration:

0x00000000 : NONE

Frames are transmitted immediately

0x00000001 : SINGLE

Transmission of new frames are delayed by a single baud period

0x00000002 : DOUBLE

Transmission of new frames are delayed by two baud periods

0x00000003 : TRIPLE

Transmission of new frames are delayed by three baud periods

End of enumeration elements list.


STARTFRAME

Start Frame Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTFRAME

STARTFRAME : Start Frame
bits : 0 - 8
access : read-write


SIGFRAME

Signal Frame Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIGFRAME

SIGFRAME : Signal Frame
bits : 0 - 8
access : read-write


RXDATAX

Receive Buffer Data Extended Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA PERR FERR

RXDATA : RX Data
bits : 0 - 8
access : read-only

PERR : Receive Data Parity Error
bits : 14 - 14
access : read-only

FERR : Receive Data Framing Error
bits : 15 - 15
access : read-only


RXDATA

Receive Buffer Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7
access : read-only


RXDATAXP

Receive Buffer Data Extended Peek Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP PERRP FERRP

RXDATAP : RX Data Peek
bits : 0 - 8
access : read-only

PERRP : Receive Data Parity Error Peek
bits : 14 - 14
access : read-only

FERRP : Receive Data Framing Error Peek
bits : 15 - 15
access : read-only


TXDATAX

Transmit Buffer Data Extended Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA TXBREAK TXDISAT RXENAT

TXDATA : TX Data
bits : 0 - 8
access : write-only

TXBREAK : Transmit Data As Break
bits : 13 - 13
access : write-only

TXDISAT : Disable TX After Transmission
bits : 14 - 14
access : write-only

RXENAT : Enable RX After Transmission
bits : 15 - 15
access : write-only


TXDATA

Transmit Buffer Data Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7
access : write-only


IF

Interrupt Flag Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXOF RXUF TXOF PERR FERR MPAF STARTF SIGF

TXC : TX Complete Interrupt Flag
bits : 0 - 0
access : read-only

TXBL : TX Buffer Level Interrupt Flag
bits : 1 - 1
access : read-only

RXDATAV : RX Data Valid Interrupt Flag
bits : 2 - 2
access : read-only

RXOF : RX Overflow Interrupt Flag
bits : 3 - 3
access : read-only

RXUF : RX Underflow Interrupt Flag
bits : 4 - 4
access : read-only

TXOF : TX Overflow Interrupt Flag
bits : 5 - 5
access : read-only

PERR : Parity Error Interrupt Flag
bits : 6 - 6
access : read-only

FERR : Framing Error Interrupt Flag
bits : 7 - 7
access : read-only

MPAF : Multi-Processor Address Frame Interrupt Flag
bits : 8 - 8
access : read-only

STARTF : Start Frame Interrupt Flag
bits : 9 - 9
access : read-only

SIGF : Signal Frame Interrupt Flag
bits : 10 - 10
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC RXOF RXUF TXOF PERR FERR MPAF STARTF SIGF

TXC : Set TX Complete Interrupt Flag
bits : 0 - 0
access : write-only

RXOF : Set RX Overflow Interrupt Flag
bits : 3 - 3
access : write-only

RXUF : Set RX Underflow Interrupt Flag
bits : 4 - 4
access : write-only

TXOF : Set TX Overflow Interrupt Flag
bits : 5 - 5
access : write-only

PERR : Set Parity Error Interrupt Flag
bits : 6 - 6
access : write-only

FERR : Set Framing Error Interrupt Flag
bits : 7 - 7
access : write-only

MPAF : Set Multi-Processor Address Frame Interrupt Flag
bits : 8 - 8
access : write-only

STARTF : Set Start Frame Interrupt Flag
bits : 9 - 9
access : write-only

SIGF : Set Signal Frame Interrupt Flag
bits : 10 - 10
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC RXOF RXUF TXOF PERR FERR MPAF STARTF SIGF

TXC : Clear TX Complete Interrupt Flag
bits : 0 - 0
access : write-only

RXOF : Clear RX Overflow Interrupt Flag
bits : 3 - 3
access : write-only

RXUF : Clear RX Underflow Interrupt Flag
bits : 4 - 4
access : write-only

TXOF : Clear TX Overflow Interrupt Flag
bits : 5 - 5
access : write-only

PERR : Clear Parity Error Interrupt Flag
bits : 6 - 6
access : write-only

FERR : Clear Framing Error Interrupt Flag
bits : 7 - 7
access : write-only

MPAF : Clear Multi-Processor Address Frame Interrupt Flag
bits : 8 - 8
access : write-only

STARTF : Clear Start-Frame Interrupt Flag
bits : 9 - 9
access : write-only

SIGF : Clear Signal-Frame Interrupt Flag
bits : 10 - 10
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXC TXBL RXDATAV RXOF RXUF TXOF PERR FERR MPAF STARTF SIGF

TXC : TX Complete Interrupt Enable
bits : 0 - 0
access : read-write

TXBL : TX Buffer Level Interrupt Enable
bits : 1 - 1
access : read-write

RXDATAV : RX Data Valid Interrupt Enable
bits : 2 - 2
access : read-write

RXOF : RX Overflow Interrupt Enable
bits : 3 - 3
access : read-write

RXUF : RX Underflow Interrupt Enable
bits : 4 - 4
access : read-write

TXOF : TX Overflow Interrupt Enable
bits : 5 - 5
access : read-write

PERR : Parity Error Interrupt Enable
bits : 6 - 6
access : read-write

FERR : Framing Error Interrupt Enable
bits : 7 - 7
access : read-write

MPAF : Multi-Processor Address Frame Interrupt Enable
bits : 8 - 8
access : read-write

STARTF : Start Frame Interrupt Enable
bits : 9 - 9
access : read-write

SIGF : Signal Frame Interrupt Enable
bits : 10 - 10
access : read-write


PULSECTRL

Pulse Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PULSEW PULSEEN PULSEFILT

PULSEW : Pulse Width
bits : 0 - 3
access : read-write

PULSEEN : Pulse Generator/Extender Enable
bits : 4 - 4
access : read-write

PULSEFILT : Pulse Filter
bits : 5 - 5
access : read-write


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXEN RXDIS TXEN TXDIS RXBLOCKEN RXBLOCKDIS CLEARTX CLEARRX

RXEN : Receiver Enable
bits : 0 - 0
access : write-only

RXDIS : Receiver Disable
bits : 1 - 1
access : write-only

TXEN : Transmitter Enable
bits : 2 - 2
access : write-only

TXDIS : Transmitter Disable
bits : 3 - 3
access : write-only

RXBLOCKEN : Receiver Block Enable
bits : 4 - 4
access : write-only

RXBLOCKDIS : Receiver Block Disable
bits : 5 - 5
access : write-only

CLEARTX : Clear TX
bits : 6 - 6
access : write-only

CLEARRX : Clear RX
bits : 7 - 7
access : write-only


FREEZE

Freeze Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE

REGFREEZE : Register Update Freeze
bits : 0 - 0
access : read-write


SYNCBUSY

Synchronization Busy Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL CMD CLKDIV STARTFRAME SIGFRAME TXDATAX TXDATA PULSECTRL

CTRL : CTRL Register Busy
bits : 0 - 0
access : read-only

CMD : CMD Register Busy
bits : 1 - 1
access : read-only

CLKDIV : CLKDIV Register Busy
bits : 2 - 2
access : read-only

STARTFRAME : STARTFRAME Register Busy
bits : 3 - 3
access : read-only

SIGFRAME : SIGFRAME Register Busy
bits : 4 - 4
access : read-only

TXDATAX : TXDATAX Register Busy
bits : 5 - 5
access : read-only

TXDATA : TXDATA Register Busy
bits : 6 - 6
access : read-only

PULSECTRL : PULSECTRL Register Busy
bits : 7 - 7
access : read-only


ROUTE

I/O Routing Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPEN TXPEN LOCATION

RXPEN : RX Pin Enable
bits : 0 - 0
access : read-write

TXPEN : TX Pin Enable
bits : 1 - 1
access : read-write

LOCATION : I/O Location
bits : 8 - 10
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

End of enumeration elements list.


STATUS

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXENS TXENS RXBLOCK TXC TXBL RXDATAV

RXENS : Receiver Enable Status
bits : 0 - 0
access : read-only

TXENS : Transmitter Enable Status
bits : 1 - 1
access : read-only

RXBLOCK : Block Incoming Data
bits : 2 - 2
access : read-only

TXC : TX Complete
bits : 3 - 3
access : read-only

TXBL : TX Buffer Level
bits : 4 - 4
access : read-only

RXDATAV : RX Data Valid
bits : 5 - 5
access : read-only


INPUT

LEUART Input Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPRSSEL RXPRS

RXPRSSEL : RX PRS Channel Select
bits : 0 - 2
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected

0x00000001 : PRSCH1

PRS Channel 1 selected

0x00000002 : PRSCH2

PRS Channel 2 selected

0x00000003 : PRSCH3

PRS Channel 3 selected

0x00000004 : PRSCH4

PRS Channel 4 selected

0x00000005 : PRSCH5

PRS Channel 5 selected

End of enumeration elements list.

RXPRS : PRS RX Enable
bits : 4 - 4
access : read-write


CLKDIV

Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Fractional Clock Divider
bits : 3 - 14
access : read-write



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