PCNT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

TOP

TOPB

IF

IFS

IFC

IEN

ROUTE

FREEZE

SYNCBUSY

AUXCNT

INPUT

CMD

STATUS

CNT


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE CNTDIR EDGE FILT RSTEN AUXCNTRSTEN HYST S1CDIR CNTEV AUXCNTEV TCCMODE TCCPRESC TCCCOMP PRSGATEEN TCCPRSPOL TCCPRSSEL

MODE : Mode Select
bits : 0 - 1
access : read-write

Enumeration:

0x00000000 : DISABLE

The module is disabled.

0x00000001 : OVSSINGLE

Single input LFACLK oversampling mode (available in EM0-EM2).

0x00000002 : EXTCLKSINGLE

Externally clocked single input counter mode (available in EM0-EM3).

0x00000003 : EXTCLKQUAD

Externally clocked quadrature decoder mode (available in EM0-EM3).

End of enumeration elements list.

CNTDIR : Non-Quadrature Mode Counter Direction Control
bits : 2 - 2
access : read-write

EDGE : Edge Select
bits : 3 - 3
access : read-write

FILT : Enable Digital Pulse Width Filter
bits : 4 - 4
access : read-write

RSTEN : Enable PCNT Clock Domain Reset
bits : 5 - 5
access : read-write

AUXCNTRSTEN : Enable AUXCNT Reset
bits : 6 - 6
access : read-write

HYST : Enable Hysteresis
bits : 8 - 8
access : read-write

S1CDIR : Count direction determined by S1
bits : 9 - 9
access : read-write

CNTEV : Controls when the counter counts
bits : 10 - 11
access : read-write

Enumeration:

0x00000000 : BOTH

Counts up on up-count and down on down-count events.

0x00000001 : UP

Only counts up on up-count events.

0x00000002 : DOWN

Only counts down on down-count events.

0x00000003 : NONE

Never counts.

End of enumeration elements list.

AUXCNTEV : Controls when the auxiliary counter counts
bits : 14 - 15
access : read-write

Enumeration:

0x00000000 : NONE

Never counts.

0x00000001 : UP

Counts up on up-count events.

0x00000002 : DOWN

Counts up on down-count events.

0x00000003 : BOTH

Counts up on both up-count and down-count events.

End of enumeration elements list.

TCCMODE : Sets the mode for triggered compare and clear
bits : 18 - 19
access : read-write

Enumeration:

0x00000000 : DISABLED

Triggered compare and clear not enabled.

0x00000001 : LFA

Compare and clear performed on each (optionally prescaled) LFA clock cycle.

0x00000002 : PRS

Compare and clear performed on positive PRS edges.

End of enumeration elements list.

TCCPRESC : Set the LFA prescaler for triggered compare and clear
bits : 22 - 23
access : read-write

Enumeration:

0x00000000 : DIV1

Compare and clear event each LFA cycle.

0x00000001 : DIV2

Compare and clear performed on every other LFA cycle.

0x00000002 : DIV4

Compare and clear performed on every 4th LFA cycle.

0x00000003 : DIV8

Compare and clear performed on every 8th LFA cycle.

End of enumeration elements list.

TCCCOMP : Triggered compare and clear compare mode
bits : 25 - 26
access : read-write

Enumeration:

0x00000000 : LTOE

Compare match if PCNT_CNT is less than, or equal to PCNT_TOP.

0x00000001 : GTOE

Compare match if PCNT_CNT is greater than or equal to PCNT_TOP.

0x00000002 : RANGE

Compare match if PCNT_CNT is less than, or equal to PCNT_TOP[15:8]], and greater than, or equal to PCNT_TOP[7:0].

End of enumeration elements list.

PRSGATEEN : PRS gate enable
bits : 27 - 27
access : read-write

TCCPRSPOL : TCC PRS polarity select
bits : 28 - 28
access : read-write

TCCPRSSEL : TCC PRS Channel Select
bits : 29 - 31
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected.

0x00000001 : PRSCH1

PRS Channel 1 selected.

0x00000002 : PRSCH2

PRS Channel 2 selected.

0x00000003 : PRSCH3

PRS Channel 3 selected.

0x00000004 : PRSCH4

PRS Channel 4 selected.

0x00000005 : PRSCH5

PRS Channel 5 selected.

End of enumeration elements list.


TOP

Top Value Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOP

TOP : Counter Top Value
bits : 0 - 15
access : read-only


TOPB

Top Value Buffer Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOPB

TOPB : Counter Top Buffer
bits : 0 - 15
access : read-write


IF

Interrupt Flag Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG AUXOF TCC

UF : Underflow Interrupt Read Flag
bits : 0 - 0
access : read-only

OF : Overflow Interrupt Read Flag
bits : 1 - 1
access : read-only

DIRCNG : Direction Change Detect Interrupt Flag
bits : 2 - 2
access : read-only

AUXOF : Overflow Interrupt Read Flag
bits : 3 - 3
access : read-only

TCC : Triggered compare Interrupt Read Flag
bits : 4 - 4
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG AUXOF TCC

UF : Underflow interrupt set
bits : 0 - 0
access : write-only

OF : Overflow Interrupt Set
bits : 1 - 1
access : write-only

DIRCNG : Direction Change Detect Interrupt Set
bits : 2 - 2
access : write-only

AUXOF : Auxiliary Overflow Interrupt Set
bits : 3 - 3
access : write-only

TCC : Triggered compare Interrupt Set
bits : 4 - 4
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG AUXOF TCC

UF : Underflow Interrupt Clear
bits : 0 - 0
access : write-only

OF : Overflow Interrupt Clear
bits : 1 - 1
access : write-only

DIRCNG : Direction Change Detect Interrupt Clear
bits : 2 - 2
access : write-only

AUXOF : Auxiliary Overflow Interrupt Clear
bits : 3 - 3
access : write-only

TCC : Triggered compare Interrupt Clear
bits : 4 - 4
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF OF DIRCNG AUXOF TCC

UF : Underflow Interrupt Enable
bits : 0 - 0
access : read-write

OF : Overflow Interrupt Enable
bits : 1 - 1
access : read-write

DIRCNG : Direction Change Detect Interrupt Enable
bits : 2 - 2
access : read-write

AUXOF : Auxiliary Overflow Interrupt Enable
bits : 3 - 3
access : read-write

TCC : Triggered compare Interrupt Enable
bits : 4 - 4
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCATION

LOCATION : I/O Location
bits : 8 - 10
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

End of enumeration elements list.


FREEZE

Freeze Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGFREEZE

REGFREEZE : Register Update Freeze
bits : 0 - 0
access : read-write


SYNCBUSY

Synchronization Busy Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL CMD TOPB

CTRL : CTRL Register Busy
bits : 0 - 0
access : read-only

CMD : CMD Register Busy
bits : 1 - 1
access : read-only

TOPB : TOPB Register Busy
bits : 2 - 2
access : read-only


AUXCNT

Auxiliary Counter Value Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXCNT

AUXCNT : Auxiliary Counter Value
bits : 0 - 15
access : read-write


INPUT

PCNT Input Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S0PRSSEL S0PRSEN S1PRSSEL S1PRSEN

S0PRSSEL : S0IN PRS Channel Select
bits : 0 - 2
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected.

0x00000001 : PRSCH1

PRS Channel 1 selected.

0x00000002 : PRSCH2

PRS Channel 2 selected.

0x00000003 : PRSCH3

PRS Channel 3 selected.

0x00000004 : PRSCH4

PRS Channel 4 selected.

0x00000005 : PRSCH5

PRS Channel 5 selected.

End of enumeration elements list.

S0PRSEN : S0IN PRS Enable
bits : 4 - 4
access : read-write

S1PRSSEL : S1IN PRS Channel Select
bits : 6 - 8
access : read-write

Enumeration:

0x00000000 : PRSCH0

PRS Channel 0 selected.

0x00000001 : PRSCH1

PRS Channel 1 selected.

0x00000002 : PRSCH2

PRS Channel 2 selected.

0x00000003 : PRSCH3

PRS Channel 3 selected.

0x00000004 : PRSCH4

PRS Channel 4 selected.

0x00000005 : PRSCH5

PRS Channel 5 selected.

End of enumeration elements list.

S1PRSEN : S1IN PRS Enable
bits : 10 - 10
access : read-write


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCNTIM LTOPBIM

LCNTIM : Load CNT Immediately
bits : 0 - 0
access : write-only

LTOPBIM : Load TOPB Immediately
bits : 1 - 1
access : write-only


STATUS

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIR

DIR : Current Counter Direction
bits : 0 - 0
access : read-only


CNT

Counter Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Counter Value
bits : 0 - 15
access : read-only



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