I2C0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

CLKDIV

SADDR

SADDRMASK

RXDATA

RXDATAP

TXDATA

IF

IFS

IFC

IEN

ROUTE

CMD

STATE

STATUS


CTRL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SLAVE AUTOACK AUTOSE AUTOSN ARBDIS GCAMEN CLHR BITO GIBITO CLTO

EN : I2C Enable
bits : 0 - 0
access : read-write

SLAVE : Addressable as Slave
bits : 1 - 1
access : read-write

AUTOACK : Automatic Acknowledge
bits : 2 - 2
access : read-write

AUTOSE : Automatic STOP when Empty
bits : 3 - 3
access : read-write

AUTOSN : Automatic STOP on NACK
bits : 4 - 4
access : read-write

ARBDIS : Arbitration Disable
bits : 5 - 5
access : read-write

GCAMEN : General Call Address Match Enable
bits : 6 - 6
access : read-write

CLHR : Clock Low High Ratio
bits : 8 - 9
access : read-write

Enumeration:

0x00000000 : STANDARD

The ratio between low period and high period counters (Nlow:Nhigh) is 4:4

0x00000001 : ASYMMETRIC

The ratio between low period and high period counters (Nlow:Nhigh) is 6:3

0x00000002 : FAST

The ratio between low period and high period counters (Nlow:Nhigh) is 11:6

End of enumeration elements list.

BITO : Bus Idle Timeout
bits : 12 - 13
access : read-write

Enumeration:

0x00000000 : OFF

Timeout disabled

0x00000001 : 40PCC

Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

0x00000002 : 80PCC

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

0x00000003 : 160PCC

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

End of enumeration elements list.

GIBITO : Go Idle on Bus Idle Timeout
bits : 15 - 15
access : read-write

CLTO : Clock Low Timeout
bits : 16 - 18
access : read-write

Enumeration:

0x00000000 : OFF

Timeout disabled

0x00000001 : 40PCC

Timeout after 40 prescaled clock cycles. In standard mode at 100 kHz, this results in a 50us timeout.

0x00000002 : 80PCC

Timeout after 80 prescaled clock cycles. In standard mode at 100 kHz, this results in a 100us timeout.

0x00000003 : 160PCC

Timeout after 160 prescaled clock cycles. In standard mode at 100 kHz, this results in a 200us timeout.

0x00000004 : 320PPC

Timeout after 320 prescaled clock cycles. In standard mode at 100 kHz, this results in a 400us timeout.

0x00000005 : 1024PPC

Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout.

End of enumeration elements list.


CLKDIV

Clock Division Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV

DIV : Clock Divider
bits : 0 - 8
access : read-write


SADDR

Slave Address Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Slave address
bits : 1 - 7
access : read-write


SADDRMASK

Slave Address Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK

MASK : Slave Address Mask
bits : 1 - 7
access : read-write


RXDATA

Receive Buffer Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATA

RXDATA : RX Data
bits : 0 - 7
access : read-only


RXDATAP

Receive Buffer Data Peek Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDATAP

RXDATAP : RX Data Peek
bits : 0 - 7
access : read-only


TXDATA

Transmit Buffer Data Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXDATA

TXDATA : TX Data
bits : 0 - 7
access : write-only


IF

Interrupt Flag Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC TXBL RXDATAV ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP

START : START condition Interrupt Flag
bits : 0 - 0
access : read-only

RSTART : Repeated START condition Interrupt Flag
bits : 1 - 1
access : read-only

ADDR : Address Interrupt Flag
bits : 2 - 2
access : read-only

TXC : Transfer Completed Interrupt Flag
bits : 3 - 3
access : read-only

TXBL : Transmit Buffer Level Interrupt Flag
bits : 4 - 4
access : read-only

RXDATAV : Receive Data Valid Interrupt Flag
bits : 5 - 5
access : read-only

ACK : Acknowledge Received Interrupt Flag
bits : 6 - 6
access : read-only

NACK : Not Acknowledge Received Interrupt Flag
bits : 7 - 7
access : read-only

MSTOP : Master STOP Condition Interrupt Flag
bits : 8 - 8
access : read-only

ARBLOST : Arbitration Lost Interrupt Flag
bits : 9 - 9
access : read-only

BUSERR : Bus Error Interrupt Flag
bits : 10 - 10
access : read-only

BUSHOLD : Bus Held Interrupt Flag
bits : 11 - 11
access : read-only

TXOF : Transmit Buffer Overflow Interrupt Flag
bits : 12 - 12
access : read-only

RXUF : Receive Buffer Underflow Interrupt Flag
bits : 13 - 13
access : read-only

BITO : Bus Idle Timeout Interrupt Flag
bits : 14 - 14
access : read-only

CLTO : Clock Low Timeout Interrupt Flag
bits : 15 - 15
access : read-only

SSTOP : Slave STOP condition Interrupt Flag
bits : 16 - 16
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP

START : Set START Interrupt Flag
bits : 0 - 0
access : write-only

RSTART : Set Repeated START Interrupt Flag
bits : 1 - 1
access : write-only

ADDR : Set Address Interrupt Flag
bits : 2 - 2
access : write-only

TXC : Set Transfer Completed Interrupt Flag
bits : 3 - 3
access : write-only

ACK : Set Acknowledge Received Interrupt Flag
bits : 6 - 6
access : write-only

NACK : Set Not Acknowledge Received Interrupt Flag
bits : 7 - 7
access : write-only

MSTOP : Set MSTOP Interrupt Flag
bits : 8 - 8
access : write-only

ARBLOST : Set Arbitration Lost Interrupt Flag
bits : 9 - 9
access : write-only

BUSERR : Set Bus Error Interrupt Flag
bits : 10 - 10
access : write-only

BUSHOLD : Set Bus Held Interrupt Flag
bits : 11 - 11
access : write-only

TXOF : Set Transmit Buffer Overflow Interrupt Flag
bits : 12 - 12
access : write-only

RXUF : Set Receive Buffer Underflow Interrupt Flag
bits : 13 - 13
access : write-only

BITO : Set Bus Idle Timeout Interrupt Flag
bits : 14 - 14
access : write-only

CLTO : Set Clock Low Interrupt Flag
bits : 15 - 15
access : write-only

SSTOP : Set SSTOP Interrupt Flag
bits : 16 - 16
access : write-only


IFC

Interrupt Flag Clear Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP

START : Clear START Interrupt Flag
bits : 0 - 0
access : write-only

RSTART : Clear Repeated START Interrupt Flag
bits : 1 - 1
access : write-only

ADDR : Clear Address Interrupt Flag
bits : 2 - 2
access : write-only

TXC : Clear Transfer Completed Interrupt Flag
bits : 3 - 3
access : write-only

ACK : Clear Acknowledge Received Interrupt Flag
bits : 6 - 6
access : write-only

NACK : Clear Not Acknowledge Received Interrupt Flag
bits : 7 - 7
access : write-only

MSTOP : Clear MSTOP Interrupt Flag
bits : 8 - 8
access : write-only

ARBLOST : Clear Arbitration Lost Interrupt Flag
bits : 9 - 9
access : write-only

BUSERR : Clear Bus Error Interrupt Flag
bits : 10 - 10
access : write-only

BUSHOLD : Clear Bus Held Interrupt Flag
bits : 11 - 11
access : write-only

TXOF : Clear Transmit Buffer Overflow Interrupt Flag
bits : 12 - 12
access : write-only

RXUF : Clear Receive Buffer Underflow Interrupt Flag
bits : 13 - 13
access : write-only

BITO : Clear Bus Idle Timeout Interrupt Flag
bits : 14 - 14
access : write-only

CLTO : Clear Clock Low Interrupt Flag
bits : 15 - 15
access : write-only

SSTOP : Clear SSTOP Interrupt Flag
bits : 16 - 16
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START RSTART ADDR TXC TXBL RXDATAV ACK NACK MSTOP ARBLOST BUSERR BUSHOLD TXOF RXUF BITO CLTO SSTOP

START : START Condition Interrupt Enable
bits : 0 - 0
access : read-write

RSTART : Repeated START condition Interrupt Enable
bits : 1 - 1
access : read-write

ADDR : Address Interrupt Enable
bits : 2 - 2
access : read-write

TXC : Transfer Completed Interrupt Enable
bits : 3 - 3
access : read-write

TXBL : Transmit Buffer level Interrupt Enable
bits : 4 - 4
access : read-write

RXDATAV : Receive Data Valid Interrupt Enable
bits : 5 - 5
access : read-write

ACK : Acknowledge Received Interrupt Enable
bits : 6 - 6
access : read-write

NACK : Not Acknowledge Received Interrupt Enable
bits : 7 - 7
access : read-write

MSTOP : MSTOP Interrupt Enable
bits : 8 - 8
access : read-write

ARBLOST : Arbitration Lost Interrupt Enable
bits : 9 - 9
access : read-write

BUSERR : Bus Error Interrupt Enable
bits : 10 - 10
access : read-write

BUSHOLD : Bus Held Interrupt Enable
bits : 11 - 11
access : read-write

TXOF : Transmit Buffer Overflow Interrupt Enable
bits : 12 - 12
access : read-write

RXUF : Receive Buffer Underflow Interrupt Enable
bits : 13 - 13
access : read-write

BITO : Bus Idle Timeout Interrupt Enable
bits : 14 - 14
access : read-write

CLTO : Clock Low Interrupt Enable
bits : 15 - 15
access : read-write

SSTOP : SSTOP Interrupt Enable
bits : 16 - 16
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDAPEN SCLPEN LOCATION

SDAPEN : SDA Pin Enable
bits : 0 - 0
access : read-write

SCLPEN : SCL Pin Enable
bits : 1 - 1
access : read-write

LOCATION : I/O Location
bits : 8 - 10
access : read-write

Enumeration:

0x00000000 : LOC0

Location 0

0x00000001 : LOC1

Location 1

0x00000002 : LOC2

Location 2

0x00000003 : LOC3

Location 3

0x00000004 : LOC4

Location 4

0x00000005 : LOC5

Location 5

0x00000006 : LOC6

Location 6

End of enumeration elements list.


CMD

Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START STOP ACK NACK CONT ABORT CLEARTX CLEARPC

START : Send start condition
bits : 0 - 0
access : write-only

STOP : Send stop condition
bits : 1 - 1
access : write-only

ACK : Send ACK
bits : 2 - 2
access : write-only

NACK : Send NACK
bits : 3 - 3
access : write-only

CONT : Continue transmission
bits : 4 - 4
access : write-only

ABORT : Abort transmission
bits : 5 - 5
access : write-only

CLEARTX : Clear TX
bits : 6 - 6
access : write-only

CLEARPC : Clear Pending Commands
bits : 7 - 7
access : write-only


STATE

State Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY MASTER TRANSMITTER NACKED BUSHOLD STATE

BUSY : Bus Busy
bits : 0 - 0
access : read-only

MASTER : Master
bits : 1 - 1
access : read-only

TRANSMITTER : Transmitter
bits : 2 - 2
access : read-only

NACKED : Nack Received
bits : 3 - 3
access : read-only

BUSHOLD : Bus Held
bits : 4 - 4
access : read-only

STATE : Transmission State
bits : 5 - 7
access : read-only

Enumeration:

0x00000000 : IDLE

No transmission is being performed.

0x00000001 : WAIT

Waiting for idle. Will send a start condition as soon as the bus is idle.

0x00000002 : START

Start transmitted or received

0x00000003 : ADDR

Address transmitted or received

0x00000004 : ADDRACK

Address ack/nack transmitted or received

0x00000005 : DATA

Data transmitted or received

0x00000006 : DATAACK

Data ack/nack transmitted or received

End of enumeration elements list.


STATUS

Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSTART PSTOP PACK PNACK PCONT PABORT TXC TXBL RXDATAV

PSTART : Pending START
bits : 0 - 0
access : read-only

PSTOP : Pending STOP
bits : 1 - 1
access : read-only

PACK : Pending ACK
bits : 2 - 2
access : read-only

PNACK : Pending NACK
bits : 3 - 3
access : read-only

PCONT : Pending continue
bits : 4 - 4
access : read-only

PABORT : Pending abort
bits : 5 - 5
access : read-only

TXC : TX Complete
bits : 6 - 6
access : read-only

TXBL : TX Buffer Level
bits : 7 - 7
access : read-only

RXDATAV : RX Data Valid
bits : 8 - 8
access : read-only



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