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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C000 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

IFC

IEN

ROUTE

GAHBCFG

GUSBCFG

GRSTCTL

GINTSTS

GINTMSK

GRXSTSR

GRXSTSP

GRXFSIZ

GNPTXFSIZ

GDFIFOCFG

DIEPTXF1

DIEPTXF2

DIEPTXF3

DCFG

DCTL

DSTS

DIEPMSK

DOEPMSK

DAINT

DAINTMSK

DIEPEMPMSK

DIEP0CTL

DIEP0INT

DIEP0TSIZ

DIEP0DMAADDR

DIEP0TXFSTS

DIEP0_CTL

DIEP0_INT

DIEP0_TSIZ

DIEP0_DMAADDR

DIEP0_TXFSTS

DIEP1_CTL

DIEP1_INT

DIEP1_TSIZ

DIEP1_DMAADDR

DIEP1_TXFSTS

DIEP2_CTL

DIEP2_INT

DIEP2_TSIZ

DIEP2_DMAADDR

DIEP2_TXFSTS

DOEP0CTL

DOEP0INT

DOEP0TSIZ

DOEP0DMAADDR

DOEP0_CTL

DOEP0_INT

DOEP0_TSIZ

DOEP0_DMAADDR

DOEP1_CTL

DOEP1_INT

DOEP1_TSIZ

DOEP1_DMAADDR

DOEP2_CTL

DOEP2_INT

DOEP2_TSIZ

DOEP2_DMAADDR

PCGCCTL

STATUS

IF

IFS


CTRL

System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMPUAP LEMOSCCTRL LEMPHYCTRL LEMIDLEEN LEMNAKEN LEMADDRMEN VREGDIS VREGOSEN BIASPROGEM01 BIASPROGEM23

DMPUAP : DMPU Active Polarity
bits : 1 - 1 (1 bit)
access : read-write

LEMOSCCTRL : Low Energy Mode Oscillator Control
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x00000000 : NONE

Low Energy Mode has no effect on neither USBC or USHFRCO.

0x00000001 : GATE

The USBC clock is gated when Low Energy Mode is active.

0x00000002 : SUSPEND

The USBC clock is gated, and USHFRCO is suspended (if not selected as HFCLK) when Low Energy Mode is active.

End of enumeration elements list.

LEMPHYCTRL : Low Energy Mode USB PHY Control
bits : 7 - 7 (1 bit)
access : read-write

LEMIDLEEN : Low Energy Mode on Bus Idle Enable
bits : 9 - 9 (1 bit)
access : read-write

LEMNAKEN : Low Energy Mode on OUT NAK Enable
bits : 10 - 10 (1 bit)
access : read-write

LEMADDRMEN : Low Energy Mode on Device Address Mismatch Enable
bits : 11 - 11 (1 bit)
access : read-write

VREGDIS : Voltage Regulator Disable
bits : 16 - 16 (1 bit)
access : read-write

VREGOSEN : VREGO Sense Enable
bits : 17 - 17 (1 bit)
access : read-write

BIASPROGEM01 : Regulator Bias Programming Value in EM0/1
bits : 20 - 21 (2 bit)
access : read-write

BIASPROGEM23 : Regulator Bias Programming Value in EM2/3
bits : 24 - 25 (2 bit)
access : read-write


IFC

Interrupt Flag Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFC IFC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREGOSH VREGOSL

VREGOSH : Clear VREGO Sense High Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

VREGOSL : Clear VREGO Sense Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only


IEN

Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IEN IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREGOSH VREGOSL

VREGOSH : VREGO Sense High Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

VREGOSL : VREGO Sense Low Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write


ROUTE

I/O Routing Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ROUTE ROUTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYPEN DMPUPEN

PHYPEN : USB PHY Pin Enable
bits : 0 - 0 (1 bit)
access : read-write

DMPUPEN : DMPU Pin Enable
bits : 2 - 2 (1 bit)
access : read-write


GAHBCFG

AHB Configuration Register
address_offset : 0x3C008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAHBCFG GAHBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLBLINTRMSK HBSTLEN DMAEN NPTXFEMPLVL REMMEMSUPP NOTIALLDMAWRIT AHBSINGLE

GLBLINTRMSK : Global Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

HBSTLEN : Burst Length/Type
bits : 1 - 4 (4 bit)
access : read-write

Enumeration:

0x00000000 : SINGLE

Single transfer.

0x00000001 : INCR

Incrementing burst of unspecified length.

0x00000003 : INCR4

4-beat incrementing burst.

0x00000005 : INCR8

8-beat incrementing burst.

0x00000007 : INCR16

16-beat incrementing burst.

End of enumeration elements list.

DMAEN : DMA Enable
bits : 5 - 5 (1 bit)
access : read-write

NPTXFEMPLVL : Non-Periodic TxFIFO Empty Level
bits : 7 - 7 (1 bit)
access : read-write

REMMEMSUPP : Remote Memory Support
bits : 21 - 21 (1 bit)
access : read-write

NOTIALLDMAWRIT : Notify All DMA Writes
bits : 22 - 22 (1 bit)
access : read-write

AHBSINGLE : AHB Single Support
bits : 23 - 23 (1 bit)
access : read-write


GUSBCFG

USB Configuration Register
address_offset : 0x3C00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUSBCFG GUSBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUTCAL FSINTF USBTRDTIM TERMSELDLPULSE TXENDDELAY CORRUPTTXPKT

TOUTCAL : Timeout Calibration
bits : 0 - 2 (3 bit)
access : read-write

FSINTF : Full-Speed Serial Interface Select
bits : 5 - 5 (1 bit)
access : read-write

USBTRDTIM : USB Turnaround Time
bits : 10 - 13 (4 bit)
access : read-write

TERMSELDLPULSE : TermSel DLine Pulsing Selection
bits : 22 - 22 (1 bit)
access : read-write

TXENDDELAY : Tx End Delay
bits : 28 - 28 (1 bit)
access : read-write

CORRUPTTXPKT : Corrupt Tx packet
bits : 31 - 31 (1 bit)
access : write-only


GRSTCTL

Reset Register
address_offset : 0x3C010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRSTCTL GRSTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSFTRST PIUFSSFTRST RXFFLSH TXFFLSH TXFNUM DMAREQ AHBIDLE

CSFTRST : Core Soft Reset
bits : 0 - 0 (1 bit)
access : read-write

PIUFSSFTRST : PIU FS Dedicated Controller Soft Reset
bits : 1 - 1 (1 bit)
access : read-write

RXFFLSH : RxFIFO Flush
bits : 4 - 4 (1 bit)
access : read-write

TXFFLSH : TxFIFO Flush
bits : 5 - 5 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 6 - 10 (5 bit)
access : read-write

Enumeration:

0x00000000 : F0

Host mode: Non-periodic TxFIFO flush. Device: Tx FIFO 0 flush

0x00000001 : F1

Host mode: Periodic TxFIFO flush. Device: TXFIFO 1 flush.

0x00000002 : F2

Device mode: TXFIFO 2 flush.

0x00000003 : F3

Device mode: TXFIFO 3 flush.

0x00000004 : F4

Device mode: TXFIFO 4 flush.

0x00000005 : F5

Device mode: TXFIFO 5 flush.

0x00000006 : F6

Device mode: TXFIFO 6 flush.

0x00000010 : FALL

Flush all the transmit FIFOs in device or host mode.

End of enumeration elements list.

DMAREQ : DMA Request Signal
bits : 30 - 30 (1 bit)
access : read-only

AHBIDLE : AHB Master Idle
bits : 31 - 31 (1 bit)
access : read-only


GINTSTS

Interrupt Register
address_offset : 0x3C014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTSTS GINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURMOD SOF RXFLVL GINNAKEFF GOUTNAKEFF ERLYSUSP USBSUSP USBRST ENUMDONE ISOOUTDROP EOPF IEPINT OEPINT INCOMPISOIN INCOMPLP FETSUSP RESETDET WKUPINT

CURMOD : Current Mode of Operation
bits : 0 - 0 (1 bit)
access : read-only

SOF : Start of Frame
bits : 3 - 3 (1 bit)
access : read-write

RXFLVL : RxFIFO Non-Empty
bits : 4 - 4 (1 bit)
access : read-only

GINNAKEFF : Global IN Non-periodic NAK Effective
bits : 6 - 6 (1 bit)
access : read-only

GOUTNAKEFF : Global OUT NAK Effective
bits : 7 - 7 (1 bit)
access : read-only

ERLYSUSP : Early Suspend
bits : 10 - 10 (1 bit)
access : read-write

USBSUSP : USB Suspend
bits : 11 - 11 (1 bit)
access : read-write

USBRST : USB Reset
bits : 12 - 12 (1 bit)
access : read-write

ENUMDONE : Enumeration Done
bits : 13 - 13 (1 bit)
access : read-write

ISOOUTDROP : Isochronous OUT Packet Dropped Interrupt
bits : 14 - 14 (1 bit)
access : read-write

EOPF : End of Periodic Frame Interrupt
bits : 15 - 15 (1 bit)
access : read-write

IEPINT : IN Endpoints Interrupt
bits : 18 - 18 (1 bit)
access : read-only

OEPINT : OUT Endpoints Interrupt
bits : 19 - 19 (1 bit)
access : read-only

INCOMPISOIN : Incomplete Isochronous IN Transfer
bits : 20 - 20 (1 bit)
access : read-write

INCOMPLP : Incomplete Periodic Transfer
bits : 21 - 21 (1 bit)
access : read-write

FETSUSP : Data Fetch Suspended
bits : 22 - 22 (1 bit)
access : read-write

RESETDET : Reset detected Interrupt
bits : 23 - 23 (1 bit)
access : read-write

WKUPINT : Resume/Remote Wakeup Detected Interrupt
bits : 31 - 31 (1 bit)
access : read-write


GINTMSK

Interrupt Mask Register
address_offset : 0x3C018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTMSK GINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEMISMSK SOFMSK RXFLVLMSK GINNAKEFFMSK GOUTNAKEFFMSK ERLYSUSPMSK USBSUSPMSK USBRSTMSK ENUMDONEMSK ISOOUTDROPMSK EOPFMSK IEPINTMSK OEPINTMSK INCOMPISOINMSK INCOMPLPMSK FETSUSPMSK RESETDETMSK WKUPINTMSK

MODEMISMSK : Mode Mismatch Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write

SOFMSK : Start of Frame Mask
bits : 3 - 3 (1 bit)
access : read-write

RXFLVLMSK : Receive FIFO Non-Empty Mask
bits : 4 - 4 (1 bit)
access : read-write

GINNAKEFFMSK : Global Non-periodic IN NAK Effective Mask
bits : 6 - 6 (1 bit)
access : read-write

GOUTNAKEFFMSK : Global OUT NAK Effective Mask
bits : 7 - 7 (1 bit)
access : read-write

ERLYSUSPMSK : Early Suspend Mask
bits : 10 - 10 (1 bit)
access : read-write

USBSUSPMSK : USB Suspend Mask
bits : 11 - 11 (1 bit)
access : read-write

USBRSTMSK : USB Reset Mask
bits : 12 - 12 (1 bit)
access : read-write

ENUMDONEMSK : Enumeration Done Mask
bits : 13 - 13 (1 bit)
access : read-write

ISOOUTDROPMSK : Isochronous OUT Packet Dropped Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-write

EOPFMSK : End of Periodic Frame Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-write

IEPINTMSK : IN Endpoints Interrupt Mask
bits : 18 - 18 (1 bit)
access : read-write

OEPINTMSK : OUT Endpoints Interrupt Mask
bits : 19 - 19 (1 bit)
access : read-write

INCOMPISOINMSK : Incomplete Isochronous IN Transfer Mask
bits : 20 - 20 (1 bit)
access : read-write

INCOMPLPMSK : Incomplete Periodic Transfer Mask
bits : 21 - 21 (1 bit)
access : read-write

FETSUSPMSK : Data Fetch Suspended Mask
bits : 22 - 22 (1 bit)
access : read-write

RESETDETMSK : Reset detected Interrupt Mask
bits : 23 - 23 (1 bit)
access : read-write

WKUPINTMSK : Resume/Remote Wakeup Detected Interrupt Mask
bits : 31 - 31 (1 bit)
access : read-write


GRXSTSR

Receive Status Debug Read Register
address_offset : 0x3C01C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GRXSTSR GRXSTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEPNUM BCNT DPID PKTSTS FN

CHEPNUM : Channel Number host only / Endpoint Number
bits : 0 - 3 (4 bit)
access : read-only

BCNT : Byte Count (host or device)
bits : 4 - 14 (11 bit)
access : read-only

DPID : Data PID (host or device)
bits : 15 - 16 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA1

DATA1 PID.

0x00000002 : DATA2

DATA2 PID.

0x00000003 : MDATA

MDATA PID.

End of enumeration elements list.

PKTSTS : Packet Status (host or device)
bits : 17 - 20 (4 bit)
access : read-only

Enumeration:

0x00000001 : GOUTNAK

Device mode: Global OUT NAK (triggers an interrupt).

0x00000002 : PKTRCV

Host mode: IN data packet received. Device mode: OUT data packet received.

0x00000003 : XFERCOMPL

Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).

0x00000004 : SETUPCOMPL

Device mode: SETUP transaction completed (triggers an interrupt).

0x00000005 : TGLERR

Host mode: Data toggle error (triggers an interrupt).

0x00000006 : SETUPRCV

Device mode: SETUP data packet received.

0x00000007 : CHLT

Host mode: Channel halted (triggers an interrupt).

End of enumeration elements list.

FN : Frame Number
bits : 21 - 24 (4 bit)
access : read-only


GRXSTSP

Receive Status Read and Pop Register
address_offset : 0x3C020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GRXSTSP GRXSTSP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEPNUM BCNT DPID PKTSTS FN

CHEPNUM : Channel Number host only / Endpoint Number
bits : 0 - 3 (4 bit)
access : read-only

BCNT : Byte Count (host or device)
bits : 4 - 14 (11 bit)
access : read-only

DPID : Data PID (host or device)
bits : 15 - 16 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA1

DATA1 PID.

0x00000002 : DATA2

DATA2 PID.

0x00000003 : MDATA

MDATA PID.

End of enumeration elements list.

PKTSTS : Packet Status (host or device)
bits : 17 - 20 (4 bit)
access : read-only

Enumeration:

0x00000001 : GOUTNAK

Device mode: Global OUT NAK (triggers an interrupt).

0x00000002 : PKTRCV

Host mode: IN data packet received. Device mode: OUT data packet received.

0x00000003 : XFERCOMPL

Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).

0x00000004 : SETUPCOMPL

Device mode: SETUP transaction completed (triggers an interrupt).

0x00000005 : TGLERR

Host mode: Data toggle error (triggers an interrupt).

0x00000006 : SETUPRCV

Device mode: SETUP data packet received.

0x00000007 : CHLT

Host mode: Channel halted (triggers an interrupt).

End of enumeration elements list.

FN : Frame Number
bits : 21 - 24 (4 bit)
access : read-only


GRXFSIZ

Receive FIFO Size Register
address_offset : 0x3C024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRXFSIZ GRXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFDEP

RXFDEP : RxFIFO Depth
bits : 0 - 9 (10 bit)
access : read-write


GNPTXFSIZ

Non-periodic Transmit FIFO Size Register
address_offset : 0x3C028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GNPTXFSIZ GNPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTXFSTADDR NPTXFINEPTXF0DEP

NPTXFSTADDR : Non-periodic Transmit RAM Start Address host only
bits : 0 - 9 (10 bit)
access : read-write

NPTXFINEPTXF0DEP : Non-periodic TxFIFO Depth host only / IN Endpoint TxFIFO 0 Depth
bits : 16 - 31 (16 bit)
access : read-write


GDFIFOCFG

Global DFIFO Configuration Register
address_offset : 0x3C05C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GDFIFOCFG GDFIFOCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GDFIFOCFG EPINFOBASEADDR

GDFIFOCFG : DFIFO Config
bits : 0 - 15 (16 bit)
access : read-write

EPINFOBASEADDR : Endpoint Info Base Address
bits : 16 - 31 (16 bit)
access : read-write


DIEPTXF1

Device IN Endpoint Transmit FIFO 1 Size Register
address_offset : 0x3C104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF1 DIEPTXF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFO 1 Transmit RAM Start Address
bits : 0 - 10 (11 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF2

Device IN Endpoint Transmit FIFO 2 Size Register
address_offset : 0x3C108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF2 DIEPTXF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFO 2 Transmit RAM Start Address
bits : 0 - 10 (11 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DIEPTXF3

Device IN Endpoint Transmit FIFO 3 Size Register
address_offset : 0x3C10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF3 DIEPTXF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPNTXFSTADDR INEPNTXFDEP

INEPNTXFSTADDR : IN Endpoint FIFO 3 Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write

INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write


DCFG

Device Configuration Register
address_offset : 0x3C800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG DCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVSPD NZSTSOUTHSHK ENA32KHZSUSP DEVADDR PERFRINT ERRATICINTMSK RESVALID

DEVSPD : Device Speed
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000002 : LS

Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.

0x00000003 : FS

Full speed (PHY clock is 48 MHz).

End of enumeration elements list.

NZSTSOUTHSHK : Non-Zero-Length Status OUT Handshake
bits : 2 - 2 (1 bit)
access : read-write

ENA32KHZSUSP : Enable 32 KHz Suspend mode
bits : 3 - 3 (1 bit)
access : read-write

DEVADDR : Device Address
bits : 4 - 10 (7 bit)
access : read-write

PERFRINT : Periodic Frame Interval
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x00000000 : 80PCNT

80% of the frame interval.

0x00000001 : 85PCNT

85% of the frame interval.

0x00000002 : 90PCNT

90% of the frame interval.

0x00000003 : 95PCNT

95% of the frame interval.

End of enumeration elements list.

ERRATICINTMSK :
bits : 15 - 15 (1 bit)
access : read-write

RESVALID : Resume Validation Period
bits : 26 - 31 (6 bit)
access : read-write


DCTL

Device Control Register
address_offset : 0x3C804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTL DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMTWKUPSIG SFTDISCON GNPINNAKSTS GOUTNAKSTS TSTCTL SGNPINNAK CGNPINNAK SGOUTNAK CGOUTNAK PWRONPRGDONE IGNRFRMNUM NAKONBBLE

RMTWKUPSIG : Remote Wakeup Signaling
bits : 0 - 0 (1 bit)
access : read-write

SFTDISCON : Soft Disconnect
bits : 1 - 1 (1 bit)
access : read-write

GNPINNAKSTS : Global Non-periodic IN NAK Status
bits : 2 - 2 (1 bit)
access : read-only

GOUTNAKSTS : Global OUT NAK Status
bits : 3 - 3 (1 bit)
access : read-only

TSTCTL : Test Control
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x00000000 : DISABLE

Test mode disabled.

0x00000001 : J

Test_J mode.

0x00000002 : K

Test_K mode.

0x00000003 : SE0NAK

Test_SE0_NAK mode.

0x00000004 : PACKET

Test_Packet mode.

0x00000005 : FORCE

Test_Force_Enable.

End of enumeration elements list.

SGNPINNAK : Set Global Non-periodic IN NAK
bits : 7 - 7 (1 bit)
access : write-only

CGNPINNAK : Clear Global Non-periodic IN NAK
bits : 8 - 8 (1 bit)
access : write-only

SGOUTNAK : Set Global OUT NAK
bits : 9 - 9 (1 bit)
access : write-only

CGOUTNAK : Clear Global OUT NAK
bits : 10 - 10 (1 bit)
access : write-only

PWRONPRGDONE : Power-On Programming Done
bits : 11 - 11 (1 bit)
access : read-write

IGNRFRMNUM : Ignore Frame number For Isochronous End points
bits : 15 - 15 (1 bit)
access : read-write

NAKONBBLE : NAK on Babble Error
bits : 16 - 16 (1 bit)
access : read-write


DSTS

Device Status Register
address_offset : 0x3C808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DSTS DSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPSTS ENUMSPD ERRTICERR SOFFN DEVLNSTS

SUSPSTS : Suspend Status
bits : 0 - 0 (1 bit)
access : read-only

ENUMSPD : Enumerated Speed
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

0x00000002 : LS

Low speed (PHY clock is running at 6 MHz).

0x00000003 : FS

Full speed (PHY clock is running at 48 MHz).

End of enumeration elements list.

ERRTICERR : Erratic Error
bits : 3 - 3 (1 bit)
access : read-only

SOFFN : Frame Number of the Received SOF
bits : 8 - 21 (14 bit)
access : read-only

DEVLNSTS : Device Line Status
bits : 22 - 23 (2 bit)
access : read-only


DIEPMSK

Device IN Endpoint Common Interrupt Mask Register
address_offset : 0x3C810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPMSK DIEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK EPDISBLDMSK AHBERRMSK TIMEOUTMSK INTKNTXFEMPMSK INEPNAKEFFMSK TXFIFOUNDRNMSK NAKMSK

XFERCOMPLMSK : Transfer Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLDMSK : Endpoint Disabled Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUTMSK : Timeout Condition Mask
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMPMSK : IN Token Received When TxFIFO Empty Mask
bits : 4 - 4 (1 bit)
access : read-write

INEPNAKEFFMSK : IN Endpoint NAK Effective Mask
bits : 6 - 6 (1 bit)
access : read-write

TXFIFOUNDRNMSK : Fifo Underrun Mask
bits : 8 - 8 (1 bit)
access : read-write

NAKMSK : NAK interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write


DOEPMSK

Device OUT Endpoint Common Interrupt Mask Register
address_offset : 0x3C814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPMSK DOEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPLMSK EPDISBLDMSK AHBERRMSK SETUPMSK OUTTKNEPDISMSK STSPHSERCVDMSK BACK2BACKSETUP OUTPKTERRMSK BBLEERRMSK NAKMSK

XFERCOMPLMSK : Transfer Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLDMSK : Endpoint Disabled Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write

AHBERRMSK : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUPMSK : SETUP Phase Done Mask
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDISMSK : OUT Token Received when Endpoint Disabled Mask
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVDMSK : Status Phase Received Mask
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received Mask
bits : 6 - 6 (1 bit)
access : read-write

OUTPKTERRMSK : OUT Packet Error Mask
bits : 8 - 8 (1 bit)
access : read-write

BBLEERRMSK : Babble Error interrupt Mask
bits : 12 - 12 (1 bit)
access : read-write

NAKMSK : NAK interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write


DAINT

Device All Endpoints Interrupt Register
address_offset : 0x3C818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DAINT DAINT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPINT0 INEPINT1 INEPINT2 INEPINT3 OUTEPINT0 OUTEPINT1 OUTEPINT2 OUTEPINT3

INEPINT0 : IN Endpoint 0 Interrupt Bit
bits : 0 - 0 (1 bit)
access : read-only

INEPINT1 : IN Endpoint 1 Interrupt Bit
bits : 1 - 1 (1 bit)
access : read-only

INEPINT2 : IN Endpoint 2 Interrupt Bit
bits : 2 - 2 (1 bit)
access : read-only

INEPINT3 : IN Endpoint 3 Interrupt Bit
bits : 3 - 3 (1 bit)
access : read-only

OUTEPINT0 : OUT Endpoint 0 Interrupt Bit
bits : 16 - 16 (1 bit)
access : read-only

OUTEPINT1 : OUT Endpoint 1 Interrupt Bit
bits : 17 - 17 (1 bit)
access : read-only

OUTEPINT2 : OUT Endpoint 2 Interrupt Bit
bits : 18 - 18 (1 bit)
access : read-only

OUTEPINT3 : OUT Endpoint 3 Interrupt Bit
bits : 19 - 19 (1 bit)
access : read-only


DAINTMSK

Device All Endpoints Interrupt Mask Register
address_offset : 0x3C81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAINTMSK DAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPMSK0 INEPMSK1 INEPMSK2 INEPMSK3 OUTEPMSK0 OUTEPMSK1 OUTEPMSK2 OUTEPMSK3

INEPMSK0 : IN Endpoint 0 Interrupt mask Bit
bits : 0 - 0 (1 bit)
access : read-write

INEPMSK1 : IN Endpoint 1 Interrupt mask Bit
bits : 1 - 1 (1 bit)
access : read-write

INEPMSK2 : IN Endpoint 2 Interrupt mask Bit
bits : 2 - 2 (1 bit)
access : read-write

INEPMSK3 : IN Endpoint 3 Interrupt mask Bit
bits : 3 - 3 (1 bit)
access : read-write

OUTEPMSK0 : OUT Endpoint 0 Interrupt mask Bit
bits : 16 - 16 (1 bit)
access : read-write

OUTEPMSK1 : OUT Endpoint 1 Interrupt mask Bit
bits : 17 - 17 (1 bit)
access : read-write

OUTEPMSK2 : OUT Endpoint 2 Interrupt mask Bit
bits : 18 - 18 (1 bit)
access : read-write

OUTEPMSK3 : OUT Endpoint 3 Interrupt mask Bit
bits : 19 - 19 (1 bit)
access : read-write


DIEPEMPMSK

Device IN Endpoint FIFO Empty Interrupt Mask Register
address_offset : 0x3C834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPEMPMSK DIEPEMPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIEPEMPMSK

DIEPEMPMSK : IN EP Tx FIFO Empty Interrupt Mask Bits
bits : 0 - 15 (16 bit)
access : read-write


DIEP0CTL

Device IN Endpoint 0 Control Register
address_offset : 0x3C900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0CTL DIEP0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP NAKSTS EPTYPE STALL TXFNUM CNAK SNAK EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0x00000000 : 64B

64 bytes.

0x00000001 : 32B

32 bytes.

0x00000002 : 16B

16 bytes.

0x00000003 : 8B

8 bytes.

End of enumeration elements list.

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP0INT

Device IN Endpoint 0 Interrupt Register
address_offset : 0x3C908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0INT DIEP0INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INEPNAKEFF TXFEMP PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP0TSIZ

Device IN Endpoint 0 Transfer Size Register
address_offset : 0x3C910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0TSIZ DIEP0TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT

XFERSIZE : Transfer Size
bits : 0 - 6 (7 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 20 (2 bit)
access : read-write


DIEP0DMAADDR

Device IN Endpoint 0 DMA Address Register
address_offset : 0x3C914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0DMAADDR DIEP0DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIEP0DMAADDR

DIEP0DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DIEP0TXFSTS

Device IN Endpoint 0 Transmit FIFO Status Register
address_offset : 0x3C918 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP0TXFSTS DIEP0TXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only


DIEP0_CTL

Device IN Endpoint x+1 Control Register
address_offset : 0x3C920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_CTL DIEP0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP0_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_INT DIEP0_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INEPNAKEFF TXFEMP PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP0_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_TSIZ DIEP0_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP0_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP0_DMAADDR DIEP0_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DIEP0_TXFSTS

Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C938 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP0_TXFSTS DIEP0_TXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only


DIEP1_CTL

Device IN Endpoint x+1 Control Register
address_offset : 0x3C940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_CTL DIEP1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP1_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_INT DIEP1_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INEPNAKEFF TXFEMP PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP1_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_TSIZ DIEP1_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP1_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP1_DMAADDR DIEP1_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DIEP1_TXFSTS

Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C958 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP1_TXFSTS DIEP1_TXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only


DIEP2_CTL

Device IN Endpoint x+1 Control Register
address_offset : 0x3C960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_CTL DIEP2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE STALL TXFNUM CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DIEP2_INT

Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_INT DIEP2_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR TIMEOUT INTKNTXFEMP INEPNAKEFF TXFEMP PKTDRPSTS BBLEERR NAKINTRPT

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write

INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write

INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write

TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write


DIEP2_TSIZ

Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_TSIZ DIEP2_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT MC

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write


DIEP2_DMAADDR

Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEP2_DMAADDR DIEP2_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DIEP2_TXFSTS

Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C978 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DIEP2_TXFSTS DIEP2_TXFSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPCAVAIL

SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only


DOEP0CTL

Device OUT Endpoint 0 Control Register
address_offset : 0x3CB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0CTL DOEP0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP NAKSTS EPTYPE SNP STALL CNAK SNAK EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 1 (2 bit)
access : read-only

Enumeration:

0x00000000 : 64B

64 bytes.

0x00000001 : 32B

32 bytes.

0x00000002 : 16B

16 bytes.

0x00000003 : 8B

8 bytes.

End of enumeration elements list.

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-only

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP0INT

Device OUT Endpoint 0 Interrupt Register
address_offset : 0x3CB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0INT DOEP0INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD : Setup Packet Received
bits : 15 - 15 (1 bit)
access : read-write


DOEP0TSIZ

Device OUT Endpoint 0 Transfer Size Register
address_offset : 0x3CB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0TSIZ DOEP0TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT SUPCNT

XFERSIZE : Transfer Size
bits : 0 - 6 (7 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 19 (1 bit)
access : read-write

SUPCNT : SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-write


DOEP0DMAADDR

Device OUT Endpoint 0 DMA Address Register
address_offset : 0x3CB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0DMAADDR DOEP0DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOEP0DMAADDR

DOEP0DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DOEP0_CTL

Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_CTL DOEP0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP0_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_INT DOEP0_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD : Setup Packet Received
bits : 15 - 15 (1 bit)
access : read-write


DOEP0_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_TSIZ DOEP0_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP0_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP0_DMAADDR DOEP0_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DOEP1_CTL

Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_CTL DOEP1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP1_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_INT DOEP1_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD : Setup Packet Received
bits : 15 - 15 (1 bit)
access : read-write


DOEP1_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_TSIZ DOEP1_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP1_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP1_DMAADDR DOEP1_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


DOEP2_CTL

Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_CTL DOEP2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS USBACTEP DPIDEOF NAKSTS EPTYPE SNP STALL CNAK SNAK SETD0PIDEF SETD1PIDOF EPDIS EPENA

MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write

USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write

DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only

NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only

EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

0x00000000 : CONTROL

Control Endpoint.

0x00000001 : ISO

Isochronous Endpoint.

0x00000002 : BULK

Bulk Endpoint.

0x00000003 : INT

Interrupt Endpoint.

End of enumeration elements list.

SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write

STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write

CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only

SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only

SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only

SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only

EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write

EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write


DOEP2_INT

Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_INT DOEP2_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERCOMPL EPDISBLD AHBERR SETUP OUTTKNEPDIS STSPHSERCVD BACK2BACKSETUP PKTDRPSTS BBLEERR NAKINTRPT STUPPKTRCVD

XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write

EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write

AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write

SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write

OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write

STSPHSERCVD : Status Phase Received For Control Write
bits : 5 - 5 (1 bit)
access : read-write

BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write

PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write

BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write

NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write

STUPPKTRCVD : Setup Packet Received
bits : 15 - 15 (1 bit)
access : read-write


DOEP2_TSIZ

Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_TSIZ DOEP2_TSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XFERSIZE PKTCNT RXDPIDSUPCNT

XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write

PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write

RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only

Enumeration:

0x00000000 : DATA0

DATA0 PID.

0x00000001 : DATA2

DATA2 PID / 1 Packet.

0x00000002 : DATA1

DATA1 PID / 2 Packets.

0x00000003 : MDATA

MDATA PID / 3 Packets.

End of enumeration elements list.


DOEP2_DMAADDR

Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEP2_DMAADDR DOEP2_DMAADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAADDR

DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write


PCGCCTL

Power and Clock Gating Control Register
address_offset : 0x3CE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCGCCTL PCGCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOPPCLK GATEHCLK PWRCLMP RSTPDWNMODULE PHYSLEEP

STOPPCLK : Stop PHY clock
bits : 0 - 0 (1 bit)
access : read-write

GATEHCLK : Gate HCLK
bits : 1 - 1 (1 bit)
access : read-write

PWRCLMP : Power Clamp
bits : 2 - 2 (1 bit)
access : read-write

RSTPDWNMODULE : Reset Power-Down Modules
bits : 3 - 3 (1 bit)
access : read-write

PHYSLEEP : PHY In Sleep
bits : 6 - 6 (1 bit)
access : read-only


STATUS

System Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREGOS LEMACTIVE

VREGOS : VREGO Sense Output
bits : 0 - 0 (1 bit)
access : read-only

LEMACTIVE : Low Energy Mode Active
bits : 2 - 2 (1 bit)
access : read-only


IF

Interrupt Flag Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IF IF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREGOSH VREGOSL

VREGOSH : VREGO Sense High Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only

VREGOSL : VREGO Sense Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only


IFS

Interrupt Flag Set Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IFS IFS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREGOSH VREGOSL

VREGOSH : Set VREGO Sense High Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only

VREGOSL : Set VREGO Sense Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only



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