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MTB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

POSITION

MASTER

FLOW

BASE


POSITION

MTB Trace Position Register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POSITION POSITION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRAP POINTER

WRAP : Trace wrap bit.
bits : 2 - 2 (1 bit)
access : read-write

POINTER : Trace packet location pointer.
bits : 3 - 31 (29 bit)
access : read-write


MASTER

MTB Trace Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASTER MASTER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASK TSTARTEN TSTOPEN HALTREQ EN

MASK : This value determines the maximum size of the trace buffer in SRAM.
bits : 0 - 4 (5 bit)
access : read-write

TSTARTEN : Trace start input enable.
bits : 5 - 5 (1 bit)
access : read-write

TSTOPEN : Trace stop input enable.
bits : 6 - 6 (1 bit)
access : read-write

HALTREQ : Halt request bit.
bits : 9 - 9 (1 bit)
access : read-write

EN : Main trace enable bit.
bits : 31 - 31 (1 bit)
access : read-write


FLOW

MTB Trace Flow Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLOW FLOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUTOSTOP AUTOHALT WATERMARK

AUTOSTOP : AUTOSTOP enable.
bits : 0 - 0 (1 bit)
access : read-write

AUTOHALT : AUTOHALT enable.
bits : 1 - 1 (1 bit)
access : read-write

WATERMARK : WATERMARK value.
bits : 3 - 31 (29 bit)
access : read-write


BASE

MTB Trace Base Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BASE BASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BASE

BASE : The ram base address.
bits : 0 - 31 (32 bit)
access : read-write



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