\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Analog Comparator Enable
bits : 0 - 0 (1 bit)
access : read-write
MUXEN : Input Mux Enable
bits : 1 - 1 (1 bit)
access : read-write
INACTVAL : Inactive Value
bits : 2 - 2 (1 bit)
access : read-write
GPIOINV : Comparator GPIO Output Invert
bits : 3 - 3 (1 bit)
access : read-write
HYSTSEL : Hysteresis Select
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x00000000 : HYST0
No hysteresis.
0x00000001 : HYST1
~15 mV hysteresis.
0x00000002 : HYST2
~22 mV hysteresis.
0x00000003 : HYST3
~29 mV hysteresis.
0x00000004 : HYST4
~36 mV hysteresis.
0x00000005 : HYST5
~43 mV hysteresis.
0x00000006 : HYST6
~50 mV hysteresis.
0x00000007 : HYST7
~57 mV hysteresis.
End of enumeration elements list.
WARMTIME : Warm-up Time
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00000000 : 4CYCLES
4 HFPERCLK cycles.
0x00000001 : 8CYCLES
8 HFPERCLK cycles.
0x00000002 : 16CYCLES
16 HFPERCLK cycles.
0x00000003 : 32CYCLES
32 HFPERCLK cycles.
0x00000004 : 64CYCLES
64 HFPERCLK cycles.
0x00000005 : 128CYCLES
128 HFPERCLK cycles.
0x00000006 : 256CYCLES
256 HFPERCLK cycles.
0x00000007 : 512CYCLES
512 HFPERCLK cycles.
End of enumeration elements list.
IRISE : Rising Edge Interrupt Sense
bits : 16 - 16 (1 bit)
access : read-write
IFALL : Falling Edge Interrupt Sense
bits : 17 - 17 (1 bit)
access : read-write
BIASPROG : Bias Configuration
bits : 24 - 27 (4 bit)
access : read-write
HALFBIAS : Half Bias Current
bits : 30 - 30 (1 bit)
access : read-write
FULLBIAS : Full Bias Current
bits : 31 - 31 (1 bit)
access : read-write
Interrupt Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EDGE : Edge Triggered Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
WARMUP : Warm-up Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EDGE : Edge Triggered Interrupt Flag Set
bits : 0 - 0 (1 bit)
access : write-only
WARMUP : Warm-up Interrupt Flag Set
bits : 1 - 1 (1 bit)
access : write-only
Interrupt Flag Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
EDGE : Edge Triggered Interrupt Flag Clear
bits : 0 - 0 (1 bit)
access : write-only
WARMUP : Warm-up Interrupt Flag Clear
bits : 1 - 1 (1 bit)
access : write-only
I/O Routing Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACMPPEN : ACMP Output Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
LOCATION : I/O Location
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00000000 : LOC0
Location 0
0x00000001 : LOC1
Location 1
0x00000002 : LOC2
Location 2
End of enumeration elements list.
Input Selection Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POSSEL : Positive Input Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x00000000 : CH0
Channel 0 as positive input.
0x00000001 : CH1
Channel 1 as positive input.
0x00000002 : CH2
Channel 2 as positive input.
0x00000003 : CH3
Channel 3 as positive input.
0x00000004 : CH4
Channel 4 as positive input.
0x00000005 : CH5
Channel 5 as positive input.
0x00000006 : CH6
Channel 6 as positive input.
0x00000007 : CH7
Channel 7 as positive input.
End of enumeration elements list.
NEGSEL : Negative Input Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0x00000000 : CH0
Channel 0 as negative input.
0x00000001 : CH1
Channel 1 as negative input.
0x00000002 : CH2
Channel 2 as negative input.
0x00000003 : CH3
Channel 3 as negative input.
0x00000004 : CH4
Channel 4 as negative input.
0x00000005 : CH5
Channel 5 as negative input.
0x00000006 : CH6
Channel 6 as negative input.
0x00000007 : CH7
Channel 7 as negative input.
0x00000008 : 1V25
1.25 V as negative input.
0x00000009 : 2V5
2.5 V as negative input.
0x0000000A : VDD
Scaled VDD as negative input.
0x0000000B : CAPSENSE
Capacitive sense mode.
0x0000000C : DAC0CH0
DAC0 channel 0.
0x0000000D : DAC0CH1
DAC0 channel 1.
End of enumeration elements list.
VDDLEVEL : VDD Reference Level
bits : 8 - 13 (6 bit)
access : read-write
LPREF : Low Power Reference Mode
bits : 16 - 16 (1 bit)
access : read-write
CSRESEN : Capacitive Sense Mode Internal Resistor Enable
bits : 24 - 24 (1 bit)
access : read-write
CSRESSEL : Capacitive Sense Mode Internal Resistor Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x00000000 : RES0
Internal capacitive sense resistor value 0.
0x00000001 : RES1
Internal capacitive sense resistor value 1.
0x00000002 : RES2
Internal capacitive sense resistor value 2.
0x00000003 : RES3
Internal capacitive sense resistor value 3.
End of enumeration elements list.
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACMPACT : Analog Comparator Active
bits : 0 - 0 (1 bit)
access : read-only
ACMPOUT : Analog Comparator Output
bits : 1 - 1 (1 bit)
access : read-only
Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGE : Edge Trigger Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
WARMUP : Warm-up Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
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