\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C000 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
System Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBUSENAP : VBUSEN Active Polarity
bits : 0 - 0 (1 bit)
access : read-write
DMPUAP : DMPU Active Polarity
bits : 1 - 1 (1 bit)
access : read-write
VREGDIS : Voltage Regulator Disable
bits : 16 - 16 (1 bit)
access : read-write
VREGOSEN : VREGO Sense Enable
bits : 17 - 17 (1 bit)
access : read-write
BIASPROGEM01 : Regulator Bias Programming Value in EM0/1
bits : 20 - 21 (2 bit)
access : read-write
BIASPROGEM23 : Regulator Bias Programming Value in EM2/3
bits : 24 - 25 (2 bit)
access : read-write
Interrupt Flag Clear Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VREGOSH : Clear VREGO Sense High Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
VREGOSL : Clear VREGO Sense Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREGOSH : VREGO Sense High Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
VREGOSL : VREGO Sense Low Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
I/O Routing Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYPEN : USB PHY Pin Enable
bits : 0 - 0 (1 bit)
access : read-write
VBUSENPEN : VBUSEN Pin Enable
bits : 1 - 1 (1 bit)
access : read-write
DMPUPEN : DMPU Pin Enable
bits : 2 - 2 (1 bit)
access : read-write
OTG Control and Status Register
address_offset : 0x3C000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SESREQSCS : Session Request Success device only
bits : 0 - 0 (1 bit)
access : read-only
SESREQ : Session Request device only
bits : 1 - 1 (1 bit)
access : read-write
VBVALIDOVEN : VBUS-Valid Override Enable
bits : 2 - 2 (1 bit)
access : read-write
VBVALIDOVVAL : VBUS Valid Override Value
bits : 3 - 3 (1 bit)
access : read-write
BVALIDOVEN : BValid Override Enable
bits : 4 - 4 (1 bit)
access : read-write
BVALIDOVVAL : Bvalid Override Value
bits : 5 - 5 (1 bit)
access : read-write
AVALIDOVEN : AValid Override Enable
bits : 6 - 6 (1 bit)
access : read-write
AVALIDOVVAL : Avalid Override Value
bits : 7 - 7 (1 bit)
access : read-write
HSTNEGSCS : Host Negotiation Success device only
bits : 8 - 8 (1 bit)
access : read-only
HNPREQ : HNP Request device only
bits : 9 - 9 (1 bit)
access : read-write
HSTSETHNPEN : Host Set HNP Enable host only
bits : 10 - 10 (1 bit)
access : read-write
DEVHNPEN : Device HNP Enabled device only
bits : 11 - 11 (1 bit)
access : read-write
CONIDSTS : Connector ID Status host and device
bits : 16 - 16 (1 bit)
access : read-only
DBNCTIME : Long/Short Debounce Time host only
bits : 17 - 17 (1 bit)
access : read-only
ASESVLD : A-Session Valid host only
bits : 18 - 18 (1 bit)
access : read-only
BSESVLD : B-Session Valid device only
bits : 19 - 19 (1 bit)
access : read-only
OTGVER : OTG Version
bits : 20 - 20 (1 bit)
access : read-write
OTG Interrupt Register
address_offset : 0x3C004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SESENDDET : Session End Detected host and device
bits : 2 - 2 (1 bit)
access : read-write
SESREQSUCSTSCHNG : Session Request Success Status Change host and device
bits : 8 - 8 (1 bit)
access : read-write
HSTNEGSUCSTSCHNG : Host Negotiation Success Status Change host and device
bits : 9 - 9 (1 bit)
access : read-write
HSTNEGDET : Host Negotiation Detected host and device
bits : 17 - 17 (1 bit)
access : read-write
ADEVTOUTCHG : A-Device Timeout Change host and device
bits : 18 - 18 (1 bit)
access : read-write
DBNCEDONE : Debounce Done host only
bits : 19 - 19 (1 bit)
access : read-write
AHB Configuration Register
address_offset : 0x3C008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GLBLINTRMSK : Global Interrupt Mask host and device
bits : 0 - 0 (1 bit)
access : read-write
HBSTLEN : Burst Length/Type host and device
bits : 1 - 4 (4 bit)
access : read-write
Enumeration:
0x00000000 : SINGLE
Single transfer.
0x00000001 : INCR
Incrementing burst of unspecified length.
0x00000003 : INCR4
4-beat incrementing burst.
0x00000005 : INCR8
8-beat incrementing burst.
0x00000007 : INCR16
16-beat incrementing burst.
End of enumeration elements list.
DMAEN : DMA Enable host and device
bits : 5 - 5 (1 bit)
access : read-write
NPTXFEMPLVL : Non-Periodic TxFIFO Empty Level host and device
bits : 7 - 7 (1 bit)
access : read-write
PTXFEMPLVL : Periodic TxFIFO Empty Level host only
bits : 8 - 8 (1 bit)
access : read-write
REMMEMSUPP : Remote Memory Support
bits : 21 - 21 (1 bit)
access : read-write
NOTIALLDMAWRIT : Notify All DMA Writes
bits : 22 - 22 (1 bit)
access : read-write
USB Configuration Register
address_offset : 0x3C00C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTCAL : Timeout Calibration host and device
bits : 0 - 2 (3 bit)
access : read-write
FSINTF : Full-Speed Serial Interface Select host and device
bits : 5 - 5 (1 bit)
access : read-write
SRPCAP : SRP-Capable host and device
bits : 8 - 8 (1 bit)
access : read-write
HNPCAP : HNP-Capable host and device
bits : 9 - 9 (1 bit)
access : read-write
USBTRDTIM : USB Turnaround Time device only
bits : 10 - 13 (4 bit)
access : read-write
TERMSELDLPULSE : TermSel DLine Pulsing Selection device only
bits : 22 - 22 (1 bit)
access : read-write
TXENDDELAY : Tx End Delay device only
bits : 28 - 28 (1 bit)
access : read-write
FORCEHSTMODE : Force Host Mode host and device
bits : 29 - 29 (1 bit)
access : read-write
FORCEDEVMODE : Force Device Mode host and device
bits : 30 - 30 (1 bit)
access : read-write
CORRUPTTXPKT : Corrupt Tx packet host and device
bits : 31 - 31 (1 bit)
access : write-only
Reset Register
address_offset : 0x3C010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSFTRST : Core Soft Reset host and device
bits : 0 - 0 (1 bit)
access : read-write
FRMCNTRRST : Host Frame Counter Reset host only
bits : 2 - 2 (1 bit)
access : read-write
RXFFLSH : RxFIFO Flush host and device
bits : 4 - 4 (1 bit)
access : read-write
TXFFLSH : TxFIFO Flush host and device
bits : 5 - 5 (1 bit)
access : read-write
TXFNUM : TxFIFO Number host and device
bits : 6 - 10 (5 bit)
access : read-write
Enumeration:
0x00000000 : F0
Host mode: Non-periodic TxFIFO flush. Device: Tx FIFO 0 flush
0x00000001 : F1
Host mode: Periodic TxFIFO flush. Device: TXFIFO 1 flush.
0x00000002 : F2
Device mode: TXFIFO 2 flush.
0x00000003 : F3
Device mode: TXFIFO 3 flush.
0x00000004 : F4
Device mode: TXFIFO 4 flush.
0x00000005 : F5
Device mode: TXFIFO 5 flush.
0x00000006 : F6
Device mode: TXFIFO 6 flush.
0x00000010 : FALL
Flush all the transmit FIFOs in device or host mode.
End of enumeration elements list.
DMAREQ : DMA Request Signal host and device
bits : 30 - 30 (1 bit)
access : read-only
AHBIDLE : AHB Master Idle host and device
bits : 31 - 31 (1 bit)
access : read-only
Interrupt Register
address_offset : 0x3C014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURMOD : Current Mode of Operation host and device
bits : 0 - 0 (1 bit)
access : read-only
MODEMIS : Mode Mismatch Interrupt host and device
bits : 1 - 1 (1 bit)
access : read-write
OTGINT : OTG Interrupt host and device
bits : 2 - 2 (1 bit)
access : read-only
SOF : Start of Frame host and device
bits : 3 - 3 (1 bit)
access : read-write
RXFLVL : RxFIFO Non-Empty host and device
bits : 4 - 4 (1 bit)
access : read-only
NPTXFEMP : Non-Periodic TxFIFO Empty host only
bits : 5 - 5 (1 bit)
access : read-only
GINNAKEFF : Global IN Non-periodic NAK Effective device only
bits : 6 - 6 (1 bit)
access : read-only
GOUTNAKEFF : Global OUT NAK Effective device only
bits : 7 - 7 (1 bit)
access : read-only
ERLYSUSP : Early Suspend device only
bits : 10 - 10 (1 bit)
access : read-write
USBSUSP : USB Suspend device only
bits : 11 - 11 (1 bit)
access : read-write
USBRST : USB Reset device only
bits : 12 - 12 (1 bit)
access : read-write
ENUMDONE : Enumeration Done device only
bits : 13 - 13 (1 bit)
access : read-write
ISOOUTDROP : Isochronous OUT Packet Dropped Interrupt device only
bits : 14 - 14 (1 bit)
access : read-write
EOPF : End of Periodic Frame Interrupt
bits : 15 - 15 (1 bit)
access : read-write
IEPINT : IN Endpoints Interrupt device only
bits : 18 - 18 (1 bit)
access : read-only
OEPINT : OUT Endpoints Interrupt device only
bits : 19 - 19 (1 bit)
access : read-only
INCOMPISOIN : Incomplete Isochronous IN Transfer device only
bits : 20 - 20 (1 bit)
access : read-write
INCOMPLP : Incomplete Periodic Transfer host and device
bits : 21 - 21 (1 bit)
access : read-write
FETSUSP : Data Fetch Suspended device only
bits : 22 - 22 (1 bit)
access : read-write
RESETDET : Reset detected Interrupt device only
bits : 23 - 23 (1 bit)
access : read-write
PRTINT : Host Port Interrupt host only
bits : 24 - 24 (1 bit)
access : read-only
HCHINT : Host Channels Interrupt host only
bits : 25 - 25 (1 bit)
access : read-only
PTXFEMP : Periodic TxFIFO Empty host only
bits : 26 - 26 (1 bit)
access : read-only
CONIDSTSCHNG : Connector ID Status Change host and device
bits : 28 - 28 (1 bit)
access : read-write
DISCONNINT : Disconnect Detected Interrupt host only
bits : 29 - 29 (1 bit)
access : read-write
SESSREQINT : Session Request/New Session Detected Interrupt host and device
bits : 30 - 30 (1 bit)
access : read-write
WKUPINT : Resume/Remote Wakeup Detected Interrupt host and device
bits : 31 - 31 (1 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x3C018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODEMISMSK : Mode Mismatch Interrupt Mask host and device
bits : 1 - 1 (1 bit)
access : read-write
OTGINTMSK : OTG Interrupt Mask host and device
bits : 2 - 2 (1 bit)
access : read-write
SOFMSK : Start of Frame Mask host and device
bits : 3 - 3 (1 bit)
access : read-write
RXFLVLMSK : Receive FIFO Non-Empty Mask host and device
bits : 4 - 4 (1 bit)
access : read-write
NPTXFEMPMSK : Non-Periodic TxFIFO Empty Mask host only
bits : 5 - 5 (1 bit)
access : read-write
GINNAKEFFMSK : Global Non-periodic IN NAK Effective Mask device only
bits : 6 - 6 (1 bit)
access : read-write
GOUTNAKEFFMSK : Global OUT NAK Effective Mask device only
bits : 7 - 7 (1 bit)
access : read-write
ERLYSUSPMSK : Early Suspend Mask device only
bits : 10 - 10 (1 bit)
access : read-write
USBSUSPMSK : USB Suspend Mask device only
bits : 11 - 11 (1 bit)
access : read-write
USBRSTMSK : USB Reset Mask device only
bits : 12 - 12 (1 bit)
access : read-write
ENUMDONEMSK : Enumeration Done Mask device only
bits : 13 - 13 (1 bit)
access : read-write
ISOOUTDROPMSK : Isochronous OUT Packet Dropped Interrupt Mask device only
bits : 14 - 14 (1 bit)
access : read-write
EOPFMSK : End of Periodic Frame Interrupt Mask device only
bits : 15 - 15 (1 bit)
access : read-write
IEPINTMSK : IN Endpoints Interrupt Mask device only
bits : 18 - 18 (1 bit)
access : read-write
OEPINTMSK : OUT Endpoints Interrupt Mask device only
bits : 19 - 19 (1 bit)
access : read-write
INCOMPISOINMSK : Incomplete Isochronous IN Transfer Mask device only
bits : 20 - 20 (1 bit)
access : read-write
INCOMPLPMSK : Incomplete Periodic Transfer Mask host and device
bits : 21 - 21 (1 bit)
access : read-write
FETSUSPMSK : Data Fetch Suspended Mask device only
bits : 22 - 22 (1 bit)
access : read-write
RESETDETMSK : Reset detected Interrupt Mask device only
bits : 23 - 23 (1 bit)
access : read-write
PRTINTMSK : Host Port Interrupt Mask host only
bits : 24 - 24 (1 bit)
access : read-write
HCHINTMSK : Host Channels Interrupt Mask host only
bits : 25 - 25 (1 bit)
access : read-write
PTXFEMPMSK : Periodic TxFIFO Empty Mask host only
bits : 26 - 26 (1 bit)
access : read-write
CONIDSTSCHNGMSK : Connector ID Status Change Mask host and device
bits : 28 - 28 (1 bit)
access : read-write
DISCONNINTMSK : Disconnect Detected Interrupt Mask host and device
bits : 29 - 29 (1 bit)
access : read-write
SESSREQINTMSK : Session Request/New Session Detected Interrupt Mask host and device
bits : 30 - 30 (1 bit)
access : read-write
WKUPINTMSK : Resume/Remote Wakeup Detected Interrupt Mask host and device
bits : 31 - 31 (1 bit)
access : read-write
Receive Status Debug Read Register
address_offset : 0x3C01C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHEPNUM : Channel Number host only / Endpoint Number device only
bits : 0 - 3 (4 bit)
access : read-only
BCNT : Byte Count (host or device)
bits : 4 - 14 (11 bit)
access : read-only
DPID : Data PID (host or device)
bits : 15 - 16 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA1
DATA1 PID.
0x00000002 : DATA2
DATA2 PID.
0x00000003 : MDATA
MDATA PID.
End of enumeration elements list.
PKTSTS : Packet Status (host or device)
bits : 17 - 20 (4 bit)
access : read-only
Enumeration:
0x00000001 : GOUTNAK
Device mode: Global OUT NAK (triggers an interrupt).
0x00000002 : PKTRCV
Host mode: IN data packet received. Device mode: OUT data packet received.
0x00000003 : XFERCOMPL
Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).
0x00000004 : SETUPCOMPL
Device mode: SETUP transaction completed (triggers an interrupt).
0x00000005 : TGLERR
Host mode: Data toggle error (triggers an interrupt).
0x00000006 : SETUPRCV
Device mode: SETUP data packet received.
0x00000007 : CHLT
Host mode: Channel halted (triggers an interrupt).
End of enumeration elements list.
FN : Frame Number device only
bits : 21 - 24 (4 bit)
access : read-only
Receive Status Read and Pop Register
address_offset : 0x3C020 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHEPNUM : Channel Number host only / Endpoint Number device only
bits : 0 - 3 (4 bit)
access : read-only
BCNT : Byte Count (host or device)
bits : 4 - 14 (11 bit)
access : read-only
DPID : Data PID (host or device)
bits : 15 - 16 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA1
DATA1 PID.
0x00000002 : DATA2
DATA2 PID.
0x00000003 : MDATA
MDATA PID.
End of enumeration elements list.
PKTSTS : Packet Status (host or device)
bits : 17 - 20 (4 bit)
access : read-only
Enumeration:
0x00000001 : GOUTNAK
Device mode: Global OUT NAK (triggers an interrupt).
0x00000002 : PKTRCV
Host mode: IN data packet received. Device mode: OUT data packet received.
0x00000003 : XFERCOMPL
Host mode: IN transfer completed (triggers an interrupt). Device mode: OUT transfer completed (triggers an interrupt).
0x00000004 : SETUPCOMPL
Device mode: SETUP transaction completed (triggers an interrupt).
0x00000005 : TGLERR
Host mode: Data toggle error (triggers an interrupt).
0x00000006 : SETUPRCV
Device mode: SETUP data packet received.
0x00000007 : CHLT
Host mode: Channel halted (triggers an interrupt).
End of enumeration elements list.
FN : Frame Number device only
bits : 21 - 24 (4 bit)
access : read-only
Receive FIFO Size Register
address_offset : 0x3C024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFDEP : RxFIFO Depth
bits : 0 - 9 (10 bit)
access : read-write
Non-periodic Transmit FIFO Size Register
address_offset : 0x3C028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NPTXFSTADDR : Non-periodic Transmit RAM Start Address host only
bits : 0 - 9 (10 bit)
access : read-write
NPTXFINEPTXF0DEP : Non-periodic TxFIFO Depth host only / IN Endpoint TxFIFO 0 Depth device only
bits : 16 - 31 (16 bit)
access : read-write
Non-periodic Transmit FIFO/Queue Status Register
address_offset : 0x3C02C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NPTXFSPCAVAIL : Non-periodic TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
NPTXQSPCAVAIL : Non-periodic Transmit Request Queue Space Available
bits : 16 - 23 (8 bit)
access : read-only
NPTXQTOP : Top of the Non-periodic Transmit Request Queue
bits : 24 - 30 (7 bit)
access : read-only
Global DFIFO Configuration Register
address_offset : 0x3C05C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GDFIFOCFG : DFIFO Config
bits : 0 - 15 (16 bit)
access : read-write
EPINFOBASEADDR : Endpoint Info Base Address
bits : 16 - 31 (16 bit)
access : read-write
Host Periodic Transmit FIFO Size Register
address_offset : 0x3C100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTXFSTADDR : Host Periodic TxFIFO Start Address
bits : 0 - 10 (11 bit)
access : read-write
PTXFSIZE : Host Periodic TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Device IN Endpoint Transmit FIFO 1 Size Register
address_offset : 0x3C104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPNTXFSTADDR : IN Endpoint FIFO 1 Transmit RAM Start Address
bits : 0 - 10 (11 bit)
access : read-write
INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Device IN Endpoint Transmit FIFO 2 Size Register
address_offset : 0x3C108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPNTXFSTADDR : IN Endpoint FIFO 2 Transmit RAM Start Address
bits : 0 - 10 (11 bit)
access : read-write
INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Device IN Endpoint Transmit FIFO 3 Size Register
address_offset : 0x3C10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPNTXFSTADDR : IN Endpoint FIFO 3 Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write
INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Device IN Endpoint Transmit FIFO 4 Size Register
address_offset : 0x3C110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPNTXFSTADDR : IN Endpoint FIFO 4 Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write
INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Device IN Endpoint Transmit FIFO 5 Size Register
address_offset : 0x3C114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPNTXFSTADDR : IN Endpoint FIFO 5 Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write
INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Device IN Endpoint Transmit FIFO 6 Size Register
address_offset : 0x3C118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPNTXFSTADDR : IN Endpoint FIFO 6 Transmit RAM Start Address
bits : 0 - 11 (12 bit)
access : read-write
INEPNTXFDEP : IN Endpoint TxFIFO Depth
bits : 16 - 25 (10 bit)
access : read-write
Host Configuration Register
address_offset : 0x3C400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSLSPCLKSEL : FS/LS PHY Clock Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000001 : DIV1
Internal PHY clock is running at 48 MHz (undivided).
0x00000002 : DIV8
Internal PHY clock is running at 6 MHz (48 MHz divided by 8).
End of enumeration elements list.
FSLSSUPP : FS- and LS-Only Support
bits : 2 - 2 (1 bit)
access : read-write
ENA32KHZS : Enable 32 KHz Suspend mode
bits : 7 - 7 (1 bit)
access : read-write
RESVALID : Resume Validation Period
bits : 8 - 15 (8 bit)
access : read-write
MODECHTIMEN : Mode Change Time
bits : 31 - 31 (1 bit)
access : read-write
Host Frame Interval Register
address_offset : 0x3C404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRINT : Frame Interval
bits : 0 - 15 (16 bit)
access : read-write
HFIRRLDCTRL : Reload Control
bits : 16 - 16 (1 bit)
access : read-write
Host Frame Number/Frame Time Remaining Register
address_offset : 0x3C408 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRNUM : Frame Number
bits : 0 - 15 (16 bit)
access : read-only
FRREM : Frame Time Remaining
bits : 16 - 31 (16 bit)
access : read-only
Host Periodic Transmit FIFO/Queue Status Register
address_offset : 0x3C410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PTXFSPCAVAIL : Periodic Transmit Data FIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
PTXQSPCAVAIL : Periodic Transmit Request Queue Space Available
bits : 16 - 23 (8 bit)
access : read-only
PTXQTOP : Top of the Periodic Transmit Request Queue
bits : 24 - 31 (8 bit)
access : read-only
Host All Channels Interrupt Register
address_offset : 0x3C414 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HAINT : Channel Interrupt for channel 0 - 13.
bits : 0 - 13 (14 bit)
access : read-only
Host All Channels Interrupt Mask Register
address_offset : 0x3C418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HAINTMSK : Channel Interrupt Mask for channel 0 - 13
bits : 0 - 13 (14 bit)
access : read-write
Host Port Control and Status Register
address_offset : 0x3C440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRTCONNSTS : Port Connect Status
bits : 0 - 0 (1 bit)
access : read-only
PRTCONNDET : Port Connect Detected
bits : 1 - 1 (1 bit)
access : read-write
PRTENA : Port Enable
bits : 2 - 2 (1 bit)
access : read-write
PRTENCHNG : Port Enable/Disable Change
bits : 3 - 3 (1 bit)
access : read-write
PRTOVRCURRACT : Port Overcurrent Active
bits : 4 - 4 (1 bit)
access : read-only
PRTOVRCURRCHNG : Port Overcurrent Change
bits : 5 - 5 (1 bit)
access : read-write
PRTRES : Port Resume
bits : 6 - 6 (1 bit)
access : read-write
PRTSUSP : Port Suspend
bits : 7 - 7 (1 bit)
access : read-write
PRTRST : Port Reset
bits : 8 - 8 (1 bit)
access : read-write
PRTLNSTS : Port Line Status
bits : 10 - 11 (2 bit)
access : read-only
PRTPWR : Port Power
bits : 12 - 12 (1 bit)
access : read-write
PRTTSTCTL : Port Test Control
bits : 13 - 16 (4 bit)
access : read-write
Enumeration:
0x00000000 : DISABLE
Test mode disabled.
0x00000001 : J
Test_J mode.
0x00000002 : K
Test_K mode.
0x00000003 : SE0NAK
Test_SE0_NAK mode.
0x00000004 : PACKET
Test_Packet mode.
0x00000005 : FORCE
Test_Force_Enable.
End of enumeration elements list.
PRTSPD : Port Speed
bits : 17 - 18 (2 bit)
access : read-only
Enumeration:
0x00000000 : HS
High speed.
0x00000001 : FS
Full speed.
0x00000002 : LS
Low speed.
End of enumeration elements list.
Host Channel x Characteristics Register
address_offset : 0x3C500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C548 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C54C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C550 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C554 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C560 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C568 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C56C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C570 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C580 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C588 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C58C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C594 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C5A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C5A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C5AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C5B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C5B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C5C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C5C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C5CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C5D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C5D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C5E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C5EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C5F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C5F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C610 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C614 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C620 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C62C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C630 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C640 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C648 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C64C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C668 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C66C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C670 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C674 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C694 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Host Channel x Characteristics Register
address_offset : 0x3C6A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
EPNUM : Endpoint Number
bits : 11 - 14 (4 bit)
access : read-write
EPDIR : Endpoint Direction
bits : 15 - 15 (1 bit)
access : read-write
LSPDDEV : Low-Speed Device
bits : 17 - 17 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control endpoint.
0x00000001 : ISO
Isochronous endpoint.
0x00000002 : BULK
Bulk endpoint.
0x00000003 : INT
Interrupt endpoint.
End of enumeration elements list.
MC : Multi Count
bits : 20 - 21 (2 bit)
access : read-write
DEVADDR : Device Address
bits : 22 - 28 (7 bit)
access : read-write
ODDFRM : Odd Frame
bits : 29 - 29 (1 bit)
access : read-write
CHDIS : Channel Disable
bits : 30 - 30 (1 bit)
access : read-write
CHENA : Channel Enable
bits : 31 - 31 (1 bit)
access : read-write
Host Channel x Interrupt Register
address_offset : 0x3C6A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed
bits : 0 - 0 (1 bit)
access : read-write
CHHLTD : Channel Halted
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
STALL : STALL Response Received Interrupt
bits : 3 - 3 (1 bit)
access : read-write
NAK : NAK Response Received Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 5 (1 bit)
access : read-write
XACTERR : Transaction Error
bits : 7 - 7 (1 bit)
access : read-write
BBLERR : Babble Error
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUN : Frame Overrun
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERR : Data Toggle Error
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Interrupt Mask Register
address_offset : 0x3C6AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Mask
bits : 0 - 0 (1 bit)
access : read-write
CHHLTDMSK : Channel Halted Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
STALLMSK : STALL Response Received Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-write
NAKMSK : NAK Response Received Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-write
ACKMSK : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-write
XACTERRMSK : Transaction Error Mask
bits : 7 - 7 (1 bit)
access : read-write
BBLERRMSK : Babble Error Mask
bits : 8 - 8 (1 bit)
access : read-write
FRMOVRUNMSK : Frame Overrun Mask
bits : 9 - 9 (1 bit)
access : read-write
DATATGLERRMSK : Data Toggle Error Mask
bits : 10 - 10 (1 bit)
access : read-write
Host Channel x Transfer Size Register
address_offset : 0x3C6B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
PID : Packet ID
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID.
0x00000002 : DATA1
DATA1 PID.
0x00000003 : MDATA
MDATA (non-control) / SETUP (control) PID.
End of enumeration elements list.
Host Channel x DMA Address Register
address_offset : 0x3C6B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device Configuration Register
address_offset : 0x3C800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVSPD : Device Speed
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000002 : LS
Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.
0x00000003 : FS
Full speed (PHY clock is 48 MHz).
End of enumeration elements list.
NZSTSOUTHSHK : Non-Zero-Length Status OUT Handshake
bits : 2 - 2 (1 bit)
access : read-write
ENA32KHZSUSP : Enable 32 KHz Suspend mode
bits : 3 - 3 (1 bit)
access : read-write
DEVADDR : Device Address
bits : 4 - 10 (7 bit)
access : read-write
PERFRINT : Periodic Frame Interval
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x00000000 : 80PCNT
80% of the frame interval.
0x00000001 : 85PCNT
85% of the frame interval.
0x00000002 : 90PCNT
90% of the frame interval.
0x00000003 : 95PCNT
95% of the frame interval.
End of enumeration elements list.
RESVALID : Resume Validation Period
bits : 26 - 31 (6 bit)
access : read-write
Device Control Register
address_offset : 0x3C804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMTWKUPSIG : Remote Wakeup Signaling
bits : 0 - 0 (1 bit)
access : read-write
SFTDISCON : Soft Disconnect
bits : 1 - 1 (1 bit)
access : read-write
GNPINNAKSTS : Global Non-periodic IN NAK Status
bits : 2 - 2 (1 bit)
access : read-only
GOUTNAKSTS : Global OUT NAK Status
bits : 3 - 3 (1 bit)
access : read-only
TSTCTL : Test Control
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x00000000 : DISABLE
Test mode disabled.
0x00000001 : J
Test_J mode.
0x00000002 : K
Test_K mode.
0x00000003 : SE0NAK
Test_SE0_NAK mode.
0x00000004 : PACKET
Test_Packet mode.
0x00000005 : FORCE
Test_Force_Enable.
End of enumeration elements list.
SGNPINNAK : Set Global Non-periodic IN NAK
bits : 7 - 7 (1 bit)
access : write-only
CGNPINNAK : Clear Global Non-periodic IN NAK
bits : 8 - 8 (1 bit)
access : write-only
SGOUTNAK : Set Global OUT NAK
bits : 9 - 9 (1 bit)
access : write-only
CGOUTNAK : Clear Global OUT NAK
bits : 10 - 10 (1 bit)
access : write-only
PWRONPRGDONE : Power-On Programming Done
bits : 11 - 11 (1 bit)
access : read-write
IGNRFRMNUM : Ignore Frame number For Isochronous End points
bits : 15 - 15 (1 bit)
access : read-write
NAKONBBLE : NAK on Babble Error
bits : 16 - 16 (1 bit)
access : read-write
Device Status Register
address_offset : 0x3C808 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPSTS : Suspend Status
bits : 0 - 0 (1 bit)
access : read-only
ENUMSPD : Enumerated Speed
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
0x00000002 : LS
Low speed (PHY clock is running at 6 MHz).
0x00000003 : FS
Full speed (PHY clock is running at 48 MHz).
End of enumeration elements list.
ERRTICERR : Erratic Error
bits : 3 - 3 (1 bit)
access : read-only
SOFFN : Frame Number of the Received SOF
bits : 8 - 21 (14 bit)
access : read-only
Device IN Endpoint Common Interrupt Mask Register
address_offset : 0x3C810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLDMSK : Endpoint Disabled Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error Mask
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUTMSK : Timeout Condition Mask
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMPMSK : IN Token Received When TxFIFO Empty Mask
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFFMSK : IN Endpoint NAK Effective Mask
bits : 6 - 6 (1 bit)
access : read-write
TXFIFOUNDRNMSK : Fifo Underrun Mask
bits : 8 - 8 (1 bit)
access : read-write
NAKMSK : NAK interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint Common Interrupt Mask Register
address_offset : 0x3C814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPLMSK : Transfer Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLDMSK : Endpoint Disabled Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-write
AHBERRMSK : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUPMSK : SETUP Phase Done Mask
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDISMSK : OUT Token Received when Endpoint Disabled Mask
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received Mask
bits : 6 - 6 (1 bit)
access : read-write
OUTPKTERRMSK : OUT Packet Error Mask
bits : 8 - 8 (1 bit)
access : read-write
BBLEERRMSK : Babble Error interrupt Mask
bits : 12 - 12 (1 bit)
access : read-write
NAKMSK : NAK interrupt Mask
bits : 13 - 13 (1 bit)
access : read-write
Device All Endpoints Interrupt Register
address_offset : 0x3C818 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INEPINT0 : IN Endpoint 0 Interrupt Bit
bits : 0 - 0 (1 bit)
access : read-only
INEPINT1 : IN Endpoint 1 Interrupt Bit
bits : 1 - 1 (1 bit)
access : read-only
INEPINT2 : IN Endpoint 2 Interrupt Bit
bits : 2 - 2 (1 bit)
access : read-only
INEPINT3 : IN Endpoint 3 Interrupt Bit
bits : 3 - 3 (1 bit)
access : read-only
INEPINT4 : IN Endpoint 4 Interrupt Bit
bits : 4 - 4 (1 bit)
access : read-only
INEPINT5 : IN Endpoint 5 Interrupt Bit
bits : 5 - 5 (1 bit)
access : read-only
INEPINT6 : IN Endpoint 6 Interrupt Bit
bits : 6 - 6 (1 bit)
access : read-only
OUTEPINT0 : OUT Endpoint 0 Interrupt Bit
bits : 16 - 16 (1 bit)
access : read-only
OUTEPINT1 : OUT Endpoint 1 Interrupt Bit
bits : 17 - 17 (1 bit)
access : read-only
OUTEPINT2 : OUT Endpoint 2 Interrupt Bit
bits : 18 - 18 (1 bit)
access : read-only
OUTEPINT3 : OUT Endpoint 3 Interrupt Bit
bits : 19 - 19 (1 bit)
access : read-only
OUTEPINT4 : OUT Endpoint 4 Interrupt Bit
bits : 20 - 20 (1 bit)
access : read-only
OUTEPINT5 : OUT Endpoint 5 Interrupt Bit
bits : 21 - 21 (1 bit)
access : read-only
OUTEPINT6 : OUT Endpoint 6 Interrupt Bit
bits : 22 - 22 (1 bit)
access : read-only
Device All Endpoints Interrupt Mask Register
address_offset : 0x3C81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPMSK0 : IN Endpoint 0 Interrupt mask Bit
bits : 0 - 0 (1 bit)
access : read-write
INEPMSK1 : IN Endpoint 1 Interrupt mask Bit
bits : 1 - 1 (1 bit)
access : read-write
INEPMSK2 : IN Endpoint 2 Interrupt mask Bit
bits : 2 - 2 (1 bit)
access : read-write
INEPMSK3 : IN Endpoint 3 Interrupt mask Bit
bits : 3 - 3 (1 bit)
access : read-write
INEPMSK4 : IN Endpoint 4 Interrupt mask Bit
bits : 4 - 4 (1 bit)
access : read-write
INEPMSK5 : IN Endpoint 5 Interrupt mask Bit
bits : 5 - 5 (1 bit)
access : read-write
INEPMSK6 : IN Endpoint 6 Interrupt mask Bit
bits : 6 - 6 (1 bit)
access : read-write
OUTEPMSK0 : OUT Endpoint 0 Interrupt mask Bit
bits : 16 - 16 (1 bit)
access : read-write
OUTEPMSK1 : OUT Endpoint 1 Interrupt mask Bit
bits : 17 - 17 (1 bit)
access : read-write
OUTEPMSK2 : OUT Endpoint 2 Interrupt mask Bit
bits : 18 - 18 (1 bit)
access : read-write
OUTEPMSK3 : OUT Endpoint 3 Interrupt mask Bit
bits : 19 - 19 (1 bit)
access : read-write
OUTEPMSK4 : OUT Endpoint 4 Interrupt mask Bit
bits : 20 - 20 (1 bit)
access : read-write
OUTEPMSK5 : OUT Endpoint 5 Interrupt mask Bit
bits : 21 - 21 (1 bit)
access : read-write
OUTEPMSK6 : OUT Endpoint 6 Interrupt mask Bit
bits : 22 - 22 (1 bit)
access : read-write
Device VBUS Discharge Time Register
address_offset : 0x3C828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVBUSDIS : Device VBUS Discharge Time
bits : 0 - 15 (16 bit)
access : read-write
Device VBUS Pulsing Time Register
address_offset : 0x3C82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVBUSPULSE : Device VBUS Pulsing Time
bits : 0 - 11 (12 bit)
access : read-write
Device IN Endpoint FIFO Empty Interrupt Mask Register
address_offset : 0x3C834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIEPEMPMSK : IN EP Tx FIFO Empty Interrupt Mask Bits
bits : 0 - 15 (16 bit)
access : read-write
Device IN Endpoint 0 Control Register
address_offset : 0x3C900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x00000000 : 64B
64 bytes.
0x00000001 : 32B
32 bytes.
0x00000002 : 16B
16 bytes.
0x00000003 : 8B
8 bytes.
End of enumeration elements list.
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint 0 Interrupt Register
address_offset : 0x3C908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint 0 Transfer Size Register
address_offset : 0x3C910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 6 (7 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 20 (2 bit)
access : read-write
Device IN Endpoint 0 DMA Address Register
address_offset : 0x3C914 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIEP0DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint 0 Transmit FIFO Status Register
address_offset : 0x3C918 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device IN Endpoint x+1 Control Register
address_offset : 0x3C920 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C930 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write
Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C934 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C938 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device IN Endpoint x+1 Control Register
address_offset : 0x3C940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C948 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C950 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write
Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C954 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C958 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device IN Endpoint x+1 Control Register
address_offset : 0x3C960 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C968 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C970 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write
Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C974 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C978 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device IN Endpoint x+1 Control Register
address_offset : 0x3C980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C988 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write
Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C994 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C998 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device IN Endpoint x+1 Control Register
address_offset : 0x3C9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C9A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C9B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write
Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C9B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C9B8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device IN Endpoint x+1 Control Register
address_offset : 0x3C9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even or Odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
TXFNUM : TxFIFO Number
bits : 22 - 25 (4 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device IN Endpoint x+1 Interrupt Register
address_offset : 0x3C9C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Timeout Condition
bits : 3 - 3 (1 bit)
access : read-write
INTKNTXFEMP : IN Token Received When TxFIFO is Empty
bits : 4 - 4 (1 bit)
access : read-write
INEPNAKEFF : IN Endpoint NAK Effective
bits : 6 - 6 (1 bit)
access : read-write
TXFEMP : Transmit FIFO Empty
bits : 7 - 7 (1 bit)
access : read-only
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device IN Endpoint x+1 Transfer Size Register
address_offset : 0x3C9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
MC : Multi Count
bits : 29 - 30 (2 bit)
access : read-write
Device IN Endpoint x+1 DMA Address Register
address_offset : 0x3C9D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device IN Endpoint x+1 Transmit FIFO Status Register
address_offset : 0x3C9D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPCAVAIL : TxFIFO Space Available
bits : 0 - 15 (16 bit)
access : read-only
Device OUT Endpoint 0 Control Register
address_offset : 0x3CB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0x00000000 : 64B
64 bytes.
0x00000001 : 32B
32 bytes.
0x00000002 : 16B
16 bytes.
0x00000003 : 8B
8 bytes.
End of enumeration elements list.
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-only
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-only
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint 0 Interrupt Register
address_offset : 0x3CB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : NAK Interrupt
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint 0 Transfer Size Register
address_offset : 0x3CB10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 6 (7 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 19 (1 bit)
access : read-write
SUPCNT : SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-write
Device OUT Endpoint 0 DMA Address Register
address_offset : 0x3CB14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOEP0DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID / 1 Packet.
0x00000002 : DATA1
DATA1 PID / 2 Packets.
0x00000003 : MDATA
MDATA PID / 3 Packets.
End of enumeration elements list.
Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID / 1 Packet.
0x00000002 : DATA1
DATA1 PID / 2 Packets.
0x00000003 : MDATA
MDATA PID / 3 Packets.
End of enumeration elements list.
Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID / 1 Packet.
0x00000002 : DATA1
DATA1 PID / 2 Packets.
0x00000003 : MDATA
MDATA PID / 3 Packets.
End of enumeration elements list.
Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device OUT Endpoint x+1 Control Register
address_offset : 0x3CB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CB88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CB90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID / 1 Packet.
0x00000002 : DATA1
DATA1 PID / 2 Packets.
0x00000003 : MDATA
MDATA PID / 3 Packets.
End of enumeration elements list.
Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CB94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device OUT Endpoint x+1 Control Register
address_offset : 0x3CBA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CBA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CBB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID / 1 Packet.
0x00000002 : DATA1
DATA1 PID / 2 Packets.
0x00000003 : MDATA
MDATA PID / 3 Packets.
End of enumeration elements list.
Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CBB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Device OUT Endpoint x+1 Control Register
address_offset : 0x3CBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPS : Maximum Packet Size
bits : 0 - 10 (11 bit)
access : read-write
USBACTEP : USB Active Endpoint
bits : 15 - 15 (1 bit)
access : read-write
DPIDEOF : Endpoint Data PID / Even-odd Frame
bits : 16 - 16 (1 bit)
access : read-only
NAKSTS : NAK Status
bits : 17 - 17 (1 bit)
access : read-only
EPTYPE : Endpoint Type
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x00000000 : CONTROL
Control Endpoint.
0x00000001 : ISO
Isochronous Endpoint.
0x00000002 : BULK
Bulk Endpoint.
0x00000003 : INT
Interrupt Endpoint.
End of enumeration elements list.
SNP : Snoop Mode
bits : 20 - 20 (1 bit)
access : read-write
STALL : STALL Handshake
bits : 21 - 21 (1 bit)
access : read-write
CNAK : Clear NAK
bits : 26 - 26 (1 bit)
access : write-only
SNAK : Set NAK
bits : 27 - 27 (1 bit)
access : write-only
SETD0PIDEF : Set DATA0 PID / Even Frame
bits : 28 - 28 (1 bit)
access : write-only
SETD1PIDOF : Set DATA1 PID / Odd Frame
bits : 29 - 29 (1 bit)
access : write-only
EPDIS : Endpoint Disable
bits : 30 - 30 (1 bit)
access : read-write
EPENA : Endpoint Enable
bits : 31 - 31 (1 bit)
access : read-write
Device OUT Endpoint x+1 Interrupt Register
address_offset : 0x3CBC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERCOMPL : Transfer Completed Interrupt
bits : 0 - 0 (1 bit)
access : read-write
EPDISBLD : Endpoint Disabled Interrupt
bits : 1 - 1 (1 bit)
access : read-write
AHBERR : AHB Error
bits : 2 - 2 (1 bit)
access : read-write
SETUP : Setup Phase Done
bits : 3 - 3 (1 bit)
access : read-write
OUTTKNEPDIS : OUT Token Received When Endpoint Disabled
bits : 4 - 4 (1 bit)
access : read-write
BACK2BACKSETUP : Back-to-Back SETUP Packets Received
bits : 6 - 6 (1 bit)
access : read-write
PKTDRPSTS : Packet Drop Status
bits : 11 - 11 (1 bit)
access : read-write
BBLEERR : Babble Error
bits : 12 - 12 (1 bit)
access : read-write
NAKINTRPT : NAK Interrupt
bits : 13 - 13 (1 bit)
access : read-write
Device OUT Endpoint x+1 Transfer Size Register
address_offset : 0x3CBD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XFERSIZE : Transfer Size
bits : 0 - 18 (19 bit)
access : read-write
PKTCNT : Packet Count
bits : 19 - 28 (10 bit)
access : read-write
RXDPIDSUPCNT : Receive Data PID / SETUP Packet Count
bits : 29 - 30 (2 bit)
access : read-only
Enumeration:
0x00000000 : DATA0
DATA0 PID.
0x00000001 : DATA2
DATA2 PID / 1 Packet.
0x00000002 : DATA1
DATA1 PID / 2 Packets.
0x00000003 : MDATA
MDATA PID / 3 Packets.
End of enumeration elements list.
Device OUT Endpoint x+1 DMA Address Register
address_offset : 0x3CBD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAADDR : DMA Address
bits : 0 - 31 (32 bit)
access : read-write
Power and Clock Gating Control Register
address_offset : 0x3CE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPPCLK : Stop PHY clock
bits : 0 - 0 (1 bit)
access : read-write
GATEHCLK : Gate HCLK
bits : 1 - 1 (1 bit)
access : read-write
PWRCLMP : Power Clamp
bits : 2 - 2 (1 bit)
access : read-write
RSTPDWNMODULE : Reset Power-Down Modules
bits : 3 - 3 (1 bit)
access : read-write
PHYSLEEP : PHY In Sleep
bits : 6 - 6 (1 bit)
access : read-only
RESETAFTERSUSP : Reset after suspend
bits : 8 - 8 (1 bit)
access : read-only
System Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VREGOS : VREGO Sense Output
bits : 0 - 0 (1 bit)
access : read-only
Interrupt Flag Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VREGOSH : VREGO Sense High Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-only
VREGOSL : VREGO Sense Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-only
Interrupt Flag Set Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VREGOSH : Set VREGO Sense High Interrupt Flag
bits : 0 - 0 (1 bit)
access : write-only
VREGOSL : Set VREGO Sense Low Interrupt Flag
bits : 1 - 1 (1 bit)
access : write-only
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