\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Watchdog Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
DEBUGRUN : Debug Mode Run Enable
bits : 1 - 1 (1 bit)
access : read-write
EM2RUN : Energy Mode 2 Run Enable
bits : 2 - 2 (1 bit)
access : read-write
EM3RUN : Energy Mode 3 Run Enable
bits : 3 - 3 (1 bit)
access : read-write
LOCK : Configuration lock
bits : 4 - 4 (1 bit)
access : read-write
EM4BLOCK : Energy Mode 4 Block
bits : 5 - 5 (1 bit)
access : read-write
SWOSCBLOCK : Software Oscillator Disable Block
bits : 6 - 6 (1 bit)
access : read-write
PERSEL : Watchdog Timeout Period Select
bits : 8 - 11 (4 bit)
access : read-write
CLKSEL : Watchdog Clock Select
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x00000000 : ULFRCO
ULFRCO
0x00000001 : LFRCO
LFRCO
0x00000002 : LFXO
LFXO
End of enumeration elements list.
Command Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLEAR : Watchdog Timer Clear
bits : 0 - 0 (1 bit)
access : write-only
Synchronization Busy Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTRL : CTRL Register Busy
bits : 0 - 0 (1 bit)
access : read-only
CMD : CMD Register Busy
bits : 1 - 1 (1 bit)
access : read-only
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