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RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

AHB1RSTR

APB1RSTR

APB2RSTR

AHB1ENR

PLLCFGR

APB1ENR

APB2ENR

AHB1LPENR

APB1LPENR

APB2LPENR

BDCR

CSR

CFGR

SSCGR

DCKCFGR

DCKCFGR2

CIR


CR

clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIRDY HSITRIM HSICAL HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

HSION : Internal high-speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : Internal high-speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSITRIM : Internal high-speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSICAL : Internal high-speed clock calibration
bits : 8 - 15 (8 bit)
access : read-only

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSE clock bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock security system enable
bits : 19 - 19 (1 bit)
access : read-write

PLLON : Main PLL (PLL) enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : Main PLL (PLL) clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


AHB1RSTR

AHB1 peripheral reset register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1RSTR AHB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOARST GPIOBRST GPIOCRST GPIOHRST CRCRST DMA1RST DMA2RST RNGRST

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

DMA1RST : DMA2 reset
bits : 21 - 21 (1 bit)

DMA2RST : DMA2 reset
bits : 22 - 22 (1 bit)

RNGRST : RNGRST
bits : 31 - 31 (1 bit)


APB1RSTR

APB1 peripheral reset register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1RSTR APB1RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM5RST TIM6RST LPTIM1RST WWDGRST SPI2RST UART2RST I2C1RST I2C2RST I2C4RST PWRRST DACRST

TIM5RST : TIM5 reset
bits : 3 - 3 (1 bit)

TIM6RST : TIM6 reset
bits : 4 - 4 (1 bit)

LPTIM1RST : LPTIM1 reset
bits : 9 - 9 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI 2 reset
bits : 14 - 14 (1 bit)

UART2RST : USART 2 reset
bits : 17 - 17 (1 bit)

I2C1RST : I2C 1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C 2 reset
bits : 22 - 22 (1 bit)

I2C4RST : I2C4 reset
bits : 24 - 24 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC reset
bits : 29 - 29 (1 bit)


APB2RSTR

APB2 peripheral reset register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2RSTR APB2RSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1RST USART1RST USART6RST ADCRST SPI1RST SYSCFGRST TIM9RST TIM11RST

TIM1RST : TIM1 reset
bits : 0 - 0 (1 bit)

USART1RST : USART1 reset
bits : 4 - 4 (1 bit)

USART6RST : USART6 reset
bits : 5 - 5 (1 bit)

ADCRST : ADC interface reset (common to all ADCs)
bits : 8 - 8 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

SYSCFGRST : System configuration controller reset
bits : 14 - 14 (1 bit)

TIM9RST : TIM9 reset
bits : 16 - 16 (1 bit)

TIM11RST : TIM11 reset
bits : 18 - 18 (1 bit)


AHB1ENR

AHB1 peripheral clock register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1ENR AHB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOAEN GPIOBEN GPIOCEN GPIOHEN CRCEN DMA1EN DMA2EN RNGEN

GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)

GPIOHEN : IO port H clock enable
bits : 7 - 7 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

DMA1EN : DMA1 clock enable
bits : 21 - 21 (1 bit)

DMA2EN : DMA2 clock enable
bits : 22 - 22 (1 bit)

RNGEN : RNG clock enable
bits : 31 - 31 (1 bit)


PLLCFGR

PLL configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCFGR PLLCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLM0 PLLM1 PLLM2 PLLM3 PLLM4 PLLM5 PLLN0 PLLN1 PLLN2 PLLN3 PLLN4 PLLN5 PLLN6 PLLN7 PLLN8 PLLP0 PLLP1 PLLSRC PLLQ0 PLLQ1 PLLQ2 PLLQ3 PLLR1 PLLR2 PLLR3

PLLM0 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 0 - 0 (1 bit)

PLLM1 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 1 - 1 (1 bit)

PLLM2 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 2 - 2 (1 bit)

PLLM3 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 3 - 3 (1 bit)

PLLM4 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 4 - 4 (1 bit)

PLLM5 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 5 - 5 (1 bit)

PLLN0 : Main PLL (PLL) multiplication factor for VCO
bits : 6 - 6 (1 bit)

PLLN1 : Main PLL (PLL) multiplication factor for VCO
bits : 7 - 7 (1 bit)

PLLN2 : Main PLL (PLL) multiplication factor for VCO
bits : 8 - 8 (1 bit)

PLLN3 : Main PLL (PLL) multiplication factor for VCO
bits : 9 - 9 (1 bit)

PLLN4 : Main PLL (PLL) multiplication factor for VCO
bits : 10 - 10 (1 bit)

PLLN5 : Main PLL (PLL) multiplication factor for VCO
bits : 11 - 11 (1 bit)

PLLN6 : Main PLL (PLL) multiplication factor for VCO
bits : 12 - 12 (1 bit)

PLLN7 : Main PLL (PLL) multiplication factor for VCO
bits : 13 - 13 (1 bit)

PLLN8 : Main PLL (PLL) multiplication factor for VCO
bits : 14 - 14 (1 bit)

PLLP0 : Main PLL (PLL) division factor for main system clock
bits : 16 - 16 (1 bit)

PLLP1 : Main PLL (PLL) division factor for main system clock
bits : 17 - 17 (1 bit)

PLLSRC : Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
bits : 22 - 22 (1 bit)

PLLQ0 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 24 - 24 (1 bit)

PLLQ1 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 25 - 25 (1 bit)

PLLQ2 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 26 - 26 (1 bit)

PLLQ3 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 27 - 27 (1 bit)

PLLR1 : PLLR1
bits : 28 - 28 (1 bit)

PLLR2 : PLLR2
bits : 29 - 29 (1 bit)

PLLR3 : PLLR3
bits : 30 - 30 (1 bit)


APB1ENR

APB1 peripheral clock enable register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1ENR APB1ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM5EN TIM6EN LPTIM1EN RTCAPBEN WWDGEN SPI2EN USART2EN I2C1EN I2C2EN I2C4EN PWREN DACEN

TIM5EN : TIM5 clock enable
bits : 3 - 3 (1 bit)

TIM6EN : TIM6 clock enable
bits : 4 - 4 (1 bit)

LPTIM1EN : LPTIM1 clock enable
bits : 9 - 9 (1 bit)

RTCAPBEN : RTC APB clock enable
bits : 10 - 10 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)

USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)

I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)

I2C4EN : I2C4 clock enable
bits : 24 - 24 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)


APB2ENR

APB2 peripheral clock enable register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2ENR APB2ENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1EN USART1EN USART6EN ADC1EN SPI1EN SYSCFGEN EXTITEN TIM9EN TIM11EN SPI5EN

TIM1EN : TIM1 clock enable
bits : 0 - 0 (1 bit)

USART1EN : USART1 clock enable
bits : 4 - 4 (1 bit)

USART6EN : USART6 clock enable
bits : 5 - 5 (1 bit)

ADC1EN : ADC1 clock enable
bits : 8 - 8 (1 bit)

SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)

SYSCFGEN : System configuration controller clock enable
bits : 14 - 14 (1 bit)

EXTITEN : EXTI ans external IT clock enable
bits : 15 - 15 (1 bit)

TIM9EN : TIM9 clock enable
bits : 16 - 16 (1 bit)

TIM11EN : TIM11 clock enable
bits : 18 - 18 (1 bit)

SPI5EN : SPI5 clock enable
bits : 20 - 20 (1 bit)


AHB1LPENR

AHB1 peripheral clock enable in low power mode register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB1LPENR AHB1LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOALPEN GPIOBLPEN GPIOCLPEN GPIOHLPEN CRCLPEN FLITFLPEN SRAM1LPEN DMA1LPEN DMA2LPEN RNGLPEN

GPIOALPEN : IO port A clock enable during sleep mode
bits : 0 - 0 (1 bit)

GPIOBLPEN : IO port B clock enable during Sleep mode
bits : 1 - 1 (1 bit)

GPIOCLPEN : IO port C clock enable during Sleep mode
bits : 2 - 2 (1 bit)

GPIOHLPEN : IO port H clock enable during Sleep mode
bits : 7 - 7 (1 bit)

CRCLPEN : CRC clock enable during Sleep mode
bits : 12 - 12 (1 bit)

FLITFLPEN : Flash interface clock enable during Sleep mode
bits : 15 - 15 (1 bit)

SRAM1LPEN : SRAM 1interface clock enable during Sleep mode
bits : 16 - 16 (1 bit)

DMA1LPEN : DMA1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

DMA2LPEN : DMA2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

RNGLPEN : RNG clock enable during sleep mode
bits : 31 - 31 (1 bit)


APB1LPENR

APB1 peripheral clock enable in low power mode register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1LPENR APB1LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM5LPEN TIM6LPEN LPTIM1LPEN RTCAPBLPEN WWDGLPEN SPI2LPEN USART2LPEN I2C1LPEN I2C2LPEN I2C4LPEN PWRLPEN DACLPEN

TIM5LPEN : TIM5 clock enable during Sleep mode
bits : 3 - 3 (1 bit)

TIM6LPEN : TIM6 clock enable during Sleep mode
bits : 4 - 4 (1 bit)

LPTIM1LPEN : LPTIM1 clock enable during sleep mode
bits : 9 - 9 (1 bit)

RTCAPBLPEN : RTC APB clock enable during sleep mode
bits : 10 - 10 (1 bit)

WWDGLPEN : Window watchdog clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI2LPEN : SPI2 clock enable during Sleep mode
bits : 14 - 14 (1 bit)

USART2LPEN : USART2 clock enable during Sleep mode
bits : 17 - 17 (1 bit)

I2C1LPEN : I2C1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

I2C2LPEN : I2C2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

I2C4LPEN : I2C4 clock enable during Sleep mode
bits : 24 - 24 (1 bit)

PWRLPEN : Power interface clock enable during Sleep mode
bits : 28 - 28 (1 bit)

DACLPEN : DAC interface clock enable during sleep mode
bits : 29 - 29 (1 bit)


APB2LPENR

APB2 peripheral clock enabled in low power mode register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2LPENR APB2LPENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM1LPEN USART1LPEN USART6LPEN ADC1LPEN SDIOLPEN SPI1LPEN SYSCFGLPEN EXTITLPEN TIM9LPEN TIM11LPEN

TIM1LPEN : TIM1 clock enable during Sleep mode
bits : 0 - 0 (1 bit)

USART1LPEN : USART1 clock enable during Sleep mode
bits : 4 - 4 (1 bit)

USART6LPEN : USART6 clock enable during Sleep mode
bits : 5 - 5 (1 bit)

ADC1LPEN : ADC1 clock enable during Sleep mode
bits : 8 - 8 (1 bit)

SDIOLPEN : SDIO clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI1LPEN : SPI 1 clock enable during Sleep mode
bits : 12 - 12 (1 bit)

SYSCFGLPEN : System configuration controller clock enable during Sleep mode
bits : 14 - 14 (1 bit)

EXTITLPEN : EXTI and External IT clock enable during sleep mode
bits : 15 - 15 (1 bit)

TIM9LPEN : TIM9 clock enable during sleep mode
bits : 16 - 16 (1 bit)

TIM11LPEN : TIM11 clock enable during Sleep mode
bits : 18 - 18 (1 bit)


BDCR

Backup domain control register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDCR BDCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP RTCSEL0 RTCSEL1 RTCEN BDRST

LSEON : External low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : External low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : External low-speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

RTCSEL0 : RTC clock source selection
bits : 8 - 8 (1 bit)
access : read-write

RTCSEL1 : RTC clock source selection
bits : 9 - 9 (1 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write


CSR

clock control and status register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY RMVF BORRSTF PADRSTF PORRSTF SFTRSTF WDGRSTF WWDGRSTF LPWRRSTF

LSION : Internal low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

BORRSTF : BOR reset flag
bits : 25 - 25 (1 bit)
access : read-write

PADRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

WDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


CFGR

clock configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW0 SW1 SWS0 SWS1 HPRE MCO1EN MCO2EN PPRE1 PPRE2 RTCPRE MCO1 MCO1PRE MCO2PRE MCO2

SW0 : System clock switch
bits : 0 - 0 (1 bit)
access : read-write

SW1 : System clock switch
bits : 1 - 1 (1 bit)
access : read-write

SWS0 : System clock switch status
bits : 2 - 2 (1 bit)
access : read-only

SWS1 : System clock switch status
bits : 3 - 3 (1 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

MCO1EN : MCO output enable
bits : 8 - 8 (1 bit)
access : read-write

MCO2EN : MCO output enable
bits : 9 - 9 (1 bit)
access : read-write

PPRE1 : APB Low speed prescaler (APB1)
bits : 10 - 12 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 13 - 15 (3 bit)
access : read-write

RTCPRE : HSE division factor for RTC clock
bits : 16 - 20 (5 bit)
access : read-write

MCO1 : Microcontroller clock output 1
bits : 21 - 22 (2 bit)
access : read-write

MCO1PRE : MCO1 prescaler
bits : 24 - 26 (3 bit)
access : read-write

MCO2PRE : MCO2 prescaler
bits : 27 - 29 (3 bit)
access : read-write

MCO2 : Microcontroller clock output 2
bits : 30 - 31 (2 bit)
access : read-write


SSCGR

spread spectrum clock generation register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSCGR SSCGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODPER INCSTEP SPREADSEL SSCGEN

MODPER : Modulation period
bits : 0 - 12 (13 bit)

INCSTEP : Incrementation step
bits : 13 - 27 (15 bit)

SPREADSEL : Spread Select
bits : 30 - 30 (1 bit)

SSCGEN : Spread spectrum modulation enable
bits : 31 - 31 (1 bit)


DCKCFGR

DCKCFGR register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCKCFGR DCKCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMPRE I2SSRC

TIMPRE : TIMPRE
bits : 24 - 24 (1 bit)

I2SSRC : I2SSRC
bits : 25 - 26 (2 bit)


DCKCFGR2

DCKCFGR2 register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCKCFGR2 DCKCFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C4SEL LPTIM1SEL

I2C4SEL : I2C4SEL
bits : 22 - 23 (2 bit)

LPTIM1SEL : LPTIM1SEL
bits : 30 - 31 (2 bit)


CIR

clock interrupt register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CIR CIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF CSSF LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE LSIRDYC LSERDYC HSIRDYC HSERDYC PLLRDYC PLLI2SRDYC CSSC

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSI ready interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE ready interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : Main PLL (PLL) ready interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

CSSF : Clock security system interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI ready interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSE ready interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSI ready interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE ready interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : Main PLL (PLL) ready interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

LSIRDYC : LSI ready interrupt clear
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSE ready interrupt clear
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSI ready interrupt clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE ready interrupt clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : Main PLL(PLL) ready interrupt clear
bits : 20 - 20 (1 bit)
access : write-only

PLLI2SRDYC : PLLI2S ready interrupt clear
bits : 21 - 21 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only



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