\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
No Description
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0 : Software Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write
SW1 : Software Interrupt 1
bits : 1 - 1 (1 bit)
access : read-write
SW2 : Software Interrupt 2
bits : 2 - 2 (1 bit)
access : read-write
SW3 : Software Interrupt 3
bits : 3 - 3 (1 bit)
access : read-write
RAMERR1B : RAM 1-bit ECC Error Interrupt flag
bits : 16 - 16 (1 bit)
access : read-write
RAMERR2B : RAM 2-bit ECC Error Interrupt flag
bits : 17 - 17 (1 bit)
access : read-write
SEQRAMERR1B : SEQRAM 1-bit ECC Error Interrupt flag
bits : 24 - 24 (1 bit)
access : read-write
SEQRAMERR2B : SEQRAM 2-bit ECC Error Interrupt flag
bits : 25 - 25 (1 bit)
access : read-write
FRCRAMERR1BIF : FRCRAM 1-bit ECC Error Interrupt flag
bits : 28 - 28 (1 bit)
access : read-write
FRCRAMERR2BIF : FRCRAM 2-bit ECC Error Interrupt flag
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Chip Rev Major value
bits : 0 - 5 (6 bit)
access : read-write
FAMILY : Chip Family value
bits : 6 - 11 (6 bit)
access : read-write
MINOR : Chip Rev Minor value
bits : 12 - 19 (8 bit)
access : read-write
No Description
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Part Revision Major value
bits : 0 - 5 (6 bit)
access : read-write
FAMILY : Part Family value
bits : 6 - 11 (6 bit)
access : read-write
MINOR : Part Revision Minor value
bits : 12 - 19 (8 bit)
access : read-write
No Description
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRFAULTEN : Invalid Address Bus Fault Response Enable
bits : 0 - 0 (1 bit)
access : read-write
RAMECCERRFAULTEN : Two bit ECC Error Bus Fault Response Enable
bits : 5 - 5 (1 bit)
access : read-write
No Description
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMRETNCTRL : DMEM0 blockset retention control
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : ALLON
None of the RAM blocks powered down
16 : BLK5
Power down RAM block 5 (address range 0x20014000-0x20017FFF)
24 : BLK4TO5
Power down RAM blocks 4 and above (address range 0x20010000-0x20017FFF)
28 : BLK3TO5
Power down RAM blocks 3 and above (address range 0x2000C000-0x20017FFF)
30 : BLK2TO5
Power down RAM blocks 2 and above (address range 0x20008000-0x20017FFF)
31 : BLK1TO5
Power down RAM blocks 1 and above (address range 0x20004000-0x20017FFF)
End of enumeration elements list.
No Description
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DMEM0ECCADDR : DMEM0 RAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMECCEWEN : RAM ECC Write Enable
bits : 0 - 0 (1 bit)
access : read-write
RAMECCCHKEN : RAM ECC Check Enable
bits : 1 - 1 (1 bit)
access : read-write
No Description
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMCACHEEN : RAM CACHE Enable
bits : 0 - 0 (1 bit)
access : read-write
RAMWSEN : RAM WAIT STATE Enable
bits : 1 - 1 (1 bit)
access : read-write
RAMPREFETCHEN : RAM Prfetch Enable
bits : 2 - 2 (1 bit)
access : read-write
No Description
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSTICEXTCLKEN : SysTick External Clock Enable
bits : 0 - 0 (1 bit)
access : read-write
No Description
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SW0 : Software interrupt 0
bits : 0 - 0 (1 bit)
access : read-write
SW1 : Software interrupt 1
bits : 1 - 1 (1 bit)
access : read-write
SW2 : Software interrupt 2
bits : 2 - 2 (1 bit)
access : read-write
SW3 : Software interrupt 3
bits : 3 - 3 (1 bit)
access : read-write
RAMERR1B : RAM 1-bit ECC Error Interrupt enable
bits : 16 - 16 (1 bit)
access : read-write
RAMERR2B : RAM 2-bit ECC Error Interrupt enable
bits : 17 - 17 (1 bit)
access : read-write
SEQRAMERR1B : SEQRAM 1-bit ECC Error Interrupt enable
bits : 24 - 24 (1 bit)
access : read-write
SEQRAMERR2B : SEQRAM 2-bit ECC Error Interrupt enable
bits : 25 - 25 (1 bit)
access : read-write
FRCRAMERR1BIEN : FRCRAM 1-bit ECC Error Interrupt enable
bits : 28 - 28 (1 bit)
access : read-write
FRCRAMERR2BIEN : FRCRAM 2-bit ECC Error Interrupt enable
bits : 29 - 29 (1 bit)
access : read-write
No Description
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQRAMRETNCTRL : SEQRAM Memory Shutdown Control Register
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : ALLON
SEQRAM not powered down
1 : SEQBLK
Power down SEQRAM (address range 0x50000000-0x50001FFF)
End of enumeration elements list.
FRCRAMRETNCTRL : FRCRAM Memory Shutdown Control Register
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : ALLON
FRCRAM not powered down
1 : FRCBLK
Power down FRCRAM (address range 0x50002000-0x50002FFF)
End of enumeration elements list.
No Description
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQRAMECCEWEN : SEQRAM ECC Write Enable
bits : 0 - 0 (1 bit)
access : read-write
SEQRAMECCCHKEN : SEQRAM ECC Check Enable
bits : 1 - 1 (1 bit)
access : read-write
FRCRAMECCEWEN : FRCRAM ECC Write Enable
bits : 8 - 8 (1 bit)
access : read-write
FRCRAMECCCHKEN : FRCRAM ECC Check Enable
bits : 9 - 9 (1 bit)
access : read-write
No Description
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEQRAMCACHEEN : SEQRAM CACHE Enable
bits : 0 - 0 (1 bit)
access : read-write
SEQRAMWSEN : SEQRAM WAIT STATE Enable
bits : 1 - 1 (1 bit)
access : read-write
SEQRAMPREFETCHEN : SEQRAM Prfetch Enable
bits : 2 - 2 (1 bit)
access : read-write
FRCRAMCACHEEN : FRCRAM CACHE Enable
bits : 16 - 16 (1 bit)
access : read-write
FRCRAMWSEN : FRCRAM WAIT STATE Enable
bits : 17 - 17 (1 bit)
access : read-write
FRCRAMPREFETCHEN : FRCRAM Prfetch Enable
bits : 18 - 18 (1 bit)
access : read-write
DEMODRAMCACHEEN : DEMODRAM CACHE Enable
bits : 24 - 24 (1 bit)
access : read-write
No Description
address_offset : 0x410 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEQRAMECCADDR : SEQRAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only
No Description
address_offset : 0x414 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRCRAMECCADDR : FRCRAM ECC Error Address
bits : 0 - 31 (32 bit)
access : read-only
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